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MIPS: CI20: Reduce clocksource to 750 kHz. 

The original clock (3 MHz) is too fast for the clocksource,
there will be a chance that the system may get stuck.

Reported-by: Nikolaus Schaller <hns@goldelico.com>
Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
周琰杰 (Zhou Yanjie) 2021-06-26 14:18:40 +08:00 committed by Thomas Bogendoerfer
parent ab3040e137
commit 23c64447b3
1 changed files with 2 additions and 2 deletions
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4
arch/mips/boot/dts/ingenic/ci20.dts
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@ -525,10 +525,10 @@
&tcu {
/*
* 750 kHz for the system timer and 3 MHz for the clocksource,
* 750 kHz for the system timer and clocksource,
* use channel #0 for the system timer, #1 for the clocksource.
*/
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
<&tcu TCU_CLK_OST>;
assigned-clock-rates = <750000>, <3000000>, <3000000>;
assigned-clock-rates = <750000>, <750000>, <3000000>;
};