phy: sparx5-serdes: reorder CMU functions
Reorder CMU functions, as some of them are now required by the serdes functions. No functional changes. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-4-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Daniel Machon
Vinod Koul
parent
3d61a1f83e
commit
238a583fe4
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@ -925,6 +925,159 @@ static void sparx5_sd10g28_get_params(struct sparx5_serdes_macro *macro,
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*params = init;
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*params = init;
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}
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}
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static int sparx5_cmu_apply_cfg(struct sparx5_serdes_private *priv,
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u32 cmu_idx,
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void __iomem *cmu_tgt,
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void __iomem *cmu_cfg_tgt,
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u32 spd10g)
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{
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void __iomem **regs = priv->regs;
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struct device *dev = priv->dev;
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int value;
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cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx);
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cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx);
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if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 ||
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cmu_idx == 10 || cmu_idx == 13) {
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spd10g = 0;
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}
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sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(1),
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SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST,
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cmu_cfg_tgt,
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SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0),
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SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST,
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cmu_cfg_tgt,
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SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(1),
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SD_CMU_CFG_SD_CMU_CFG_CMU_RST,
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cmu_cfg_tgt,
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SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) |
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SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(0x1) |
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SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(0x1) |
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SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(0x1) |
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SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(0x0),
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SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT |
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SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT |
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SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT |
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SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT |
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SD_CMU_CMU_45_R_EN_RATECHG_CTRL,
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cmu_tgt,
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SD_CMU_CMU_45(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0),
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SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0,
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cmu_tgt,
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SD_CMU_CMU_47(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0),
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SD_CMU_CMU_1B_CFG_RESERVE_7_0,
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cmu_tgt,
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SD_CMU_CMU_1B(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1),
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SD_CMU_CMU_0D_CFG_JC_BYP,
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cmu_tgt,
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SD_CMU_CMU_0D(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(1),
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SD_CMU_CMU_1F_CFG_VTUNE_SEL,
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cmu_tgt,
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SD_CMU_CMU_1F(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(3),
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SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0,
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cmu_tgt,
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SD_CMU_CMU_00(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(3),
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SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0,
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cmu_tgt,
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SD_CMU_CMU_05(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(1),
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SD_CMU_CMU_30_R_PLL_DLOL_EN,
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cmu_tgt,
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SD_CMU_CMU_30(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_09_CFG_SW_10G_SET(spd10g),
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SD_CMU_CMU_09_CFG_SW_10G,
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cmu_tgt,
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SD_CMU_CMU_09(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(0),
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SD_CMU_CFG_SD_CMU_CFG_CMU_RST,
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cmu_cfg_tgt,
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SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
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msleep(20);
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sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(0),
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SD_CMU_CMU_44_R_PLL_RSTN,
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cmu_tgt,
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SD_CMU_CMU_44(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(1),
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SD_CMU_CMU_44_R_PLL_RSTN,
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cmu_tgt,
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SD_CMU_CMU_44(cmu_idx));
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msleep(20);
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value = readl(sdx5_addr(regs, SD_CMU_CMU_E0(cmu_idx)));
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value = SD_CMU_CMU_E0_PLL_LOL_UDL_GET(value);
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if (value) {
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dev_err(dev, "CMU PLL Loss of Lock: 0x%x\n", value);
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return -EINVAL;
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}
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sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(0),
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SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD,
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cmu_tgt,
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SD_CMU_CMU_0D(cmu_idx));
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return 0;
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}
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static int sparx5_cmu_cfg(struct sparx5_serdes_private *priv, u32 cmu_idx)
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{
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void __iomem *cmu_tgt, *cmu_cfg_tgt;
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u32 spd10g = 1;
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if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 ||
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cmu_idx == 10 || cmu_idx == 13) {
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spd10g = 0;
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}
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cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx);
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cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx);
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return sparx5_cmu_apply_cfg(priv, cmu_idx, cmu_tgt, cmu_cfg_tgt, spd10g);
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}
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static int sparx5_serdes_cmu_enable(struct sparx5_serdes_private *priv)
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{
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int idx, err = 0;
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if (!priv->cmu_enabled) {
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for (idx = 0; idx < SPX5_CMU_MAX; idx++) {
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err = sparx5_cmu_cfg(priv, idx);
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if (err) {
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dev_err(priv->dev, "CMU %u, error: %d\n", idx, err);
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goto leave;
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}
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}
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priv->cmu_enabled = true;
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}
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leave:
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return err;
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}
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static void sparx5_sd25g28_reset(void __iomem *regs[],
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static void sparx5_sd25g28_reset(void __iomem *regs[],
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struct sparx5_sd25g28_params *params,
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struct sparx5_sd25g28_params *params,
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u32 sd_index)
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u32 sd_index)
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@ -1966,159 +2119,6 @@ static int sparx5_serdes_clock_config(struct sparx5_serdes_macro *macro)
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return 0;
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return 0;
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}
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}
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static int sparx5_cmu_apply_cfg(struct sparx5_serdes_private *priv,
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u32 cmu_idx,
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void __iomem *cmu_tgt,
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void __iomem *cmu_cfg_tgt,
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u32 spd10g)
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{
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void __iomem **regs = priv->regs;
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struct device *dev = priv->dev;
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int value;
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cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx);
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cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx);
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if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 ||
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cmu_idx == 10 || cmu_idx == 13) {
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spd10g = 0;
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}
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sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(1),
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SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST,
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cmu_cfg_tgt,
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SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0),
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SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST,
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cmu_cfg_tgt,
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SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(1),
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SD_CMU_CFG_SD_CMU_CFG_CMU_RST,
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cmu_cfg_tgt,
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SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) |
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SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(0x1) |
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SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(0x1) |
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SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(0x1) |
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SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(0x0),
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SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT |
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SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT |
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SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT |
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SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT |
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SD_CMU_CMU_45_R_EN_RATECHG_CTRL,
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cmu_tgt,
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SD_CMU_CMU_45(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0),
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SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0,
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cmu_tgt,
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SD_CMU_CMU_47(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0),
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SD_CMU_CMU_1B_CFG_RESERVE_7_0,
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cmu_tgt,
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SD_CMU_CMU_1B(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1),
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SD_CMU_CMU_0D_CFG_JC_BYP,
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cmu_tgt,
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SD_CMU_CMU_0D(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(1),
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SD_CMU_CMU_1F_CFG_VTUNE_SEL,
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cmu_tgt,
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SD_CMU_CMU_1F(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(3),
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SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0,
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cmu_tgt,
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SD_CMU_CMU_00(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(3),
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SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0,
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cmu_tgt,
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SD_CMU_CMU_05(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(1),
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SD_CMU_CMU_30_R_PLL_DLOL_EN,
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cmu_tgt,
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SD_CMU_CMU_30(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_09_CFG_SW_10G_SET(spd10g),
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SD_CMU_CMU_09_CFG_SW_10G,
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cmu_tgt,
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SD_CMU_CMU_09(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(0),
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SD_CMU_CFG_SD_CMU_CFG_CMU_RST,
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cmu_cfg_tgt,
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SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
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msleep(20);
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sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(0),
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SD_CMU_CMU_44_R_PLL_RSTN,
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cmu_tgt,
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SD_CMU_CMU_44(cmu_idx));
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sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(1),
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SD_CMU_CMU_44_R_PLL_RSTN,
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cmu_tgt,
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SD_CMU_CMU_44(cmu_idx));
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msleep(20);
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value = readl(sdx5_addr(regs, SD_CMU_CMU_E0(cmu_idx)));
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value = SD_CMU_CMU_E0_PLL_LOL_UDL_GET(value);
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if (value) {
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dev_err(dev, "CMU PLL Loss of Lock: 0x%x\n", value);
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return -EINVAL;
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}
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sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(0),
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SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD,
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cmu_tgt,
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SD_CMU_CMU_0D(cmu_idx));
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return 0;
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}
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static int sparx5_cmu_cfg(struct sparx5_serdes_private *priv, u32 cmu_idx)
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{
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void __iomem *cmu_tgt, *cmu_cfg_tgt;
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u32 spd10g = 1;
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if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 ||
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cmu_idx == 10 || cmu_idx == 13) {
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spd10g = 0;
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}
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cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx);
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cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx);
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return sparx5_cmu_apply_cfg(priv, cmu_idx, cmu_tgt, cmu_cfg_tgt, spd10g);
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}
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|
||||||
static int sparx5_serdes_cmu_enable(struct sparx5_serdes_private *priv)
|
|
||||||
{
|
|
||||||
int idx, err = 0;
|
|
||||||
|
|
||||||
if (!priv->cmu_enabled) {
|
|
||||||
for (idx = 0; idx < SPX5_CMU_MAX; idx++) {
|
|
||||||
err = sparx5_cmu_cfg(priv, idx);
|
|
||||||
if (err) {
|
|
||||||
dev_err(priv->dev, "CMU %u, error: %d\n", idx, err);
|
|
||||||
goto leave;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
priv->cmu_enabled = true;
|
|
||||||
}
|
|
||||||
leave:
|
|
||||||
return err;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int sparx5_serdes_get_serdesmode(phy_interface_t portmode, int speed)
|
static int sparx5_serdes_get_serdesmode(phy_interface_t portmode, int speed)
|
||||||
{
|
{
|
||||||
switch (portmode) {
|
switch (portmode) {
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue