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ARM: dts: stm32: fix timer nodes on STM32 MCU to prevent warnings 

Prevent warning seen with "make dtbs_check W=1" command:

Warning (avoid_unnecessary_addr_size): /soc/timers@40001c00: unnecessary
address-cells/size-cells without "ranges" or child "reg" property

Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This commit is contained in:
Alexandre Torgue 2021-04-15 12:10:27 +02:00
parent e4b948415a
commit 2388f14d87
3 changed files with 0 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/boot/dts/stm32f429.dtsi
View File

@ -283,8 +283,6 @@
}; };
timers13: timers@40001c00 { timers13: timers@40001c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>; reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
@ -299,8 +297,6 @@
}; };
timers14: timers@40002000 { timers14: timers@40002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40002000 0x400>; reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
@ -633,8 +629,6 @@
}; };
timers10: timers@40014400 { timers10: timers@40014400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40014400 0x400>; reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
@ -649,8 +643,6 @@
}; };
timers11: timers@40014800 { timers11: timers@40014800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40014800 0x400>; reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;

8
arch/arm/boot/dts/stm32f746.dtsi
View File

@ -265,8 +265,6 @@
}; };
timers13: timers@40001c00 { timers13: timers@40001c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>; reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
@ -281,8 +279,6 @@
}; };
timers14: timers@40002000 { timers14: timers@40002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40002000 0x400>; reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
@ -531,8 +527,6 @@
}; };
timers10: timers@40014400 { timers10: timers@40014400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40014400 0x400>; reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
@ -547,8 +541,6 @@
}; };
timers11: timers@40014800 { timers11: timers@40014800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40014800 0x400>; reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;

4
arch/arm/boot/dts/stm32h743.dtsi
View File

@ -485,8 +485,6 @@
}; };
lptimer4: timer@58002c00 { lptimer4: timer@58002c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer"; compatible = "st,stm32-lptimer";
reg = <0x58002c00 0x400>; reg = <0x58002c00 0x400>;
clocks = <&rcc LPTIM4_CK>; clocks = <&rcc LPTIM4_CK>;
@ -501,8 +499,6 @@
}; };
lptimer5: timer@58003000 { lptimer5: timer@58003000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer"; compatible = "st,stm32-lptimer";
reg = <0x58003000 0x400>; reg = <0x58003000 0x400>;
clocks = <&rcc LPTIM5_CK>; clocks = <&rcc LPTIM5_CK>;