drm/amdgpu: use RREG32_KIQ to read register when get cg state
Use RREG32_KIQ to read gfx register when try to get gfx/sdma clockgating state instead of RREG32, as it will result to system hard hang when GPU is enter into GFXOFF state. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -7481,12 +7481,12 @@ static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
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int data;
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/* AMD_CG_SUPPORT_GFX_MGCG */
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data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
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data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
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if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
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*flags |= AMD_CG_SUPPORT_GFX_MGCG;
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/* AMD_CG_SUPPORT_GFX_CGCG */
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data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
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data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
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if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
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*flags |= AMD_CG_SUPPORT_GFX_CGCG;
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@ -7495,17 +7495,17 @@ static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
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*flags |= AMD_CG_SUPPORT_GFX_CGLS;
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/* AMD_CG_SUPPORT_GFX_RLC_LS */
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data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
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data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
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if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
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*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
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/* AMD_CG_SUPPORT_GFX_CP_LS */
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data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
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data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
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if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
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*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
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/* AMD_CG_SUPPORT_GFX_3D_CGCG */
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data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
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data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
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if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
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*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
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@ -1572,7 +1572,7 @@ static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
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*flags = 0;
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/* AMD_CG_SUPPORT_SDMA_LS */
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data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
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data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
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if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
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*flags |= AMD_CG_SUPPORT_SDMA_LS;
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}
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