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Samsung DTS ARM64 changes for v5.19, part two 

1. Cleanups: unused and undocumented dma-channels and dma-requests.
 2. Add clock controllers to ExynosAutov9.
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Merge tag 'samsung-dt64-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Samsung DTS ARM64 changes for v5.19, part two

1. Cleanups: unused and undocumented dma-channels and dma-requests.
2. Add clock controllers to ExynosAutov9.

* tag 'samsung-dt64-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos: switch UFS clock node in ExynosAutov9
  arm64: dts: exynos: switch USI clocks in ExynosAutov9
  arm64: dts: exynos: add initial CMU clock nodes in ExynosAutov9
  dt-bindings: clock: add Exynos Auto v9 SoC CMU bindings
  dt-bindings: clock: add clock binding definitions for Exynos Auto v9
  arm64: dts: fsd: drop useless 'dma-channels/requests' properties
  arm64: dts: exynos: drop useless 'dma-channels/requests' properties
  arm64: dts: exynos: move XTCXO clock frequency to board in Exynos Auto v9

Link: https://lore.kernel.org/r/20220506081438.149192-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-05-06 22:26:28 +02:00
parent c86071e890 9882948322
commit 2367ee1ab9
7 changed files with 612 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

219
Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml Normal file
View File

@ -0,0 +1,219 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos Auto v9 SoC clock controller
maintainers:
- Chanho Park <chanho61.park@samsung.com>
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
Exynos Auto v9 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. Root clocks in that clock tree are
two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
The external OSCCLK must be defined as fixed-rate clock in dts.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
dividers; all other clocks of function blocks (other CMUs) are usually
derived from CMU_TOP.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'include/dt-bindings/clock/samsung,exynosautov9.h' header.
properties:
compatible:
enum:
- samsung,exynosautov9-cmu-top
- samsung,exynosautov9-cmu-busmc
- samsung,exynosautov9-cmu-core
- samsung,exynosautov9-cmu-fsys2
- samsung,exynosautov9-cmu-peric0
- samsung,exynosautov9-cmu-peric1
- samsung,exynosautov9-cmu-peris
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
maxItems: 5
"#clock-cells":
const: 1
reg:
maxItems: 1
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-top
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
clock-names:
items:
- const: oscclk
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-busmc
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_BUSMC bus clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_busmc_bus
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-core
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_CORE bus clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_core_bus
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-fsys2
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_FSYS2 bus clock (from CMU_TOP)
- description: UFS clock (from CMU_TOP)
- description: Ethernet clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_fsys2_bus
- const: dout_fsys2_clkcmu_ufs_embd
- const: dout_fsys2_clkcmu_ethernet
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-peric0
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERIC0 bus clock (from CMU_TOP)
- description: PERIC0 IP clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_peric0_bus
- const: dout_clkcmu_peric0_ip
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-peric1
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERIC1 bus clock (from CMU_TOP)
- description: PERIC1 IP clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_peric1_bus
- const: dout_clkcmu_peric1_ip
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-peris
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERIS bus clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_peris_bus
required:
- compatible
- "#clock-cells"
- clocks
- clock-names
- reg
additionalProperties: false
examples:
# Clock controller node for CMU_FSYS2
- |
#include <dt-bindings/clock/samsung,exynosautov9.h>
cmu_fsys2: clock-controller@17c00000 {
compatible = "samsung,exynosautov9-cmu-fsys2";
reg = <0x17c00000 0x8000>;
#clock-cells = <1>;
clocks = <&xtcxo>,
<&cmu_top DOUT_CLKCMU_FSYS2_BUS>,
<&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,
<&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;
clock-names = "oscclk",
"dout_clkcmu_fsys2_bus",
"dout_fsys2_clkcmu_ufs_embd",
"dout_fsys2_clkcmu_ethernet";
};
...

6
arch/arm64/boot/dts/exynos/exynos5433.dtsi
View File

@ -1866,8 +1866,6 @@
clocks = <&cmu_fsys CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: dma-controller@15600000 {
@ -1877,8 +1875,6 @@
clocks = <&cmu_fsys CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
audio-subsystem@11400000 {
@ -1898,8 +1894,6 @@
clocks = <&cmu_aud CLK_ACLK_DMAC>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
power-domains = <&pd_aud>;
};

4
arch/arm64/boot/dts/exynos/exynos7.dtsi
View File

@ -149,8 +149,6 @@
clocks = <&clock_fsys0 ACLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: dma-controller@10eb0000 {
@ -160,8 +158,6 @@
clocks = <&clock_fsys0 ACLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
clock_topc: clock-controller@10570000 {

4
arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts
View File

@ -58,3 +58,7 @@
&usi_0 {
status = "okay";
};
&xtcxo {
clock-frequency = <26000000>;
};

116
arch/arm64/boot/dts/exynos/exynosautov9.dtsi
View File

@ -6,6 +6,7 @@
*
*/
#include <dt-bindings/clock/samsung,exynosautov9.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/samsung,exynos-usi.h>
@ -153,30 +154,8 @@
xtcxo: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "oscclk";
};
/*
* Keep the stub clock for serial driver, until proper clock
* driver is implemented.
*/
uart_clock: uart-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133250000>;
clock-output-names = "uart";
};
/*
* Keep the stub clock for ufs driver, until proper clock
* driver is implemented.
*/
ufs_core_clock: ufs-core-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <166562500>;
};
};
soc: soc@0 {
@ -190,6 +169,89 @@
reg = <0x10000000 0x24>;
};
cmu_peris: clock-controller@10020000 {
compatible = "samsung,exynosautov9-cmu-peris";
reg = <0x10020000 0x8000>;
#clock-cells = <1>;
clocks = <&xtcxo>,
<&cmu_top DOUT_CLKCMU_PERIS_BUS>;
clock-names = "oscclk",
"dout_clkcmu_peris_bus";
};
cmu_peric0: clock-controller@10200000 {
compatible = "samsung,exynosautov9-cmu-peric0";
reg = <0x10200000 0x8000>;
#clock-cells = <1>;
clocks = <&xtcxo>,
<&cmu_top DOUT_CLKCMU_PERIC0_BUS>,
<&cmu_top DOUT_CLKCMU_PERIC0_IP>;
clock-names = "oscclk",
"dout_clkcmu_peric0_bus",
"dout_clkcmu_peric0_ip";
};
cmu_peric1: clock-controller@10800000 {
compatible = "samsung,exynosautov9-cmu-peric1";
reg = <0x10800000 0x8000>;
#clock-cells = <1>;
clocks = <&xtcxo>,
<&cmu_top DOUT_CLKCMU_PERIC1_BUS>,
<&cmu_top DOUT_CLKCMU_PERIC1_IP>;
clock-names = "oscclk",
"dout_clkcmu_peric1_bus",
"dout_clkcmu_peric1_ip";
};
cmu_fsys2: clock-controller@17c00000 {
compatible = "samsung,exynosautov9-cmu-fsys2";
reg = <0x17c00000 0x8000>;
#clock-cells = <1>;
clocks = <&xtcxo>,
<&cmu_top DOUT_CLKCMU_FSYS2_BUS>,
<&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,
<&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;
clock-names = "oscclk",
"dout_clkcmu_fsys2_bus",
"dout_fsys2_clkcmu_ufs_embd",
"dout_fsys2_clkcmu_ethernet";
};
cmu_core: clock-controller@1b030000 {
compatible = "samsung,exynosautov9-cmu-core";
reg = <0x1b030000 0x8000>;
#clock-cells = <1>;
clocks = <&xtcxo>,
<&cmu_top DOUT_CLKCMU_CORE_BUS>;
clock-names = "oscclk",
"dout_clkcmu_core_bus";
};
cmu_busmc: clock-controller@1b200000 {
compatible = "samsung,exynosautov9-cmu-busmc";
reg = <0x1b200000 0x8000>;
#clock-cells = <1>;
clocks = <&xtcxo>,
<&cmu_top DOUT_CLKCMU_BUSMC_BUS>;
clock-names = "oscclk",
"dout_clkcmu_busmc_bus";
};
cmu_top: clock-controller@1b240000 {
compatible = "samsung,exynosautov9-cmu-top";
reg = <0x1b240000 0x8000>;
#clock-cells = <1>;
clocks = <&xtcxo>;
clock-names = "oscclk";
};
gic: interrupt-controller@10101000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@ -271,7 +333,8 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&uart_clock>, <&uart_clock>;
clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>,
<&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>;
clock-names = "pclk", "ipclk";
status = "disabled";
@ -282,7 +345,8 @@
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_bus_dual>;
clocks = <&uart_clock>, <&uart_clock>;
clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>,
<&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
@ -308,8 +372,8 @@
<0x17dc0000 0x2200>; /* 3: UFS protector */
reg-names = "hci", "vs_hci", "unipro", "ufsp";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ufs_core_clock>,
<&ufs_core_clock>;
clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>,
<&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO>;
clock-names = "core_clk", "sclk_unipro_main";
freq-table-hz = <0 0>, <0 0>;
pinctrl-names = "default";

8
arch/arm64/boot/dts/tesla/fsd.dtsi
View File

@ -432,8 +432,6 @@
reg = <0x0 0x10100000 0x0 0x1000>;
interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>;
clock-names = "apb_pclk";
iommus = <&smmu_imem 0x800 0x0>;
@ -444,8 +442,6 @@
reg = <0x0 0x10110000 0x0 0x1000>;
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>;
clock-names = "apb_pclk";
iommus = <&smmu_imem 0x801 0x0>;
@ -456,8 +452,6 @@
reg = <0x0 0x14280000 0x0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>;
clock-names = "apb_pclk";
iommus = <&smmu_peric 0x2 0x0>;
@ -468,8 +462,6 @@
reg = <0x0 0x14290000 0x0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>;
clock-names = "apb_pclk";
iommus = <&smmu_peric 0x1 0x0>;

299
include/dt-bindings/clock/samsung,exynosautov9.h Normal file
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@ -0,0 +1,299 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022 Samsung Electronics Co., Ltd.
* Author: Chanho Park <chanho61.park@samsung.com>
*
* Device Tree binding constants for Exynos Auto V9 clock controller.
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H
#define _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H
/* CMU_TOP */
#define FOUT_SHARED0_PLL 1
#define FOUT_SHARED1_PLL 2
#define FOUT_SHARED2_PLL 3
#define FOUT_SHARED3_PLL 4
#define FOUT_SHARED4_PLL 5
/* MUX in CMU_TOP */
#define MOUT_SHARED0_PLL 6
#define MOUT_SHARED1_PLL 7
#define MOUT_SHARED2_PLL 8
#define MOUT_SHARED3_PLL 9
#define MOUT_SHARED4_PLL 10
#define MOUT_CLKCMU_CMU_BOOST 11
#define MOUT_CLKCMU_CMU_CMUREF 12
#define MOUT_CLKCMU_ACC_BUS 13
#define MOUT_CLKCMU_APM_BUS 14
#define MOUT_CLKCMU_AUD_CPU 15
#define MOUT_CLKCMU_AUD_BUS 16
#define MOUT_CLKCMU_BUSC_BUS 17
#define MOUT_CLKCMU_BUSMC_BUS 19
#define MOUT_CLKCMU_CORE_BUS 20
#define MOUT_CLKCMU_CPUCL0_SWITCH 21
#define MOUT_CLKCMU_CPUCL0_CLUSTER 22
#define MOUT_CLKCMU_CPUCL1_SWITCH 24
#define MOUT_CLKCMU_CPUCL1_CLUSTER 25
#define MOUT_CLKCMU_DPTX_BUS 26
#define MOUT_CLKCMU_DPTX_DPGTC 27
#define MOUT_CLKCMU_DPUM_BUS 28
#define MOUT_CLKCMU_DPUS0_BUS 29
#define MOUT_CLKCMU_DPUS1_BUS 30
#define MOUT_CLKCMU_FSYS0_BUS 31
#define MOUT_CLKCMU_FSYS0_PCIE 32
#define MOUT_CLKCMU_FSYS1_BUS 33
#define MOUT_CLKCMU_FSYS1_USBDRD 34
#define MOUT_CLKCMU_FSYS1_MMC_CARD 35
#define MOUT_CLKCMU_FSYS2_BUS 36
#define MOUT_CLKCMU_FSYS2_UFS_EMBD 37
#define MOUT_CLKCMU_FSYS2_ETHERNET 38
#define MOUT_CLKCMU_G2D_G2D 39
#define MOUT_CLKCMU_G2D_MSCL 40
#define MOUT_CLKCMU_G3D00_SWITCH 41
#define MOUT_CLKCMU_G3D01_SWITCH 42
#define MOUT_CLKCMU_G3D1_SWITCH 43
#define MOUT_CLKCMU_ISPB_BUS 44
#define MOUT_CLKCMU_MFC_MFC 45
#define MOUT_CLKCMU_MFC_WFD 46
#define MOUT_CLKCMU_MIF_SWITCH 47
#define MOUT_CLKCMU_MIF_BUSP 48
#define MOUT_CLKCMU_NPU_BUS 49
#define MOUT_CLKCMU_PERIC0_BUS 50
#define MOUT_CLKCMU_PERIC0_IP 51
#define MOUT_CLKCMU_PERIC1_BUS 52
#define MOUT_CLKCMU_PERIC1_IP 53
#define MOUT_CLKCMU_PERIS_BUS 54
/* DIV in CMU_TOP */
#define DOUT_SHARED0_DIV3 101
#define DOUT_SHARED0_DIV2 102
#define DOUT_SHARED1_DIV3 103
#define DOUT_SHARED1_DIV2 104
#define DOUT_SHARED1_DIV4 105
#define DOUT_SHARED2_DIV3 106
#define DOUT_SHARED2_DIV2 107
#define DOUT_SHARED2_DIV4 108
#define DOUT_SHARED4_DIV2 109
#define DOUT_SHARED4_DIV4 110
#define DOUT_CLKCMU_CMU_BOOST 111
#define DOUT_CLKCMU_ACC_BUS 112
#define DOUT_CLKCMU_APM_BUS 113
#define DOUT_CLKCMU_AUD_CPU 114
#define DOUT_CLKCMU_AUD_BUS 115
#define DOUT_CLKCMU_BUSC_BUS 116
#define DOUT_CLKCMU_BUSMC_BUS 118
#define DOUT_CLKCMU_CORE_BUS 119
#define DOUT_CLKCMU_CPUCL0_SWITCH 120
#define DOUT_CLKCMU_CPUCL0_CLUSTER 121
#define DOUT_CLKCMU_CPUCL1_SWITCH 123
#define DOUT_CLKCMU_CPUCL1_CLUSTER 124
#define DOUT_CLKCMU_DPTX_BUS 125
#define DOUT_CLKCMU_DPTX_DPGTC 126
#define DOUT_CLKCMU_DPUM_BUS 127
#define DOUT_CLKCMU_DPUS0_BUS 128
#define DOUT_CLKCMU_DPUS1_BUS 129
#define DOUT_CLKCMU_FSYS0_BUS 130
#define DOUT_CLKCMU_FSYS0_PCIE 131
#define DOUT_CLKCMU_FSYS1_BUS 132
#define DOUT_CLKCMU_FSYS1_USBDRD 133
#define DOUT_CLKCMU_FSYS2_BUS 134
#define DOUT_CLKCMU_FSYS2_UFS_EMBD 135
#define DOUT_CLKCMU_FSYS2_ETHERNET 136
#define DOUT_CLKCMU_G2D_G2D 137
#define DOUT_CLKCMU_G2D_MSCL 138
#define DOUT_CLKCMU_G3D00_SWITCH 139
#define DOUT_CLKCMU_G3D01_SWITCH 140
#define DOUT_CLKCMU_G3D1_SWITCH 141
#define DOUT_CLKCMU_ISPB_BUS 142
#define DOUT_CLKCMU_MFC_MFC 143
#define DOUT_CLKCMU_MFC_WFD 144
#define DOUT_CLKCMU_MIF_SWITCH 145
#define DOUT_CLKCMU_MIF_BUSP 146
#define DOUT_CLKCMU_NPU_BUS 147
#define DOUT_CLKCMU_PERIC0_BUS 148
#define DOUT_CLKCMU_PERIC0_IP 149
#define DOUT_CLKCMU_PERIC1_BUS 150
#define DOUT_CLKCMU_PERIC1_IP 151
#define DOUT_CLKCMU_PERIS_BUS 152
/* GAT in CMU_TOP */
#define GOUT_CLKCMU_CMU_BOOST 201
#define GOUT_CLKCMU_CPUCL0_BOOST 202
#define GOUT_CLKCMU_CPUCL1_BOOST 203
#define GOUT_CLKCMU_CORE_BOOST 204
#define GOUT_CLKCMU_BUSC_BOOST 205
#define GOUT_CLKCMU_BUSMC_BOOST 206
#define GOUT_CLKCMU_MIF_BOOST 207
#define GOUT_CLKCMU_ACC_BUS 208
#define GOUT_CLKCMU_APM_BUS 209
#define GOUT_CLKCMU_AUD_CPU 210
#define GOUT_CLKCMU_AUD_BUS 211
#define GOUT_CLKCMU_BUSC_BUS 212
#define GOUT_CLKCMU_BUSMC_BUS 214
#define GOUT_CLKCMU_CORE_BUS 215
#define GOUT_CLKCMU_CPUCL0_SWITCH 216
#define GOUT_CLKCMU_CPUCL0_CLUSTER 217
#define GOUT_CLKCMU_CPUCL1_SWITCH 219
#define GOUT_CLKCMU_CPUCL1_CLUSTER 220
#define GOUT_CLKCMU_DPTX_BUS 221
#define GOUT_CLKCMU_DPTX_DPGTC 222
#define GOUT_CLKCMU_DPUM_BUS 223
#define GOUT_CLKCMU_DPUS0_BUS 224
#define GOUT_CLKCMU_DPUS1_BUS 225
#define GOUT_CLKCMU_FSYS0_BUS 226
#define GOUT_CLKCMU_FSYS0_PCIE 227
#define GOUT_CLKCMU_FSYS1_BUS 228
#define GOUT_CLKCMU_FSYS1_USBDRD 229
#define GOUT_CLKCMU_FSYS1_MMC_CARD 230
#define GOUT_CLKCMU_FSYS2_BUS 231
#define GOUT_CLKCMU_FSYS2_UFS_EMBD 232
#define GOUT_CLKCMU_FSYS2_ETHERNET 233
#define GOUT_CLKCMU_G2D_G2D 234
#define GOUT_CLKCMU_G2D_MSCL 235
#define GOUT_CLKCMU_G3D00_SWITCH 236
#define GOUT_CLKCMU_G3D01_SWITCH 237
#define GOUT_CLKCMU_G3D1_SWITCH 238
#define GOUT_CLKCMU_ISPB_BUS 239
#define GOUT_CLKCMU_MFC_MFC 240
#define GOUT_CLKCMU_MFC_WFD 241
#define GOUT_CLKCMU_MIF_SWITCH 242
#define GOUT_CLKCMU_MIF_BUSP 243
#define GOUT_CLKCMU_NPU_BUS 244
#define GOUT_CLKCMU_PERIC0_BUS 245
#define GOUT_CLKCMU_PERIC0_IP 246
#define GOUT_CLKCMU_PERIC1_BUS 247
#define GOUT_CLKCMU_PERIC1_IP 248
#define GOUT_CLKCMU_PERIS_BUS 249
#define TOP_NR_CLK 249
/* CMU_BUSMC */
#define CLK_MOUT_BUSMC_BUS_USER 1
#define CLK_DOUT_BUSMC_BUSP 2
#define CLK_GOUT_BUSMC_PDMA0_PCLK 3
#define CLK_GOUT_BUSMC_SPDMA_PCLK 4
#define BUSMC_NR_CLK 4
/* CMU_CORE */
#define CLK_MOUT_CORE_BUS_USER 1
#define CLK_DOUT_CORE_BUSP 2
#define CLK_GOUT_CORE_CCI_CLK 3
#define CLK_GOUT_CORE_CCI_PCLK 4
#define CLK_GOUT_CORE_CMU_CORE_PCLK 5
#define CORE_NR_CLK 5
/* CMU_FSYS2 */
#define CLK_MOUT_FSYS2_BUS_USER 1
#define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
#define CLK_MOUT_FSYS2_ETHERNET_USER 3
#define CLK_GOUT_FSYS2_UFS_EMBD0_ACLK 4
#define CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO 5
#define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6
#define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7
#define FSYS2_NR_CLK 7
/* CMU_PERIC0 */
#define CLK_MOUT_PERIC0_BUS_USER 1
#define CLK_MOUT_PERIC0_IP_USER 2
#define CLK_MOUT_PERIC0_USI00_USI 3
#define CLK_MOUT_PERIC0_USI01_USI 4
#define CLK_MOUT_PERIC0_USI02_USI 5
#define CLK_MOUT_PERIC0_USI03_USI 6
#define CLK_MOUT_PERIC0_USI04_USI 7
#define CLK_MOUT_PERIC0_USI05_USI 8
#define CLK_MOUT_PERIC0_USI_I2C 9
#define CLK_DOUT_PERIC0_USI00_USI 10
#define CLK_DOUT_PERIC0_USI01_USI 11
#define CLK_DOUT_PERIC0_USI02_USI 12
#define CLK_DOUT_PERIC0_USI03_USI 13
#define CLK_DOUT_PERIC0_USI04_USI 14
#define CLK_DOUT_PERIC0_USI05_USI 15
#define CLK_DOUT_PERIC0_USI_I2C 16
#define CLK_GOUT_PERIC0_IPCLK_0 20
#define CLK_GOUT_PERIC0_IPCLK_1 21
#define CLK_GOUT_PERIC0_IPCLK_2 22
#define CLK_GOUT_PERIC0_IPCLK_3 23
#define CLK_GOUT_PERIC0_IPCLK_4 24
#define CLK_GOUT_PERIC0_IPCLK_5 25
#define CLK_GOUT_PERIC0_IPCLK_6 26
#define CLK_GOUT_PERIC0_IPCLK_7 27
#define CLK_GOUT_PERIC0_IPCLK_8 28
#define CLK_GOUT_PERIC0_IPCLK_9 29
#define CLK_GOUT_PERIC0_IPCLK_10 30
#define CLK_GOUT_PERIC0_IPCLK_11 30
#define CLK_GOUT_PERIC0_PCLK_0 31
#define CLK_GOUT_PERIC0_PCLK_1 32
#define CLK_GOUT_PERIC0_PCLK_2 33
#define CLK_GOUT_PERIC0_PCLK_3 34
#define CLK_GOUT_PERIC0_PCLK_4 35
#define CLK_GOUT_PERIC0_PCLK_5 36
#define CLK_GOUT_PERIC0_PCLK_6 37
#define CLK_GOUT_PERIC0_PCLK_7 38
#define CLK_GOUT_PERIC0_PCLK_8 39
#define CLK_GOUT_PERIC0_PCLK_9 40
#define CLK_GOUT_PERIC0_PCLK_10 41
#define CLK_GOUT_PERIC0_PCLK_11 42
#define PERIC0_NR_CLK 42
/* CMU_PERIC1 */
#define CLK_MOUT_PERIC1_BUS_USER 1
#define CLK_MOUT_PERIC1_IP_USER 2
#define CLK_MOUT_PERIC1_USI06_USI 3
#define CLK_MOUT_PERIC1_USI07_USI 4
#define CLK_MOUT_PERIC1_USI08_USI 5
#define CLK_MOUT_PERIC1_USI09_USI 6
#define CLK_MOUT_PERIC1_USI10_USI 7
#define CLK_MOUT_PERIC1_USI11_USI 8
#define CLK_MOUT_PERIC1_USI_I2C 9
#define CLK_DOUT_PERIC1_USI06_USI 10
#define CLK_DOUT_PERIC1_USI07_USI 11
#define CLK_DOUT_PERIC1_USI08_USI 12
#define CLK_DOUT_PERIC1_USI09_USI 13
#define CLK_DOUT_PERIC1_USI10_USI 14
#define CLK_DOUT_PERIC1_USI11_USI 15
#define CLK_DOUT_PERIC1_USI_I2C 16
#define CLK_GOUT_PERIC1_IPCLK_0 20
#define CLK_GOUT_PERIC1_IPCLK_1 21
#define CLK_GOUT_PERIC1_IPCLK_2 22
#define CLK_GOUT_PERIC1_IPCLK_3 23
#define CLK_GOUT_PERIC1_IPCLK_4 24
#define CLK_GOUT_PERIC1_IPCLK_5 25
#define CLK_GOUT_PERIC1_IPCLK_6 26
#define CLK_GOUT_PERIC1_IPCLK_7 27
#define CLK_GOUT_PERIC1_IPCLK_8 28
#define CLK_GOUT_PERIC1_IPCLK_9 29
#define CLK_GOUT_PERIC1_IPCLK_10 30
#define CLK_GOUT_PERIC1_IPCLK_11 30
#define CLK_GOUT_PERIC1_PCLK_0 31
#define CLK_GOUT_PERIC1_PCLK_1 32
#define CLK_GOUT_PERIC1_PCLK_2 33
#define CLK_GOUT_PERIC1_PCLK_3 34
#define CLK_GOUT_PERIC1_PCLK_4 35
#define CLK_GOUT_PERIC1_PCLK_5 36
#define CLK_GOUT_PERIC1_PCLK_6 37
#define CLK_GOUT_PERIC1_PCLK_7 38
#define CLK_GOUT_PERIC1_PCLK_8 39
#define CLK_GOUT_PERIC1_PCLK_9 40
#define CLK_GOUT_PERIC1_PCLK_10 41
#define CLK_GOUT_PERIC1_PCLK_11 42
#define PERIC1_NR_CLK 42
/* CMU_PERIS */
#define CLK_MOUT_PERIS_BUS_USER 1
#define CLK_GOUT_SYSREG_PERIS_PCLK 2
#define CLK_GOUT_WDT_CLUSTER0 3
#define CLK_GOUT_WDT_CLUSTER1 4
#define PERIS_NR_CLK 4
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */