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x86, amd: Add support for CPUID topology extension of AMD CPUs 

Node information (ID, number of internal nodes) is provided via
CPUID Fn8000_001e_ECX.

See AMD CPUID Specification (Publication # 25481, Revision 2.34,
September 2010).

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
LKML-Reference: <20100930123628.GD20545@loge.amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This commit is contained in:
Andreas Herrmann 2010-09-30 14:36:28 +02:00 committed by H. Peter Anvin
parent 420b13b60a
commit 23588c38a8
1 changed files with 26 additions and 24 deletions
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50
arch/x86/kernel/cpu/amd.c
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@ -253,37 +253,41 @@ static int __cpuinit nearby_node(int apicid)
#endif
/*
* Fixup core topology information for AMD multi-node processors.
* Assumption: Number of cores in each internal node is the same.
* Fixup core topology information for
* (1) AMD multi-node processors
* Assumption: Number of cores in each internal node is the same.
*/
#ifdef CONFIG_X86_HT
static void __cpuinit amd_fixup_dcm(struct cpuinfo_x86 *c)
static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
{
unsigned long long value;
u32 nodes, cores_per_node;
u8 node_id;
unsigned long long value;
int cpu = smp_processor_id();
if (!cpu_has(c, X86_FEATURE_NODEID_MSR))
/* get information required for multi-node processors */
if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
value = cpuid_ecx(0x8000001e);
nodes = ((value >> 8) & 7) + 1;
node_id = value & 7;
} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
rdmsrl(MSR_FAM10H_NODE_ID, value);
nodes = ((value >> 3) & 7) + 1;
node_id = value & 7;
} else
return;
/* fixup topology information only once for a core */
if (cpu_has(c, X86_FEATURE_AMD_DCM))
return;
/* fixup multi-node processor information */
if (nodes > 1) {
set_cpu_cap(c, X86_FEATURE_AMD_DCM);
cores_per_node = c->x86_max_cores / nodes;
rdmsrl(MSR_FAM10H_NODE_ID, value);
/* store NodeID, use llc_shared_map to store sibling info */
per_cpu(cpu_llc_id, cpu) = node_id;
nodes = ((value >> 3) & 7) + 1;
if (nodes == 1)
return;
set_cpu_cap(c, X86_FEATURE_AMD_DCM);
cores_per_node = c->x86_max_cores / nodes;
/* store NodeID, use llc_shared_map to store sibling info */
per_cpu(cpu_llc_id, cpu) = value & 7;
/* fixup core id to be in range from 0 to (cores_per_node - 1) */
c->cpu_core_id = c->cpu_core_id % cores_per_node;
/* core id to be in range from 0 to (cores_per_node - 1) */
c->cpu_core_id = c->cpu_core_id % cores_per_node;
}
}
#endif
@ -304,9 +308,7 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
c->phys_proc_id = c->initial_apicid >> bits;
/* use socket ID also for last level cache */
per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
/* fixup topology information on multi-node processors */
if ((c->x86 == 0x10) && (c->x86_model == 9))
amd_fixup_dcm(c);
amd_get_topology(c);
#endif
}