x86/amd_nb: Add northbridge support for Hygon family 18h model 4h
Add dedicated functions to initialize the northbridge for Hygon family 18h model 4h processors. Signed-off-by: Pu Wen <puwen@hygon.cn> Signed-off-by: Jinliang Zheng <alexjlzheng@tencent.com> Reviewed-by: Bin Lai <robinlai@tencent.com> Signed-off-by: Jinliang Zheng <alexjlzheng@tencent.com> Reviewed-by: caelli <caelli@tencent.com> Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
This commit is contained in:
Pu Wen
Jianping Liu
parent
88dbf4a46d
commit
2336e8989a
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@ -84,6 +84,10 @@ u16 amd_nb_num(void);
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bool amd_nb_has_feature(unsigned int feature);
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struct amd_northbridge *node_to_amd_nb(int node);
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bool hygon_f18h_m4h(void);
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u16 hygon_nb_num(void);
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int get_df_id(struct pci_dev *misc, u8 *id);
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static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev)
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{
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struct pci_dev *misc;
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@ -121,6 +125,10 @@ static inline bool amd_gart_present(void)
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#define node_to_amd_nb(x) NULL
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#define amd_gart_present(x) false
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#define hygon_f18h_m4h false
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#define hygon_nb_num(x) 0
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#define get_df_id(x, y) NULL
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#endif
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@ -27,10 +27,14 @@
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#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
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#define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
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#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
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#define PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1 0x1491
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/* Protect the PCI config register pairs used for SMN and DF indirect access. */
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static DEFINE_MUTEX(smn_mutex);
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static u32 *flush_words;
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static u16 nb_num;
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static const struct pci_device_id amd_root_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
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@ -231,6 +235,192 @@ out:
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}
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EXPORT_SYMBOL_GPL(amd_df_indirect_read);
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bool hygon_f18h_m4h(void)
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{
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if (boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
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return false;
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if (boot_cpu_data.x86 == 0x18 &&
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boot_cpu_data.x86_model >= 0x4 &&
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boot_cpu_data.x86_model <= 0xf)
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return true;
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return false;
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}
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EXPORT_SYMBOL_GPL(hygon_f18h_m4h);
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u16 hygon_nb_num(void)
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{
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return nb_num;
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}
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EXPORT_SYMBOL_GPL(hygon_nb_num);
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static int get_df1_register(struct pci_dev *misc, int offset, u32 *value)
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{
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struct pci_dev *df_f1 = NULL;
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int err;
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while ((df_f1 = pci_get_device(misc->vendor,
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PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1, df_f1)))
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if (pci_domain_nr(df_f1->bus) == pci_domain_nr(misc->bus) &&
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df_f1->bus->number == misc->bus->number &&
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PCI_SLOT(df_f1->devfn) == PCI_SLOT(misc->devfn))
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break;
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if (!df_f1) {
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pr_warn("Error getting DF F1 device.\n");
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return -ENODEV;
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}
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err = pci_read_config_dword(df_f1, offset, value);
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if (err)
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pr_warn("Error reading DF F1 register.\n");
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return err;
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}
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int get_df_id(struct pci_dev *misc, u8 *id)
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{
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u32 value;
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int ret;
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/* F1x200[23:20]: DF ID */
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ret = get_df1_register(misc, 0x200, &value);
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*id = (value >> 20) & 0xf;
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return ret;
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}
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EXPORT_SYMBOL_GPL(get_df_id);
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static u8 get_socket_num(struct pci_dev *misc)
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{
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u32 value;
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int ret;
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/* F1x200[7:0]: Which socket is present. */
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ret = get_df1_register(misc, 0x200, &value);
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return ret ? 0 : hweight8(value & 0xff);
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}
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static int northbridge_init_f18h_m4h(const struct pci_device_id *root_ids,
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const struct pci_device_id *misc_ids,
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const struct pci_device_id *link_ids)
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{
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struct pci_dev *root, *misc, *link;
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struct pci_dev *root_first = NULL;
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struct amd_northbridge *nb;
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u16 roots_per_socket = 0;
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u16 miscs_per_socket = 0;
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u16 socket_num = 0;
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u16 root_count = 0;
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u16 misc_count = 0;
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int err = -ENODEV;
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u8 i, j, m, n;
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u8 id;
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pr_info("Hygon Fam%xh Model%xh NB driver.\n",
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boot_cpu_data.x86, boot_cpu_data.x86_model);
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misc = next_northbridge(NULL, misc_ids);
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if (misc != NULL) {
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socket_num = get_socket_num(misc);
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pr_info("Socket number: %d\n", socket_num);
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if (!socket_num) {
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err = -ENODEV;
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goto ret;
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}
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} else {
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err = -ENODEV;
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goto ret;
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}
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misc = NULL;
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while ((misc = next_northbridge(misc, misc_ids)) != NULL)
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misc_count++;
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root = NULL;
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while ((root = next_northbridge(root, root_ids)) != NULL)
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root_count++;
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if (!root_count || !misc_count) {
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err = -ENODEV;
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goto ret;
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}
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/*
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* There should be _exactly_ N roots for each DF/SMN
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* interface, and M DF/SMN interfaces in one socket.
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*/
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roots_per_socket = root_count / socket_num;
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miscs_per_socket = misc_count / socket_num;
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if (!roots_per_socket || !miscs_per_socket) {
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err = -ENODEV;
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goto ret;
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}
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nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
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if (!nb) {
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err = -ENOMEM;
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goto ret;
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}
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amd_northbridges.nb = nb;
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amd_northbridges.num = misc_count;
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link = misc = root = NULL;
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j = m = n = 0;
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for (i = 0; i < amd_northbridges.num; i++) {
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misc = next_northbridge(misc, misc_ids);
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link = next_northbridge(link, link_ids);
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/* Only save the first PCI root device for each socket. */
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if (!(i % miscs_per_socket)) {
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root_first = next_northbridge(root, root_ids);
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root = root_first;
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j = 1;
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}
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if (get_df_id(misc, &id)) {
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err = -ENODEV;
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goto err;
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}
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pr_info("DF ID: %d\n", id);
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if (id < 4) {
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/* Add the devices with id<4 from the tail. */
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node_to_amd_nb(misc_count - m - 1)->misc = misc;
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node_to_amd_nb(misc_count - m - 1)->link = link;
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node_to_amd_nb(misc_count - m - 1)->root = root_first;
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m++;
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} else {
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node_to_amd_nb(n)->misc = misc;
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node_to_amd_nb(n)->link = link;
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node_to_amd_nb(n)->root = root_first;
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n++;
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}
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/* Skip the redundant PCI root devices per socket. */
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while (j < roots_per_socket) {
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root = next_northbridge(root, root_ids);
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j++;
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}
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}
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nb_num = n;
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return 0;
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err:
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kfree(nb);
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amd_northbridges.nb = NULL;
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ret:
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pr_err("Hygon Fam%xh Model%xh northbridge init failed(%d)!\n",
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boot_cpu_data.x86, boot_cpu_data.x86_model, err);
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return err;
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}
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int amd_cache_northbridges(void)
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{
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const struct pci_device_id *misc_ids = amd_nb_misc_ids;
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@ -250,6 +440,11 @@ int amd_cache_northbridges(void)
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root_ids = hygon_root_ids;
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misc_ids = hygon_nb_misc_ids;
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link_ids = hygon_nb_link_ids;
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if (boot_cpu_data.x86_model >= 0x4 &&
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boot_cpu_data.x86_model <= 0xf)
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return northbridge_init_f18h_m4h(root_ids,
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misc_ids, link_ids);
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}
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misc = NULL;
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