ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4)
The L2x0 cache controllers need to explicitly drain their write buffer even for Normal Noncacheable memory accesses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -763,6 +763,7 @@ config CACHE_L2X0
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REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
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default y
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select OUTER_CACHE
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select OUTER_CACHE_SYNC
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help
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This option enables the L2x0 PrimeCell.
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@ -93,6 +93,15 @@ static inline void l2x0_flush_line(unsigned long addr)
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}
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#endif
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static void l2x0_cache_sync(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&l2x0_lock, flags);
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cache_sync();
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static inline void l2x0_inv_all(void)
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{
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unsigned long flags;
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@ -225,6 +234,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
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outer_cache.inv_range = l2x0_inv_range;
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outer_cache.clean_range = l2x0_clean_range;
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outer_cache.flush_range = l2x0_flush_range;
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outer_cache.sync = l2x0_cache_sync;
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printk(KERN_INFO "L2X0 cache controller enabled\n");
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}
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