bnxt_en: Handle firmware reset.
Add the bnxt_fw_reset() main function to handle firmware reset. This is triggered by firmware to initiate an orderly reset, for example when a non-fatal exception condition has been detected. bnxt_fw_reset() will first wait for all VFs to shutdown and then start the bnxt_fw_reset_task() work queue to go through the sequence of reset, re-probe, and re-initialization. The next patch will add the devlink reporter to start the sequence and call bnxt_fw_reset(). Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
2151fe0830
commit
230d1f0de7
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@ -1140,6 +1140,14 @@ static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
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return 0;
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}
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static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay)
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{
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if (BNXT_PF(bp))
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queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay);
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else
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schedule_delayed_work(&bp->fw_reset_task, delay);
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}
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static void bnxt_queue_sp_work(struct bnxt *bp)
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{
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if (BNXT_PF(bp))
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@ -6355,6 +6363,8 @@ static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
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struct bnxt_vf_info *vf = &bp->vf;
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vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
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} else {
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bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs);
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}
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#endif
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flags = le16_to_cpu(resp->flags);
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@ -9980,6 +9990,53 @@ static void bnxt_reset(struct bnxt *bp, bool silent)
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bnxt_rtnl_unlock_sp(bp);
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}
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static void bnxt_fw_reset_close(struct bnxt *bp)
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{
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__bnxt_close_nic(bp, true, false);
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bnxt_ulp_irq_stop(bp);
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bnxt_clear_int_mode(bp);
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bnxt_hwrm_func_drv_unrgtr(bp);
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bnxt_free_ctx_mem(bp);
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kfree(bp->ctx);
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bp->ctx = NULL;
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}
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void bnxt_fw_reset(struct bnxt *bp)
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{
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int rc;
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bnxt_rtnl_lock_sp(bp);
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if (test_bit(BNXT_STATE_OPEN, &bp->state) &&
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!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
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set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
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if (BNXT_PF(bp) && bp->pf.active_vfs) {
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rc = bnxt_hwrm_func_qcfg(bp);
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if (rc) {
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netdev_err(bp->dev, "Firmware reset aborted, first func_qcfg cmd failed, rc = %d\n",
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rc);
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clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
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dev_close(bp->dev);
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goto fw_reset_exit;
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}
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if (bp->pf.registered_vfs || bp->sriov_cfg) {
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u16 vf_tmo_dsecs = bp->pf.registered_vfs * 10;
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if (bp->fw_reset_max_dsecs < vf_tmo_dsecs)
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bp->fw_reset_max_dsecs = vf_tmo_dsecs;
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bp->fw_reset_state =
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BNXT_FW_RESET_STATE_POLL_VF;
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bnxt_queue_fw_reset_work(bp, HZ / 10);
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goto fw_reset_exit;
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}
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}
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bnxt_fw_reset_close(bp);
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bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
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bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10);
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}
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fw_reset_exit:
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bnxt_rtnl_unlock_sp(bp);
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}
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static void bnxt_chk_missed_irq(struct bnxt *bp)
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{
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int i;
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@ -10339,6 +10396,98 @@ static int bnxt_fw_init_one(struct bnxt *bp)
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return 0;
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}
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static void bnxt_fw_reset_task(struct work_struct *work)
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{
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struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work);
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int rc;
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if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
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netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n");
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return;
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}
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switch (bp->fw_reset_state) {
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case BNXT_FW_RESET_STATE_POLL_VF:
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rc = bnxt_hwrm_func_qcfg(bp);
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if (rc) {
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netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n",
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rc, jiffies_to_msecs(jiffies -
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bp->fw_reset_timestamp));
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goto fw_reset_abort;
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}
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if (bp->pf.registered_vfs || bp->sriov_cfg) {
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if (time_after(jiffies, bp->fw_reset_timestamp +
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(bp->fw_reset_max_dsecs * HZ / 10))) {
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clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
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bp->fw_reset_state = 0;
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netdev_err(bp->dev, "Firmware reset aborted, %d VFs still registered, sriov_cfg %d\n",
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bp->pf.registered_vfs,
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bp->sriov_cfg);
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return;
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}
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bnxt_queue_fw_reset_work(bp, HZ / 10);
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return;
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}
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bp->fw_reset_timestamp = jiffies;
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rtnl_lock();
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bnxt_fw_reset_close(bp);
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bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
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rtnl_unlock();
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bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10);
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return;
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case BNXT_FW_RESET_STATE_ENABLE_DEV:
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if (pci_enable_device(bp->pdev)) {
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netdev_err(bp->dev, "Cannot re-enable PCI device\n");
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goto fw_reset_abort;
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}
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pci_set_master(bp->pdev);
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bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW;
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/* fall through */
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case BNXT_FW_RESET_STATE_POLL_FW:
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bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
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rc = __bnxt_hwrm_ver_get(bp, true);
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if (rc) {
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if (time_after(jiffies, bp->fw_reset_timestamp +
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(bp->fw_reset_max_dsecs * HZ / 10))) {
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netdev_err(bp->dev, "Firmware reset aborted\n");
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goto fw_reset_abort;
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}
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bnxt_queue_fw_reset_work(bp, HZ / 5);
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return;
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}
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bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
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bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING;
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/* fall through */
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case BNXT_FW_RESET_STATE_OPENING:
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while (!rtnl_trylock()) {
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bnxt_queue_fw_reset_work(bp, HZ / 10);
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return;
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}
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rc = bnxt_open(bp->dev);
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if (rc) {
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netdev_err(bp->dev, "bnxt_open_nic() failed\n");
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clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
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dev_close(bp->dev);
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}
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bnxt_ulp_irq_restart(bp, rc);
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rtnl_unlock();
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bp->fw_reset_state = 0;
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/* Make sure fw_reset_state is 0 before clearing the flag */
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smp_mb__before_atomic();
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clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
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break;
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}
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return;
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fw_reset_abort:
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clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
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bp->fw_reset_state = 0;
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rtnl_lock();
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dev_close(bp->dev);
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rtnl_unlock();
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}
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static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
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{
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int rc;
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pci_enable_pcie_error_reporting(pdev);
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INIT_WORK(&bp->sp_task, bnxt_sp_task);
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INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task);
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spin_lock_init(&bp->ntp_fltr_lock);
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#if BITS_PER_LONG == 32
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@ -640,6 +640,7 @@ struct nqe_cn {
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#define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len)
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#define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
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#define DFLT_HWRM_CMD_TIMEOUT 500
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#define SHORT_HWRM_CMD_TIMEOUT 20
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#define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout)
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#define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
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#define HWRM_RESP_ERR_CODE_MASK 0xffff
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@ -1066,6 +1067,7 @@ struct bnxt_pf_info {
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u8 mac_addr[ETH_ALEN];
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u32 first_vf_id;
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u16 active_vfs;
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u16 registered_vfs;
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u16 max_vfs;
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u32 max_encap_records;
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u32 max_decap_records;
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#define BNXT_RING_COAL_NOW_SP_EVENT 17
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#define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
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struct delayed_work fw_reset_task;
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int fw_reset_state;
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#define BNXT_FW_RESET_STATE_POLL_VF 1
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#define BNXT_FW_RESET_STATE_RESET_FW 2
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#define BNXT_FW_RESET_STATE_ENABLE_DEV 3
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#define BNXT_FW_RESET_STATE_POLL_FW 4
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#define BNXT_FW_RESET_STATE_OPENING 5
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u16 fw_reset_min_dsecs;
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#define BNXT_DFLT_FW_RST_MIN_DSECS 20
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u16 fw_reset_max_dsecs;
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@ -1966,6 +1976,7 @@ int bnxt_open_nic(struct bnxt *, bool, bool);
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int bnxt_half_open_nic(struct bnxt *bp);
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void bnxt_half_close_nic(struct bnxt *bp);
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int bnxt_close_nic(struct bnxt *, bool, bool);
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void bnxt_fw_reset(struct bnxt *bp);
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int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
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int tx_xdp);
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int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
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@ -226,6 +226,9 @@ static int bnxt_send_msg(struct bnxt_en_dev *edev, int ulp_id,
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struct input *req;
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int rc;
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if (ulp_id != BNXT_ROCE_ULP && bp->fw_reset_state)
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return -EBUSY;
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mutex_lock(&bp->hwrm_cmd_lock);
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req = fw_msg->msg;
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req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
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