drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1120,7 +1120,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
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s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
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for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
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s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
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s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
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s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
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s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
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@ -1164,7 +1164,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
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s->pm_ier = I915_READ(GEN6_PMIER);
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for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
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s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
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s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
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/* GT SA CZ domain, 0x100000-0x138124 */
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s->tilectl = I915_READ(TILECTL);
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@ -1202,7 +1202,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
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I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
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for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
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I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
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I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
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I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
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I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
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@ -1246,7 +1246,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
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I915_WRITE(GEN6_PMIER, s->pm_ier);
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for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
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I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
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I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
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/* GT SA CZ domain, 0x100000-0x138124 */
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I915_WRITE(TILECTL, s->tilectl);
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@ -1527,7 +1527,7 @@ enum skl_disp_power_wells {
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#define GEN7_GFX_PEND_TLB0 0x4034
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#define GEN7_GFX_PEND_TLB1 0x4038
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/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
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#define GEN7_LRA_LIMITS_BASE 0x403C
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#define GEN7_LRA_LIMITS(i) (0x403C + (i) * 4)
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#define GEN7_LRA_LIMITS_REG_NUM 13
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#define GEN7_MEDIA_MAX_REQ_COUNT 0x4070
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#define GEN7_GFX_MAX_REQ_COUNT 0x4074
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@ -6813,7 +6813,7 @@ enum skl_disp_power_wells {
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GEN6_PM_RP_DOWN_THRESHOLD | \
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GEN6_PM_RP_DOWN_TIMEOUT)
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#define GEN7_GT_SCRATCH_BASE 0x4F100
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#define GEN7_GT_SCRATCH(i) (0x4F100 + (i) * 4)
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#define GEN7_GT_SCRATCH_REG_NUM 8
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#define VLV_GTLC_SURVIVABILITY_REG 0x130098
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