Merge branch 'for-3.1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound-2.6.git into for-3.1
This commit is contained in:
Mark Brown
commit
22de4534ae
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@ -33,73 +33,31 @@
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#define SGTL5000_DAP_REG_OFFSET 0x0100
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#define SGTL5000_MAX_REG_OFFSET 0x013A
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/* default value of sgtl5000 registers except DAP */
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static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET >> 1] = {
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0xa011, /* 0x0000, CHIP_ID. 11 stand for revison 17 */
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0x0000, /* 0x0002, CHIP_DIG_POWER. */
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0x0008, /* 0x0004, CHIP_CKL_CTRL */
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0x0010, /* 0x0006, CHIP_I2S_CTRL */
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0x0000, /* 0x0008, reserved */
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0x0008, /* 0x000A, CHIP_SSS_CTRL */
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0x0000, /* 0x000C, reserved */
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0x020c, /* 0x000E, CHIP_ADCDAC_CTRL */
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0x3c3c, /* 0x0010, CHIP_DAC_VOL */
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0x0000, /* 0x0012, reserved */
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0x015f, /* 0x0014, CHIP_PAD_STRENGTH */
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0x0000, /* 0x0016, reserved */
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0x0000, /* 0x0018, reserved */
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0x0000, /* 0x001A, reserved */
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0x0000, /* 0x001E, reserved */
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0x0000, /* 0x0020, CHIP_ANA_ADC_CTRL */
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0x1818, /* 0x0022, CHIP_ANA_HP_CTRL */
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0x0111, /* 0x0024, CHIP_ANN_CTRL */
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0x0000, /* 0x0026, CHIP_LINREG_CTRL */
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0x0000, /* 0x0028, CHIP_REF_CTRL */
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0x0000, /* 0x002A, CHIP_MIC_CTRL */
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0x0000, /* 0x002C, CHIP_LINE_OUT_CTRL */
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0x0404, /* 0x002E, CHIP_LINE_OUT_VOL */
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0x7060, /* 0x0030, CHIP_ANA_POWER */
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0x5000, /* 0x0032, CHIP_PLL_CTRL */
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0x0000, /* 0x0034, CHIP_CLK_TOP_CTRL */
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0x0000, /* 0x0036, CHIP_ANA_STATUS */
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0x0000, /* 0x0038, reserved */
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0x0000, /* 0x003A, CHIP_ANA_TEST2 */
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0x0000, /* 0x003C, CHIP_SHORT_CTRL */
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0x0000, /* reserved */
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};
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/* default value of dap registers */
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static const u16 sgtl5000_dap_regs[] = {
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0x0000, /* 0x0100, DAP_CONTROL */
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0x0000, /* 0x0102, DAP_PEQ */
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0x0040, /* 0x0104, DAP_BASS_ENHANCE */
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0x051f, /* 0x0106, DAP_BASS_ENHANCE_CTRL */
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0x0000, /* 0x0108, DAP_AUDIO_EQ */
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0x0040, /* 0x010A, DAP_SGTL_SURROUND */
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0x0000, /* 0x010C, DAP_FILTER_COEF_ACCESS */
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0x0000, /* 0x010E, DAP_COEF_WR_B0_MSB */
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0x0000, /* 0x0110, DAP_COEF_WR_B0_LSB */
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0x0000, /* 0x0112, reserved */
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0x0000, /* 0x0114, reserved */
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0x002f, /* 0x0116, DAP_AUDIO_EQ_BASS_BAND0 */
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0x002f, /* 0x0118, DAP_AUDIO_EQ_BAND0 */
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0x002f, /* 0x011A, DAP_AUDIO_EQ_BAND2 */
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0x002f, /* 0x011C, DAP_AUDIO_EQ_BAND3 */
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0x002f, /* 0x011E, DAP_AUDIO_EQ_TREBLE_BAND4 */
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0x8000, /* 0x0120, DAP_MAIN_CHAN */
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0x0000, /* 0x0122, DAP_MIX_CHAN */
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0x0510, /* 0x0124, DAP_AVC_CTRL */
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0x1473, /* 0x0126, DAP_AVC_THRESHOLD */
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0x0028, /* 0x0128, DAP_AVC_ATTACK */
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0x0050, /* 0x012A, DAP_AVC_DECAY */
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0x0000, /* 0x012C, DAP_COEF_WR_B1_MSB */
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0x0000, /* 0x012E, DAP_COEF_WR_B1_LSB */
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0x0000, /* 0x0130, DAP_COEF_WR_B2_MSB */
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0x0000, /* 0x0132, DAP_COEF_WR_B2_LSB */
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0x0000, /* 0x0134, DAP_COEF_WR_A1_MSB */
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0x0000, /* 0x0136, DAP_COEF_WR_A1_LSB */
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0x0000, /* 0x0138, DAP_COEF_WR_A2_MSB */
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0x0000, /* 0x013A, DAP_COEF_WR_A2_LSB */
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/* default value of sgtl5000 registers */
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static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = {
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[SGTL5000_CHIP_CLK_CTRL] = 0x0008,
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[SGTL5000_CHIP_I2S_CTRL] = 0x0010,
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[SGTL5000_CHIP_SSS_CTRL] = 0x0008,
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[SGTL5000_CHIP_DAC_VOL] = 0x3c3c,
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[SGTL5000_CHIP_PAD_STRENGTH] = 0x015f,
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[SGTL5000_CHIP_ANA_HP_CTRL] = 0x1818,
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[SGTL5000_CHIP_ANA_CTRL] = 0x0111,
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[SGTL5000_CHIP_LINE_OUT_VOL] = 0x0404,
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[SGTL5000_CHIP_ANA_POWER] = 0x7060,
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[SGTL5000_CHIP_PLL_CTRL] = 0x5000,
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[SGTL5000_DAP_BASS_ENHANCE] = 0x0040,
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[SGTL5000_DAP_BASS_ENHANCE_CTRL] = 0x051f,
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[SGTL5000_DAP_SURROUND] = 0x0040,
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[SGTL5000_DAP_EQ_BASS_BAND0] = 0x002f,
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[SGTL5000_DAP_EQ_BASS_BAND1] = 0x002f,
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[SGTL5000_DAP_EQ_BASS_BAND2] = 0x002f,
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[SGTL5000_DAP_EQ_BASS_BAND3] = 0x002f,
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[SGTL5000_DAP_EQ_BASS_BAND4] = 0x002f,
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[SGTL5000_DAP_MAIN_CHAN] = 0x8000,
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[SGTL5000_DAP_AVC_CTRL] = 0x0510,
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[SGTL5000_DAP_AVC_THRESHOLD] = 0x1473,
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[SGTL5000_DAP_AVC_ATTACK] = 0x0028,
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[SGTL5000_DAP_AVC_DECAY] = 0x0050,
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};
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/* regulator supplies for sgtl5000, VDDD is an optional external supply */
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@ -1023,12 +981,10 @@ static int sgtl5000_suspend(struct snd_soc_codec *codec, pm_message_t state)
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static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
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{
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u16 *cache = codec->reg_cache;
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int i;
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int regular_regs = SGTL5000_CHIP_SHORT_CTRL >> 1;
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u16 reg;
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/* restore regular registers */
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for (i = 0; i < regular_regs; i++) {
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int reg = i << 1;
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for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
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/* this regs depends on the others */
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if (reg == SGTL5000_CHIP_ANA_POWER ||
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@ -1038,35 +994,31 @@ static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
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reg == SGTL5000_CHIP_CLK_CTRL)
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continue;
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snd_soc_write(codec, reg, cache[i]);
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snd_soc_write(codec, reg, cache[reg]);
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}
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/* restore dap registers */
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for (i = SGTL5000_DAP_REG_OFFSET >> 1;
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i < SGTL5000_MAX_REG_OFFSET >> 1; i++) {
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int reg = i << 1;
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snd_soc_write(codec, reg, cache[i]);
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}
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for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
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snd_soc_write(codec, reg, cache[reg]);
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/*
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* restore power and other regs according
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* to set_power() and set_clock()
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*/
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snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
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cache[SGTL5000_CHIP_LINREG_CTRL >> 1]);
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cache[SGTL5000_CHIP_LINREG_CTRL]);
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snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
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cache[SGTL5000_CHIP_ANA_POWER >> 1]);
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cache[SGTL5000_CHIP_ANA_POWER]);
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snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
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cache[SGTL5000_CHIP_CLK_CTRL >> 1]);
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cache[SGTL5000_CHIP_CLK_CTRL]);
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snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
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cache[SGTL5000_CHIP_REF_CTRL >> 1]);
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cache[SGTL5000_CHIP_REF_CTRL]);
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snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
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cache[SGTL5000_CHIP_LINE_OUT_CTRL >> 1]);
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cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
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return 0;
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}
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@ -1454,16 +1406,6 @@ static __devinit int sgtl5000_i2c_probe(struct i2c_client *client,
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if (!sgtl5000)
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return -ENOMEM;
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/*
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* copy DAP default values to default value array.
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* sgtl5000 register space has a big hole, merge it
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* at init phase makes life easy.
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* FIXME: should we drop 'const' of sgtl5000_regs?
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*/
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memcpy((void *)(&sgtl5000_regs[0] + (SGTL5000_DAP_REG_OFFSET >> 1)),
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sgtl5000_dap_regs,
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SGTL5000_MAX_REG_OFFSET - SGTL5000_DAP_REG_OFFSET);
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i2c_set_clientdata(client, sgtl5000);
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ret = snd_soc_register_codec(&client->dev,
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@ -440,9 +440,8 @@ static int hp_event(struct snd_soc_dapm_widget *w,
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reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY;
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snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
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/* Smallest supported update interval */
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snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
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WM8993_DCS_TIMER_PERIOD_01_MASK, 1);
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WM8993_DCS_TIMER_PERIOD_01_MASK, 0);
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calibrate_dc_servo(codec);
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