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drm/amdgpu: Match TC hash settings to DF settings (v2) 

On Arcturus, data fabric hashing is set by the VBIOS, and
affects which addresses map to which memory channels. The
gfx core's caches also need to know this mapping, but the
hash settings for these these caches is set by the driver.

This change queries the DF to understand how the VBIOS
configured DF, then matches the TC hash configuration bits
to do the same thing.

v2: squash in warning fix

Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Joseph Greathouse 2020-01-09 17:41:43 -06:00 committed by Alex Deucher
parent ae99fc35ce
commit 22d39fe729
3 changed files with 50 additions and 0 deletions
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3
drivers/gpu/drm/amd/amdgpu/df_v1_7.c
View File

@ -31,6 +31,9 @@ static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
static void df_v1_7_sw_init(struct amdgpu_device *adev)
{
adev->df.hash_status.hash_64k = false;
adev->df.hash_status.hash_2m = false;
adev->df.hash_status.hash_1g = false;
}
static void df_v1_7_sw_fini(struct amdgpu_device *adev)

28
drivers/gpu/drm/amd/amdgpu/df_v3_6.c
View File

@ -262,6 +262,32 @@ static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev,
/* device attr for available perfmon counters */
static DEVICE_ATTR(df_cntr_avail, S_IRUGO, df_v3_6_get_df_cntr_avail, NULL);
static void df_v3_6_query_hashes(struct amdgpu_device *adev)
{
u32 tmp;
adev->df.hash_status.hash_64k = false;
adev->df.hash_status.hash_2m = false;
adev->df.hash_status.hash_1g = false;
if (adev->asic_type != CHIP_ARCTURUS)
return;
/* encoding for hash-enabled on Arcturus */
if (adev->df.funcs->get_fb_channel_number(adev) == 0xe) {
tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl);
adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp,
DF_CS_UMC_AON0_DfGlobalCtrl,
GlbHashIntlvCtl64K);
adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp,
DF_CS_UMC_AON0_DfGlobalCtrl,
GlbHashIntlvCtl2M);
adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp,
DF_CS_UMC_AON0_DfGlobalCtrl,
GlbHashIntlvCtl1G);
}
}
/* init perfmons */
static void df_v3_6_sw_init(struct amdgpu_device *adev)
{
@ -273,6 +299,8 @@ static void df_v3_6_sw_init(struct amdgpu_device *adev)
for (i = 0; i < AMDGPU_MAX_DF_PERFMONS; i++)
adev->df_perfmon_config_assign_mask[i] = 0;
df_v3_6_query_hashes(adev);
}
static void df_v3_6_sw_fini(struct amdgpu_device *adev)

19
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@ -3637,6 +3637,23 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
return 0;
}
static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
{
u32 tmp;
if (adev->asic_type != CHIP_ARCTURUS)
return;
tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH,
adev->df.hash_status.hash_64k);
tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH,
adev->df.hash_status.hash_2m);
tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH,
adev->df.hash_status.hash_1g);
WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp);
}
static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
{
if (adev->asic_type != CHIP_ARCTURUS)
@ -3654,6 +3671,8 @@ static int gfx_v9_0_hw_init(void *handle)
gfx_v9_0_constants_init(adev);
gfx_v9_0_init_tcp_config(adev);
r = adev->gfx.rlc.funcs->resume(adev);
if (r)
return r;