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Char / Misc driver changes for 6.0-rc1 

Here is the large set of char and misc and other driver subsystem
 changes for 6.0-rc1.
 
 Highlights include:
 	- large set of IIO driver updates, additions, and cleanups
 	- new habanalabs device support added (loads of register maps
 	  much like GPUs have)
 	- soundwire driver updates
 	- phy driver updates
 	- slimbus driver updates
 	- tiny virt driver fixes and updates
 	- misc driver fixes and updates
 	- interconnect driver updates
 	- hwtracing driver updates
 	- fpga driver updates
 	- extcon driver updates
 	- firmware driver updates
 	- counter driver update
 	- mhi driver fixes and updates
 	- binder driver fixes and updates
 	- speakup driver fixes
 
 Full details are in the long shortlog contents.
 
 All of these have been in linux-next for a while without any reported
 problems.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'char-misc-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char / misc driver updates from Greg KH:
 "Here is the large set of char and misc and other driver subsystem
  changes for 6.0-rc1.

  Highlights include:

   - large set of IIO driver updates, additions, and cleanups

   - new habanalabs device support added (loads of register maps much
     like GPUs have)

   - soundwire driver updates

   - phy driver updates

   - slimbus driver updates

   - tiny virt driver fixes and updates

   - misc driver fixes and updates

   - interconnect driver updates

   - hwtracing driver updates

   - fpga driver updates

   - extcon driver updates

   - firmware driver updates

   - counter driver update

   - mhi driver fixes and updates

   - binder driver fixes and updates

   - speakup driver fixes

  All of these have been in linux-next for a while without any reported
  problems"

* tag 'char-misc-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (634 commits)
  drivers: lkdtm: fix clang -Wformat warning
  char: remove VR41XX related char driver
  misc: Mark MICROCODE_MINOR unused
  spmi: trace: fix stack-out-of-bound access in SPMI tracing functions
  dt-bindings: iio: adc: Add compatible for MT8188
  iio: light: isl29028: Fix the warning in isl29028_remove()
  iio: accel: sca3300: Extend the trigger buffer from 16 to 32 bytes
  iio: fix iio_format_avail_range() printing for none IIO_VAL_INT
  iio: adc: max1027: unlock on error path in max1027_read_single_value()
  iio: proximity: sx9324: add empty line in front of bullet list
  iio: magnetometer: hmc5843: Remove duplicate 'the'
  iio: magn: yas530: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
  iio: magnetometer: ak8974: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
  iio: light: veml6030: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
  iio: light: vcnl4035: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
  iio: light: vcnl4000: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
  iio: light: tsl2591: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr()
  iio: light: tsl2583: Use DEFINE_RUNTIME_DEV_PM_OPS and pm_ptr()
  iio: light: isl29028: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr()
  iio: light: gp2ap002: Switch to DEFINE_RUNTIME_DEV_PM_OPS and pm_ptr()
  ...
This commit is contained in:
Linus Torvalds 2022-08-04 11:05:48 -07:00
parent 798cd57cd5 b5276c9244
commit 228dfe98a3
706 changed files with 184551 additions and 11936 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
Documentation/ABI/testing/debugfs-driver-habanalabs
View File

@ -101,6 +101,15 @@ Description: Specify the size of the DMA transaction when using DMA to read
When the write is finished, the user can read the "data_dma"
blob
What: /sys/kernel/debug/habanalabs/hl<n>/dump_razwi_events
Date: Aug 2022
KernelVersion: 5.20
Contact: fkassabri@habana.ai
Description: Dumps all razwi events to dmesg if exist.
After reading the status register of an existing event
the routine will clear the status register.
Usage: cat dump_razwi_events
What: /sys/kernel/debug/habanalabs/hl<n>/dump_security_violations
Date: Jan 2021
KernelVersion: 5.12
@ -121,14 +130,16 @@ Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Sets I2C device address for I2C transaction that is generated
by the device's CPU
by the device's CPU, Not available when device is loaded with secured
firmware
What: /sys/kernel/debug/habanalabs/hl<n>/i2c_bus
Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Sets I2C bus address for I2C transaction that is generated by
the device's CPU
the device's CPU, Not available when device is loaded with secured
firmware
What: /sys/kernel/debug/habanalabs/hl<n>/i2c_data
Date: Jan 2019
@ -136,39 +147,45 @@ KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Triggers an I2C transaction that is generated by the device's
CPU. Writing to this file generates a write transaction while
reading from the file generates a read transaction
reading from the file generates a read transaction, Not available
when device is loaded with secured firmware
What: /sys/kernel/debug/habanalabs/hl<n>/i2c_len
Date: Dec 2021
KernelVersion: 5.17
Contact: obitton@habana.ai
Description: Sets I2C length in bytes for I2C transaction that is generated by
the device's CPU
the device's CPU, Not available when device is loaded with secured
firmware
What: /sys/kernel/debug/habanalabs/hl<n>/i2c_reg
Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Sets I2C register id for I2C transaction that is generated by
the device's CPU
the device's CPU, Not available when device is loaded with secured
firmware
What: /sys/kernel/debug/habanalabs/hl<n>/led0
Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Sets the state of the first S/W led on the device
Description: Sets the state of the first S/W led on the device, Not available
when device is loaded with secured firmware
What: /sys/kernel/debug/habanalabs/hl<n>/led1
Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Sets the state of the second S/W led on the device
Description: Sets the state of the second S/W led on the device, Not available
when device is loaded with secured firmware
What: /sys/kernel/debug/habanalabs/hl<n>/led2
Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Sets the state of the third S/W led on the device
Description: Sets the state of the third S/W led on the device, Not available
when device is loaded with secured firmware
What: /sys/kernel/debug/habanalabs/hl<n>/memory_scrub
Date: May 2022
@ -182,7 +199,8 @@ Date: May 2022
KernelVersion: 5.19
Contact: dhirschfeld@habana.ai
Description: The value to which the dram will be set to when the user
scrubs the dram using 'memory_scrub' debugfs file
scrubs the dram using 'memory_scrub' debugfs file and
the scrubbing value when using module param 'memory_scrub'
What: /sys/kernel/debug/habanalabs/hl<n>/mmu
Date: Jan 2019
@ -277,7 +295,7 @@ Description: Displays a list with information about the currently user
to DMA addresses
What: /sys/kernel/debug/habanalabs/hl<n>/userptr_lookup
Date: Aug 2021
Date: Oct 2021
KernelVersion: 5.15
Contact: ogabbay@kernel.org
Description: Allows to search for specific user pointers (user virtual

8
Documentation/ABI/testing/sysfs-bus-iio
View File

@ -79,6 +79,11 @@ Description:
* "accel-base"
* "accel-display"
For devices where an accelerometer is housed in the swivel camera subassembly
(for AR application), the following standardized label is used:
* "accel-camera"
What: /sys/bus/iio/devices/iio:deviceX/current_timestamp_clock
KernelVersion: 4.5
Contact: linux-iio@vger.kernel.org
@ -102,6 +107,9 @@ Description:
relevant directories. If it affects all of the above
then it is to be found in the base device directory.
The stm32-timer-trigger has the additional characteristic that
a sampling_frequency of 0 is defined to stop sampling.
What: /sys/bus/iio/devices/iio:deviceX/sampling_frequency_available
What: /sys/bus/iio/devices/iio:deviceX/in_intensity_sampling_frequency_available
What: /sys/bus/iio/devices/iio:deviceX/in_proximity_sampling_frequency_available

1
Documentation/ABI/testing/sysfs-bus-iio-sx9324
View File

@ -5,6 +5,7 @@ Contact: Gwendal Grignou <gwendal@chromium.org>
Description:
SX9324 has 3 inputs, CS0, CS1 and CS2. Hardware layout
defines if the input is
+ not connected (HZ),
+ grounded (GD),
+ connected to an antenna where it can act as a base

31
Documentation/ABI/testing/sysfs-bus-iio-temperature-max31856
View File

@ -1,31 +0,0 @@
What: /sys/bus/iio/devices/iio:deviceX/fault_oc
KernelVersion: 5.1
Contact: linux-iio@vger.kernel.org
Description:
Open-circuit fault. The detection of open-circuit faults,
such as those caused by broken thermocouple wires.
Reading returns either '1' or '0'.
=== =======================================================
'1' An open circuit such as broken thermocouple wires
has been detected.
'0' No open circuit or broken thermocouple wires are detected
=== =======================================================
What: /sys/bus/iio/devices/iio:deviceX/fault_ovuv
KernelVersion: 5.1
Contact: linux-iio@vger.kernel.org
Description:
Overvoltage or Undervoltage Input Fault. The internal circuitry
is protected from excessive voltages applied to the thermocouple
cables by integrated MOSFETs at the T+ and T- inputs, and the
BIAS output. These MOSFETs turn off when the input voltage is
negative or greater than VDD.
Reading returns either '1' or '0'.
=== =======================================================
'1' The input voltage is negative or greater than VDD.
'0' The input voltage is positive and less than VDD (normal
state).
=== =======================================================

20
Documentation/ABI/testing/sysfs-bus-iio-temperature-max31865
View File

@ -1,20 +0,0 @@
What: /sys/bus/iio/devices/iio:deviceX/fault_ovuv
KernelVersion: 5.11
Contact: linux-iio@vger.kernel.org
Description:
Overvoltage or Undervoltage Input fault. The internal circuitry
is protected from excessive voltages applied to the thermocouple
cables at FORCE+, FORCE2, RTDIN+ & RTDIN-. This circuitry turn
off when the input voltage is negative or greater than VDD.
Reading returns '1' if input voltage is negative or greater
than VDD, otherwise '0'.
What: /sys/bus/iio/devices/iio:deviceX/in_filter_notch_center_frequency
KernelVersion: 5.11
Contact: linux-iio@vger.kernel.org
Description:
Notch frequency in Hz for a noise rejection filter. Used i.e for
line noise rejection.
Valid notch filter values are 50 Hz and 60 Hz.

18
Documentation/ABI/testing/sysfs-bus-iio-thermocouple Normal file
View File

@ -0,0 +1,18 @@
What: /sys/bus/iio/devices/iio:deviceX/fault_ovuv
KernelVersion: 5.1
Contact: linux-iio@vger.kernel.org
Description:
Overvoltage or Undervoltage Input Fault. The internal circuitry
is protected from excessive voltages applied to the thermocouple
cables. The device can also detect if such a condition occurs.
Reading returns '1' if input voltage is negative or greater
than VDD, otherwise '0'.
What: /sys/bus/iio/devices/iio:deviceX/fault_oc
KernelVersion: 5.1
Contact: linux-iio@vger.kernel.org
Description:
Open-circuit fault. The detection of open-circuit faults,
such as those caused by broken thermocouple wires.
Reading returns '1' if fault, '0' otherwise.

8
Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
View File

@ -90,14 +90,6 @@ Description:
Reading returns the current master modes.
Writing set the master mode
What: /sys/bus/iio/devices/triggerX/sampling_frequency
KernelVersion: 4.11
Contact: benjamin.gaignard@st.com
Description:
Reading returns the current sampling frequency.
Writing an value different of 0 set and start sampling.
Writing 0 stop sampling.
What: /sys/bus/iio/devices/iio:deviceX/in_count0_preset
KernelVersion: 4.12
Contact: benjamin.gaignard@st.com

33
Documentation/ABI/testing/sysfs-class-vduse Normal file
View File

@ -0,0 +1,33 @@
What: /sys/class/vduse/
Date: Oct 2021
KernelVersion: 5.15
Contact: Yongji Xie <xieyongji@bytedance.com>
Description:
The vduse/ class sub-directory belongs to the VDUSE
framework and provides a sysfs interface for configuring
VDUSE devices.
What: /sys/class/vduse/control/
Date: Oct 2021
KernelVersion: 5.15
Contact: Yongji Xie <xieyongji@bytedance.com>
Description:
This directory entry is created for the control device
of VDUSE framework.
What: /sys/class/vduse/<device-name>/
Date: Oct 2021
KernelVersion: 5.15
Contact: Yongji Xie <xieyongji@bytedance.com>
Description:
This directory entry is created when a VDUSE device is
created via the control device.
What: /sys/class/vduse/<device-name>/msg_timeout
Date: Oct 2021
KernelVersion: 5.15
Contact: Yongji Xie <xieyongji@bytedance.com>
Description:
(RW) The timeout (in seconds) for waiting for the control
message's response from userspace. Default value is 30s.
Writing a '0' to the file means to disable the timeout.

61
Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update Normal file
View File

@ -0,0 +1,61 @@
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_root_entry_hash
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns the root entry hash for the static
region if one is programmed, else it returns the
string: "hash not programmed". This file is only
visible if the underlying device supports it.
Format: string.
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_root_entry_hash
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns the root entry hash for the partial
reconfiguration region if one is programmed, else it
returns the string: "hash not programmed". This file
is only visible if the underlying device supports it.
Format: string.
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_root_entry_hash
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns the root entry hash for the BMC image
if one is programmed, else it returns the string:
"hash not programmed". This file is only visible if the
underlying device supports it.
Format: string.
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_canceled_csks
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns a list of indices for canceled code
signing keys for the static region. The standard bitmap
list format is used (e.g. "1,2-6,9").
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_canceled_csks
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns a list of indices for canceled code
signing keys for the partial reconfiguration region. The
standard bitmap list format is used (e.g. "1,2-6,9").
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_canceled_csks
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns a list of indices for canceled code
signing keys for the BMC. The standard bitmap list format
is used (e.g. "1,2-6,9").
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/flash_count
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns number of times the secure update
staging area has been flashed.
Format: "%u".

101
Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml Normal file
View File

@ -0,0 +1,101 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Coresight Address Translation Unit (CATU)
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The CoreSight Address Translation Unit (CATU) translates addresses between an
AXI master and system memory. The CATU is normally used along with the TMC to
implement scattering of virtual trace buffers in physical memory. The CATU
translates contiguous Virtual Addresses (VAs) from an AXI master into
non-contiguous Physical Addresses (PAs) that are intended for system memory.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-catu
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-catu
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
interrupts:
maxItems: 1
description: Address translation error interrupt
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: AXI Slave connected to another Coresight component
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
catu@207e0000 {
compatible = "arm,coresight-catu", "arm,primecell";
reg = <0x207e0000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
in-ports {
port {
catu_in_port: endpoint {
remote-endpoint = <&etr_out_port>;
};
};
};
};
...

81
Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml Normal file
View File

@ -0,0 +1,81 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CoreSight CPU Debug Component
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight CPU debug component are compliant with the ARMv8 architecture
reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
external debug module is mainly used for two modes: self-hosted debug and
external debug, and it can be accessed from mmio region from Coresight and
eventually the debug module connects with CPU for debugging. And the debug
module provides sample-based profiling extension, which can be used to sample
CPU program counter, secure state and exception level, etc; usually every CPU
has one dedicated debug module to be connected.
select:
properties:
compatible:
contains:
const: arm,coresight-cpu-debug
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-cpu-debug
- const: arm,primecell
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
maxItems: 1
cpu:
description:
A phandle to the cpu this debug component is bound to.
$ref: /schemas/types.yaml#/definitions/phandle
power-domains:
maxItems: 1
description:
A phandle to the debug power domain if the debug logic has its own
dedicated power domain. CPU idle states may also need to be separately
constrained to keep CPU cores powered.
required:
- compatible
- reg
- clocks
- clock-names
- cpu
unevaluatedProperties: false
examples:
- |
debug@f6590000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0xf6590000 0x1000>;
clocks = <&sys_ctrl 1>;
clock-names = "apb_pclk";
cpu = <&cpu0>;
};
...

5
Documentation/devicetree/bindings/arm/coresight-cti.yaml → Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
View File

@ -2,7 +2,7 @@
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
$id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Coresight Cross Trigger Interface (CTI) device.
@ -12,8 +12,7 @@ description: |
to one or more CoreSight components and/or a CPU, with CTIs interconnected in
a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
The ECT components are not part of the trace generation data path and are thus
not part of the CoreSight graph described in the general CoreSight bindings
file coresight.txt.
not part of the CoreSight graph.
The CTI component properties define the connections between the individual
CTI and the components it is directly connected to, consisting of input and

126
Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml Normal file
View File

@ -0,0 +1,126 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-funnel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Programmable Trace Bus Funnel
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight funnel merges 2-8 trace sources into a single trace
stream with programmable enable and priority of input ports.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-dynamic-funnel
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-dynamic-funnel
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port(@[0-7])?$':
description: Input connections from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
- out-ports
unevaluatedProperties: false
examples:
- |
funnel@20040000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x20040000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_out_port0: endpoint {
remote-endpoint = <&replicator_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_in_port0: endpoint {
remote-endpoint = <&ptm0_out_port>;
};
};
port@1 {
reg = <1>;
funnel_in_port1: endpoint {
remote-endpoint = <&ptm1_out_port>;
};
};
port@2 {
reg = <2>;
funnel_in_port2: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
};
};
...

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-replicator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Coresight Programmable Trace Bus Replicator
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight replicator splits a single trace stream into two trace streams
for systems that have more than one trace sink component.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-dynamic-replicator
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-dynamic-replicator
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
qcom,replicator-loses-context:
type: boolean
description:
Indicates that the replicator will lose register context when AMBA clock
is removed which is observed in some replicator designs.
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port(@[01])?$':
description: Output connections to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
- out-ports
unevaluatedProperties: false
examples:
- |
replicator@20120000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x20120000 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&etr_in_port>;
};
};
};
in-ports {
port {
replicator_in_port0: endpoint {
remote-endpoint = <&csys2_funnel_out_port>;
};
};
};
};
...

92
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-etb10.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Embedded Trace Buffer
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The CoreSight Embedded Trace Buffer stores traces in a dedicated SRAM that is
used as a circular buffer.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-etb10
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-etb10
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
etb@20010000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x20010000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
in-ports {
port {
etb_in_port: endpoint {
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
...

156
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Embedded Trace MacroCell
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Embedded Trace Macrocell (ETM) is a real-time trace module providing
instruction and data tracing of a processor.
select:
properties:
compatible:
contains:
enum:
- arm,coresight-etm3x
- arm,coresight-etm4x
- arm,coresight-etm4x-sysreg
required:
- compatible
allOf:
- if:
not:
properties:
compatible:
contains:
const: arm,coresight-etm4x-sysreg
then:
$ref: /schemas/arm/primecell.yaml#
required:
- reg
properties:
compatible:
oneOf:
- description:
Embedded Trace Macrocell with memory mapped access.
items:
- enum:
- arm,coresight-etm3x
- arm,coresight-etm4x
- const: arm,primecell
- description:
Embedded Trace Macrocell (version 4.x), with system register access only
const: arm,coresight-etm4x-sysreg
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
arm,coresight-loses-context-with-cpu:
type: boolean
description:
Indicates that the hardware will lose register context on CPU power down
(e.g. CPUIdle). An example of where this may be needed are systems which
contain a coresight component and CPU in the same power domain. When the
CPU powers down the coresight component also powers down and loses its
context.
arm,cp14:
type: boolean
description:
Must be present if the system accesses ETM/PTM management registers via
co-processor 14.
qcom,skip-power-up:
type: boolean
description:
Indicates that an implementation can skip powering up the trace unit.
TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
since ETMs are in the same power domain as their CPU cores. This property
is required to identify such systems with hardware errata where the CPU
watchdog counter is stopped when TRCPDCR.PU is set.
cpu:
description:
phandle to the cpu this ETM is bound to.
$ref: /schemas/types.yaml#/definitions/phandle
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection from the ETM to CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- clocks
- clock-names
- cpu
- out-ports
unevaluatedProperties: false
examples:
- |
ptm@2201c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x2201c000 0x1000>;
cpu = <&cpu0>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel_in_port0>;
};
};
};
};
ptm@2201d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x2201d000 0x1000>;
cpu = <&cpu1>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
ptm1_out_port: endpoint {
remote-endpoint = <&funnel_in_port1>;
};
};
};
};
...

90
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@ -0,0 +1,90 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Static Trace Bus Funnel
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight static funnel merges 2-8 trace sources into a single trace
stream.
properties:
compatible:
const: arm,coresight-static-funnel
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port@[0-7]$':
description: Input connections from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- in-ports
- out-ports
additionalProperties: false
examples:
- |
funnel {
/*
* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
out-ports {
port {
combo_funnel_out: endpoint {
remote-endpoint = <&top_funnel_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
combo_funnel_in0: endpoint {
remote-endpoint = <&cluster0_etf_out>;
};
};
port@1 {
reg = <1>;
combo_funnel_in1: endpoint {
remote-endpoint = <&cluster1_etf_out>;
};
};
};
};
...

91
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@ -0,0 +1,91 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Static Trace Bus Replicator
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight replicator splits a single trace stream into two trace streams
for systems that have more than one trace sink component.
properties:
compatible:
const: arm,coresight-static-replicator
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port@[01]$':
description: Output connections to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- in-ports
- out-ports
additionalProperties: false
examples:
- |
replicator {
/*
* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&etb_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
};
in-ports {
port {
replicator_in_port0: endpoint {
remote-endpoint = <&funnel_out_port0>;
};
};
};
};
...

101
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight System Trace MacroCell
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The STM is a trace source that is integrated into a CoreSight system, designed
primarily for high-bandwidth trace of instrumentation embedded into software.
This instrumentation is made up of memory-mapped writes to the STM Advanced
eXtensible Interface (AXI) slave, which carry information about the behavior
of the software.
select:
properties:
compatible:
contains:
const: arm,coresight-stm
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-stm
- const: arm,primecell
reg:
maxItems: 2
reg-names:
items:
- const: stm-base
- const: stm-stimulus-base
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- out-ports
unevaluatedProperties: false
examples:
- |
stm@20100000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x20100000 0x1000>,
<0x28000000 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
out-ports {
port {
stm_out_port: endpoint {
remote-endpoint = <&main_funnel_in_port2>;
};
};
};
};
...

131
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Trace Memory Controller
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace
FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-tmc
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-tmc
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
arm,buffer-size:
$ref: /schemas/types.yaml#/definitions/uint32
deprecated: true
description:
Size of contiguous buffer space for TMC ETR (embedded trace router). The
buffer size can be configured dynamically via buffer_size property in
sysfs instead.
arm,scatter-gather:
type: boolean
description:
Indicates that the TMC-ETR can safely use the SG mode on this system.
arm,max-burst-size:
description:
The maximum burst size initiated by TMC on the AXI master interface. The
burst size can be in the range [0..15], the setting supports one data
transfer per burst up to a maximum of 16 data transfers per burst.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: AXI or ATB Master output connection. Used for ETR
and ETF configurations.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
etr@20070000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x20070000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
in-ports {
port {
etr_in_port: endpoint {
remote-endpoint = <&replicator2_out_port0>;
};
};
};
out-ports {
port {
etr_out_port: endpoint {
remote-endpoint = <&catu_in_port>;
};
};
};
};
...

91
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@ -0,0 +1,91 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Trace Port Interface Unit
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The CoreSight Trace Port Interface Unit captures trace data from the trace bus
and outputs it to an external trace port.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-tpiu
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-tpiu
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
tpiu@e3c05000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0xe3c05000 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
in-ports {
port {
tpiu_in_port: endpoint {
remote-endpoint = <&funnel4_out_port0>;
};
};
};
};
...

3
Documentation/devicetree/bindings/arm/ete.yaml → Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml
View File

@ -2,7 +2,7 @@
# Copyright 2021, Arm Ltd
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/ete.yaml#"
$id: "http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ARM Embedded Trace Extensions
@ -20,7 +20,6 @@ description: |
Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
legacy CoreSight components, a node must be listed per instance, along
with any optional connection graph as per the coresight bindings.
See bindings/arm/coresight.txt.
properties:
$nodename:

2
Documentation/devicetree/bindings/arm/trbe.yaml → Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
View File

@ -2,7 +2,7 @@
# Copyright 2021, Arm Ltd
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/trbe.yaml#"
$id: "http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ARM Trace Buffer Extensions

49
Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
View File

@ -1,49 +0,0 @@
* CoreSight CPU Debug Component:
CoreSight CPU debug component are compliant with the ARMv8 architecture
reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
external debug module is mainly used for two modes: self-hosted debug and
external debug, and it can be accessed from mmio region from Coresight
and eventually the debug module connects with CPU for debugging. And the
debug module provides sample-based profiling extension, which can be used
to sample CPU program counter, secure state and exception level, etc;
usually every CPU has one dedicated debug module to be connected.
Required properties:
- compatible : should be "arm,coresight-cpu-debug"; supplemented with
"arm,primecell" since this driver is using the AMBA bus
interface.
- reg : physical base address and length of the register set.
- clocks : the clock associated to this component.
- clock-names : the name of the clock referenced by the code. Since we are
using the AMBA framework, the name of the clock providing
the interconnect should be "apb_pclk" and the clock is
mandatory. The interface between the debug logic and the
processor core is clocked by the internal CPU clock, so it
is enabled with CPU clock by default.
- cpu : the CPU phandle the debug module is affined to. Do not assume it
to default to CPU0 if omitted.
Optional properties:
- power-domains: a phandle to the debug power domain. We use "power-domains"
binding to turn on the debug logic if it has own dedicated
power domain and if necessary to use "cpuidle.off=1" or
"nohlt" in the kernel command line or sysfs node to
constrain idle states to ensure registers in the CPU power
domain are accessible.
Example:
debug@f6590000 {
compatible = "arm,coresight-cpu-debug","arm,primecell";
reg = <0 0xf6590000 0 0x1000>;
clocks = <&sys_ctrl HI6220_DAPB_CLK>;
clock-names = "apb_pclk";
cpu = <&cpu0>;
};

402
Documentation/devicetree/bindings/arm/coresight.txt
View File

@ -1,402 +0,0 @@
* CoreSight Components:
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink. Each CoreSight component device should use these properties to describe
its hardware characteristcs.
* Required properties for all components *except* non-configurable replicators
and non-configurable funnels:
* compatible: These have to be supplemented with "arm,primecell" as
drivers are using the AMBA bus interface. Possible values include:
- Embedded Trace Buffer (version 1.0):
"arm,coresight-etb10", "arm,primecell";
- Trace Port Interface Unit:
"arm,coresight-tpiu", "arm,primecell";
- Trace Memory Controller, used for Embedded Trace Buffer(ETB),
Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
configuration. The configuration mode (ETB, ETF, ETR) is
discovered at boot time when the device is probed.
"arm,coresight-tmc", "arm,primecell";
- Trace Programmable Funnel:
"arm,coresight-dynamic-funnel", "arm,primecell";
"arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
backward compatibility and will be removed)
- Embedded Trace Macrocell (version 3.x) and
Program Flow Trace Macrocell:
"arm,coresight-etm3x", "arm,primecell";
- Embedded Trace Macrocell (version 4.x), with memory mapped access.
"arm,coresight-etm4x", "arm,primecell";
- Embedded Trace Macrocell (version 4.x), with system register access only.
"arm,coresight-etm4x-sysreg";
- Coresight programmable Replicator :
"arm,coresight-dynamic-replicator", "arm,primecell";
- System Trace Macrocell:
"arm,coresight-stm", "arm,primecell"; [1]
- Coresight Address Translation Unit (CATU)
"arm,coresight-catu", "arm,primecell";
- Coresight Cross Trigger Interface (CTI):
"arm,coresight-cti", "arm,primecell";
See coresight-cti.yaml for full CTI definitions.
* reg: physical base address and length of the register
set(s) of the component.
* clocks: the clocks associated to this component.
* clock-names: the name of the clocks referenced by the code.
Since we are using the AMBA framework, the name of the clock
providing the interconnect should be "apb_pclk", and some
coresight blocks also have an additional clock "atclk", which
clocks the core of that coresight component. The latter clock
is optional.
* port or ports: see "Graph bindings for Coresight" below.
* Additional required property for Embedded Trace Macrocell (version 3.x and
version 4.x):
* cpu: the cpu phandle this ETM/PTM is affined to. Do not
assume it to default to CPU0 if omitted.
* Additional required properties for System Trace Macrocells (STM):
* reg: along with the physical base address and length of the register
set as described above, another entry is required to describe the
mapping of the extended stimulus port area.
* reg-names: the only acceptable values are "stm-base" and
"stm-stimulus-base", each corresponding to the areas defined in "reg".
* Required properties for Coresight Cross Trigger Interface (CTI)
See coresight-cti.yaml for full CTI definitions.
* Required properties for devices that don't show up on the AMBA bus, such as
non-configurable replicators and non-configurable funnels:
* compatible: Currently supported value is (note the absence of the
AMBA markee):
- Coresight Non-configurable Replicator:
"arm,coresight-static-replicator";
"arm,coresight-replicator"; (OBSOLETE. For backward
compatibility and will be removed)
- Coresight Non-configurable Funnel:
"arm,coresight-static-funnel";
* port or ports: see "Graph bindings for Coresight" below.
* Optional properties for all components:
* arm,coresight-loses-context-with-cpu : boolean. Indicates that the
hardware will lose register context on CPU power down (e.g. CPUIdle).
An example of where this may be needed are systems which contain a
coresight component and CPU in the same power domain. When the CPU
powers down the coresight component also powers down and loses its
context. This property is currently only used for the ETM 4.x driver.
* Optional properties for ETM/PTMs:
* arm,cp14: must be present if the system accesses ETM/PTM management
registers via co-processor 14.
* qcom,skip-power-up: boolean. Indicates that an implementation can
skip powering up the trace unit. TRCPDCR.PU does not have to be set
on Qualcomm Technologies Inc. systems since ETMs are in the same power
domain as their CPU cores. This property is required to identify such
systems with hardware errata where the CPU watchdog counter is stopped
when TRCPDCR.PU is set.
* Optional property for TMC:
* arm,buffer-size: size of contiguous buffer space for TMC ETR
(embedded trace router). This property is obsolete. The buffer size
can be configured dynamically via buffer_size property in sysfs.
* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
use the SG mode on this system.
* arm,max-burst-size: The maximum burst size initiated by TMC on the
AXI master interface. The burst size can be in the range [0..15],
the setting supports one data transfer per burst up to a maximum of
16 data transfers per burst.
* Optional property for CATU :
* interrupts : Exactly one SPI may be listed for reporting the address
error
* Optional property for configurable replicators:
* qcom,replicator-loses-context: boolean. Indicates that the replicator
will lose register context when AMBA clock is removed which is observed
in some replicator designs.
Graph bindings for Coresight
-------------------------------
Coresight components are interconnected to create a data path for the flow of
trace data generated from the "sources" to their collection points "sink".
Each coresight component must describe the "input" and "output" connections.
The connections must be described via generic DT graph bindings as described
by the "bindings/graph.txt", where each "port" along with an "endpoint"
component represents a hardware port and the connection.
* All output ports must be listed inside a child node named "out-ports"
* All input ports must be listed inside a child node named "in-ports".
* Port address must match the hardware port number.
Example:
1. Sinks
etb@20010000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0x20010000 0 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
in-ports {
port {
etb_in_port: endpoint@0 {
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
tpiu@20030000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0 0x20030000 0 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
in-ports {
port {
tpiu_in_port: endpoint@0 {
remote-endpoint = <&replicator_out_port1>;
};
};
};
};
etr@20070000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x20070000 0 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
in-ports {
port {
etr_in_port: endpoint {
remote-endpoint = <&replicator2_out_port0>;
};
};
};
out-ports {
port {
etr_out_port: endpoint {
remote-endpoint = <&catu_in_port>;
};
};
};
};
2. Links
replicator {
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&etb_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
};
in-ports {
port {
replicator_in_port0: endpoint {
remote-endpoint = <&funnel_out_port0>;
};
};
};
};
funnel {
/*
* non-configurable funnel don't show up on the AMBA
* bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
clocks = <&crg_ctrl HI3660_PCLK>;
clock-names = "apb_pclk";
out-ports {
port {
combo_funnel_out: endpoint {
remote-endpoint = <&top_funnel_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
combo_funnel_in0: endpoint {
remote-endpoint = <&cluster0_etf_out>;
};
};
port@1 {
reg = <1>;
combo_funnel_in1: endpoint {
remote-endpoint = <&cluster1_etf_out>;
};
};
};
};
funnel@20040000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x20040000 0 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_out_port0: endpoint {
remote-endpoint =
<&replicator_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_in_port0: endpoint {
remote-endpoint = <&ptm0_out_port>;
};
};
port@1 {
reg = <1>;
funnel_in_port1: endpoint {
remote-endpoint = <&ptm1_out_port>;
};
};
port@2 {
reg = <2>;
funnel_in_port2: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
};
};
3. Sources
ptm@2201c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0x2201c000 0 0x1000>;
cpu = <&cpu0>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel_in_port0>;
};
};
};
};
ptm@2201d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0x2201d000 0 0x1000>;
cpu = <&cpu1>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
ptm1_out_port: endpoint {
remote-endpoint = <&funnel_in_port1>;
};
};
};
};
4. STM
stm@20100000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x20100000 0 0x1000>,
<0 0x28000000 0 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
out-ports {
port {
stm_out_port: endpoint {
remote-endpoint = <&main_funnel_in_port2>;
};
};
};
};
5. CATU
catu@207e0000 {
compatible = "arm,coresight-catu", "arm,primecell";
reg = <0 0x207e0000 0 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
in-ports {
port {
catu_in_port: endpoint {
remote-endpoint = <&etr_out_port>;
};
};
};
};
[1]. There is currently two version of STM: STM32 and STM500. Both
have the same HW interface and as such don't need an explicit binding name.

44
Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml Normal file
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@ -0,0 +1,44 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip Polarfire FPGA manager.
maintainers:
- Ivan Bornyakov <i.bornyakov@metrotek.ru>
description:
Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
load the bitstream in .dat format.
properties:
compatible:
enum:
- microchip,mpf-spi-fpga-mgr
reg:
description: SPI chip select
maxItems: 1
spi-max-frequency: true
required:
- compatible
- reg
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
fpga_mgr@0 {
compatible = "microchip,mpf-spi-fpga-mgr";
spi-max-frequency = <20000000>;
reg = <0>;
};
};

2
Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ADIS16240 Programmable Impact Sensor and Recorder driver
maintainers:
- Alexandru Ardelean <alexandru.ardelean@analog.com>
- Alexandru Tachici <alexandru.tachici@analog.com>
description: |
ADIS16240 Programmable Impact Sensor and Recorder driver that supports

2
Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml
View File

@ -55,7 +55,7 @@ examples:
/* Example for a I2C device node */
accelerometer@2a {
compatible = "adi,adxl345";
reg = <0x53>;
reg = <0x2a>;
interrupt-parent = <&gpio0>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};

2
Documentation/devicetree/bindings/iio/accel/bosch,bmi088.yaml
View File

@ -17,7 +17,9 @@ description: |
properties:
compatible:
enum:
- bosch,bmi085-accel
- bosch,bmi088-accel
- bosch,bmi090l-accel
reg:
maxItems: 1

1
Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml
View File

@ -17,6 +17,7 @@ properties:
compatible:
enum:
- murata,sca3300
- murata,scl3300
reg:
maxItems: 1

1
Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml
View File

@ -8,7 +8,6 @@ title: Analog Devices AD9467 and similar High-Speed ADCs
maintainers:
- Michael Hennerich <michael.hennerich@analog.com>
- Alexandru Ardelean <alexandru.ardelean@analog.com>
description: |
The AD9467 and the parts similar with it, are high-speed analog-to-digital

1
Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml
View File

@ -8,7 +8,6 @@ title: Analog Devices AXI ADC IP core
maintainers:
- Michael Hennerich <michael.hennerich@analog.com>
- Alexandru Ardelean <alexandru.ardelean@analog.com>
description: |
Analog Devices Generic AXI ADC IP core for interfacing an ADC device

9
Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml
View File

@ -14,7 +14,14 @@ description:
properties:
compatible:
const: fsl,vf610-adc
oneOf:
- items:
- enum:
- fsl,imx6sx-adc
- fsl,imx6ul-adc
- const: fsl,vf610-adc
- items:
- const: fsl,vf610-adc
reg:
maxItems: 1

1
Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
View File

@ -35,6 +35,7 @@ properties:
- enum:
- mediatek,mt8183-auxadc
- mediatek,mt8186-auxadc
- mediatek,mt8188-auxadc
- mediatek,mt8195-auxadc
- mediatek,mt8516-auxadc
- const: mediatek,mt8173-auxadc

7
Documentation/devicetree/bindings/iio/adc/nuvoton,npcm750-adc.yaml
View File

@ -10,11 +10,14 @@ maintainers:
- Tomer Maimon <tmaimon77@gmail.com>
description:
The NPCM ADC is a 10-bit converter for eight channel inputs.
The NPCM7XX ADC is a 10-bit converter and NPCM8XX ADC is a 12-bit converter,
both have eight channel inputs.
properties:
compatible:
const: nuvoton,npcm750-adc
enum:
- nuvoton,npcm750-adc
- nuvoton,npcm845-adc
reg:
maxItems: 1

51
Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml Normal file
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@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-rradc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm's SPMI PMIC Round Robin ADC
maintainers:
- Caleb Connolly <caleb.connolly@linaro.org>
description: |
The Qualcomm SPMI Round Robin ADC (RRADC) provides interface to clients to
read the voltage, current and temperature for supported peripherals such as
the battery thermistor die temperature, charger temperature, USB and DC input
voltage / current and battery ID resistor.
properties:
compatible:
enum:
- qcom,pmi8998-rradc
- qcom,pm660-rradc
reg:
maxItems: 1
qcom,batt-id-delay-ms:
description: Sets the hardware settling time for the battery ID resistor.
enum: [0, 1, 4, 12, 20, 40, 60, 80]
"#io-channel-cells":
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pmic {
#address-cells = <1>;
#size-cells = <0>;
pmic_rradc: adc@4500 {
compatible = "qcom,pmi8998-rradc";
reg = <0x4500>;
#io-channel-cells = <1>;
};
};

28
Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
View File

@ -19,6 +19,7 @@ properties:
compatible:
items:
- enum:
- renesas,r9a07g043-adc # RZ/G2UL
- renesas,r9a07g044-adc # RZ/G2L
- renesas,r9a07g054-adc # RZ/V2L
- const: renesas,rzg2l-adc
@ -76,16 +77,35 @@ patternProperties:
properties:
reg:
description: |
The channel number. It can have up to 8 channels numbered from 0 to 7.
items:
- minimum: 0
maximum: 7
The channel number.
required:
- reg
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: renesas,r9a07g043-adc
then:
patternProperties:
"^channel@[2-7]$": false
"^channel@[0-1]$":
properties:
reg:
minimum: 0
maximum: 1
else:
patternProperties:
"^channel@[0-7]$":
properties:
reg:
minimum: 0
maximum: 7
additionalProperties: false
examples:

2
Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml
View File

@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD5770R DAC device driver
maintainers:
- Mircea Caprioru <mircea.caprioru@analog.com>
- Alexandru Tachici <alexandru.tachici@analog.com>
description: |
Bindings for the Analog Devices AD5770R current DAC device. Datasheet can be

1
Documentation/devicetree/bindings/iio/dac/microchip,mcp4922.yaml
View File

@ -15,6 +15,7 @@ properties:
enum:
- microchip,mcp4902
- microchip,mcp4912
- microchip,mcp4921
- microchip,mcp4922
reg:

1
Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml
View File

@ -21,6 +21,7 @@ properties:
- ti,dac5573
- ti,dac6573
- ti,dac7573
- ti,dac121c081
reg:
maxItems: 1

2
Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices ADIS16480 and similar IMUs
maintainers:
- Alexandru Ardelean <alexandru.ardelean@analog.com>
- Alexandru Tachici <alexandru.tachici@analog.com>
properties:
compatible:

39
Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml
View File

@ -126,6 +126,42 @@ properties:
UINT_MAX (4294967295) represents infinite. Other values
represent 1-1/N.
semtech,cs-idle-sleep:
description:
State of CS pins during sleep mode and idle time.
enum:
- hi-z
- gnd
- vdd
semtech,int-comp-resistor:
description:
Internal resistor setting for compensation.
enum:
- lowest
- low
- high
- highest
semtech,input-precharge-resistor-ohms:
default: 4000
multipleOf: 2000
minimum: 0
maximum: 30000
description:
Pre-charge input resistance in Ohm.
semtech,input-analog-gain:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
description: |
Defines the input antenna analog gain
0: x1.247
1: x1 (default)
2: x0.768
3: x0.552
required:
- compatible
- reg
@ -157,5 +193,8 @@ examples:
semtech,ph01-proxraw-strength = <2>;
semtech,ph23-proxraw-strength = <2>;
semtech,avg-pos-strength = <64>;
semtech,int-comp-resistor = "lowest";
semtech,input-precharge-resistor-ohms = <2000>;
semtech,cs-idle-sleep = "gnd";
};
};

9
Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
View File

@ -61,6 +61,14 @@ properties:
UINT_MAX (4294967295) represents infinite. Other values
represent 1-1/N.
semtech,input-precharge-resistor-ohms:
default: 0
multipleOf: 2000
minimum: 0
maximum: 30000
description:
Pre-charge input resistance in Ohm.
required:
- compatible
- reg
@ -85,5 +93,6 @@ examples:
semtech,resolution = <256>;
semtech,proxraw-strength = <2>;
semtech,avg-pos-strength = <64>;
semtech,input-precharge-resistor-ohms = <4000>;
};
};

5
Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml
View File

@ -19,6 +19,11 @@ properties:
interrupts:
maxItems: 1
reset-gpios:
maxItems: 1
vdd-supply: true
required:
- compatible
- reg

6
Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml
View File

@ -26,14 +26,16 @@ properties:
oneOf:
- items:
- enum:
- fsl,imx8mn-nic
- fsl,imx8mm-nic
- fsl,imx8mn-nic
- fsl,imx8mp-nic
- fsl,imx8mq-nic
- const: fsl,imx8m-nic
- items:
- enum:
- fsl,imx8mn-noc
- fsl,imx8mm-noc
- fsl,imx8mn-noc
- fsl,imx8mp-noc
- fsl,imx8mq-noc
- const: fsl,imx8m-noc
- const: fsl,imx8m-nic

6
Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
View File

@ -45,7 +45,11 @@ properties:
- qcom,sdm660-snoc
'#interconnect-cells':
const: 1
description: |
Value: <1> is one cell in an interconnect specifier for the
interconnect node id, <2> requires the interconnect node id and an
extra path tag.
enum: [ 1, 2 ]
clocks:
minItems: 2

43
Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml Normal file
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@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,rpmh-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect
maintainers:
- Georgi Djakov <djakov@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
description:
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
properties:
'#interconnect-cells':
enum: [ 1, 2 ]
qcom,bcm-voters:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
maxItems: 2
description:
List of phandles to qcom,bcm-voter nodes that are required by
this interconnect to send RPMh commands.
qcom,bcm-voter-names:
maxItems: 2
description:
Names for each of the qcom,bcm-voters specified.
required:
- '#interconnect-cells'
- qcom,bcm-voters
additionalProperties: true

22
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
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@ -18,6 +18,9 @@ description: |
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
allOf:
- $ref: qcom,rpmh-common.yaml#
properties:
reg:
maxItems: 1
@ -130,28 +133,13 @@ properties:
- qcom,sm8450-pcie-anoc
- qcom,sm8450-system-noc
'#interconnect-cells':
enum: [ 1, 2 ]
qcom,bcm-voters:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description: |
List of phandles to qcom,bcm-voter nodes that are required by
this interconnect to send RPMh commands.
qcom,bcm-voter-names:
description: |
Names for each of the qcom,bcm-voters specified.
'#interconnect-cells': true
required:
- compatible
- reg
- '#interconnect-cells'
- qcom,bcm-voters
additionalProperties: false
unevaluatedProperties: false
examples:
- |

82
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@ -0,0 +1,82 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sm6350-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM6350 RPMh Network-On-Chip Interconnect
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description:
Qualcomm RPMh-based interconnect provider on SM6350.
allOf:
- $ref: qcom,rpmh-common.yaml#
properties:
compatible:
enum:
- qcom,sm6350-aggre1-noc
- qcom,sm6350-aggre2-noc
- qcom,sm6350-config-noc
- qcom,sm6350-dc-noc
- qcom,sm6350-gem-noc
- qcom,sm6350-mmss-noc
- qcom,sm6350-npu-noc
- qcom,sm6350-system-noc
reg:
maxItems: 1
'#interconnect-cells': true
patternProperties:
'^interconnect-[a-z0-9\-]+$':
type: object
description:
The interconnect providers do not have a separate QoS register space,
but share parent's space.
$ref: qcom,rpmh-common.yaml#
properties:
compatible:
enum:
- qcom,sm6350-clk-virt
- qcom,sm6350-compute-noc
'#interconnect-cells': true
required:
- compatible
unevaluatedProperties: false
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
config_noc: interconnect@1500000 {
compatible = "qcom,sm6350-config-noc";
reg = <0x01500000 0x28000>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1620000 {
compatible = "qcom,sm6350-system-noc";
reg = <0x01620000 0x17080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
clk_virt: interconnect-clk-virt {
compatible = "qcom,sm6350-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
};

51
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@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/qemu,vcpu-stall-detector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: VCPU stall detector
description:
This binding describes a CPU stall detector mechanism for virtual CPUs
which is accessed through MMIO.
maintainers:
- Sebastian Ene <sebastianene@google.com>
properties:
compatible:
enum:
- qemu,vcpu-stall-detector
reg:
maxItems: 1
clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
The internal clock of the stall detector peripheral measure in Hz used
to decrement its internal counter register on each tick.
Defaults to 10 if unset.
default: 10
timeout-sec:
description: |
The stall detector expiration timeout measured in seconds.
Defaults to 8 if unset. Please note that it also takes into account the
time spent while the VCPU is not running.
default: 8
required:
- compatible
additionalProperties: false
examples:
- |
vmwdt@9030000 {
compatible = "qemu,vcpu-stall-detector";
reg = <0x9030000 0x10000>;
clock-frequency = <10>;
timeout-sec = <8>;
};

89
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@ -0,0 +1,89 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/mediatek,efuse.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek efuse
description: |
MediaTek's efuse is used for storing calibration data, it can be accessed
on ARM devices usiong I/O mapped memory.
maintainers:
- Andrew-CT Chen <andrew-ct.chen@mediatek.com>
- Lala Lin <lala.lin@mediatek.com>
allOf:
- $ref: "nvmem.yaml#"
properties:
$nodename:
pattern: "^efuse@[0-9a-f]+$"
compatible:
oneOf:
- items:
- enum:
- mediatek,mt7622-efuse
- mediatek,mt7623-efuse
- mediatek,mt8173-efuse
- mediatek,mt8183-efuse
- mediatek,mt8186-efuse
- mediatek,mt8192-efuse
- mediatek,mt8195-efuse
- mediatek,mt8516-efuse
- const: mediatek,efuse
- const: mediatek,mt8173-efuse
deprecated: true
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
efuse@11c10000 {
compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
reg = <0x11c10000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
u3_tx_imp_p0: usb3-tx-imp@184,1 {
reg = <0x184 0x1>;
bits = <0 5>;
};
u3_rx_imp_p0: usb3-rx-imp@184,2 {
reg = <0x184 0x2>;
bits = <5 5>;
};
u3_intr_p0: usb3-intr@185 {
reg = <0x185 0x1>;
bits = <2 6>;
};
comb_tx_imp_p1: usb3-tx-imp@186,1 {
reg = <0x186 0x1>;
bits = <0 5>;
};
comb_rx_imp_p1: usb3-rx-imp@186,2 {
reg = <0x186 0x2>;
bits = <5 5>;
};
comb_intr_p1: usb3-intr@187 {
reg = <0x187 0x1>;
bits = <2 6>;
};
u2_intr_p0: usb2-intr-p0@188,1 {
reg = <0x188 0x1>;
bits = <0 5>;
};
u2_intr_p1: usb2-intr-p1@188,2 {
reg = <0x188 0x2>;
bits = <5 5>;
};
};

50
Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml Normal file
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@ -0,0 +1,50 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/microchip,sama7g5-otpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip SAMA7G5 OTP Controller (OTPC)
maintainers:
- Claudiu Beznea <claudiu.beznea@microchip.com>
description: |
OTP controller drives a NVMEM memory where system specific data
(e.g. calibration data for analog cells, hardware configuration
settings, chip identifiers) or user specific data could be stored.
allOf:
- $ref: "nvmem.yaml#"
properties:
compatible:
items:
- const: microchip,sama7g5-otpc
- const: syscon
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
otpc: efuse@e8c00000 {
compatible = "microchip,sama7g5-otpc", "syscon";
reg = <0xe8c00000 0xec>;
#address-cells = <1>;
#size-cells = <1>;
temperature_calib: calib@1 {
reg = <OTP_PKT(1) 76>;
};
};
...

43
Documentation/devicetree/bindings/nvmem/mtk-efuse.txt
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@ -1,43 +0,0 @@
= Mediatek MTK-EFUSE device tree bindings =
This binding is intended to represent MTK-EFUSE which is found in most Mediatek SOCs.
Required properties:
- compatible: should be
"mediatek,mt7622-efuse", "mediatek,efuse": for MT7622
"mediatek,mt7623-efuse", "mediatek,efuse": for MT7623
"mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173
"mediatek,mt8192-efuse", "mediatek,efuse": for MT8192
"mediatek,mt8195-efuse", "mediatek,efuse": for MT8195
"mediatek,mt8516-efuse", "mediatek,efuse": for MT8516
- reg: Should contain registers location and length
- bits: contain the bits range by offset and size
= Data cells =
Are child nodes of MTK-EFUSE, bindings of which as described in
bindings/nvmem/nvmem.txt
Example:
efuse: efuse@10206000 {
compatible = "mediatek,mt8173-efuse";
reg = <0 0x10206000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
/* Data cells */
thermal_calibration: calib@528 {
reg = <0x528 0xc>;
};
};
= Data consumers =
Are device nodes which consume nvmem data cells.
For example:
thermal {
...
nvmem-cells = <&thermal_calibration>;
nvmem-cell-names = "calibration";
};

35
Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml Normal file
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@ -0,0 +1,35 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic G12A MIPI analog PHY
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
properties:
compatible:
const: amlogic,g12a-mipi-dphy-analog
"#phy-cells":
const: 0
reg:
maxItems: 1
required:
- compatible
- reg
- "#phy-cells"
additionalProperties: false
examples:
- |
phy@0 {
compatible = "amlogic,g12a-mipi-dphy-analog";
reg = <0x0 0xc>;
#phy-cells = <0>;
};

5
Documentation/devicetree/bindings/phy/cdns,dphy.yaml
View File

@ -11,8 +11,9 @@ maintainers:
properties:
compatible:
items:
- const: cdns,dphy
enum:
- cdns,dphy
- ti,j721e-dphy
reg:
maxItems: 1

61
Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml Normal file
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@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mixel LVDS PHY for Freescale i.MX8qm SoC
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
It converts two groups of four 7/10 bits of CMOS data into two
groups of four data lanes of LVDS data streams. A phase-locked
transmit clock is transmitted in parallel with each group of
data streams over a fifth LVDS link. Every cycle of the transmit
clock, 56/80 bits of input data are sampled and transmitted
through the two groups of LVDS data streams. Together with the
transmit clocks, the two groups of LVDS data streams form two
LVDS channels.
The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
by Control and Status Registers(CSR) module in the SoC. The CSR
module, as a system controller, contains the PHY's registers.
properties:
compatible:
enum:
- fsl,imx8qm-lvds-phy
- mixel,28fdsoi-lvds-1250-8ch-tx-pll
"#phy-cells":
const: 1
description: |
Cell allows setting the LVDS channel index of the PHY.
Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
clocks:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- "#phy-cells"
- clocks
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/firmware/imx/rsrc.h>
phy {
compatible = "fsl,imx8qm-lvds-phy";
#phy-cells = <1>;
clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
power-domains = <&pd IMX_SC_R_LVDS_0>;
};

4
Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
View File

@ -24,6 +24,10 @@ properties:
- enum:
- mediatek,mt7623-mipi-tx
- const: mediatek,mt2701-mipi-tx
- items:
- enum:
- mediatek,mt8365-mipi-tx
- const: mediatek,mt8183-mipi-tx
- const: mediatek,mt2701-mipi-tx
- const: mediatek,mt8173-mipi-tx
- const: mediatek,mt8183-mipi-tx

75
Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml Normal file
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@ -0,0 +1,75 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek PCIe PHY
maintainers:
- Jianjun Wang <jianjun.wang@mediatek.com>
description: |
The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
properties:
compatible:
const: mediatek,mt8195-pcie-phy
reg:
maxItems: 1
reg-names:
items:
- const: sif
"#phy-cells":
const: 0
nvmem-cells:
maxItems: 7
description:
Phandles to nvmem cell that contains the efuse data, if unspecified,
default value is used.
nvmem-cell-names:
items:
- const: glb_intr
- const: tx_ln0_pmos
- const: tx_ln0_nmos
- const: rx_ln0
- const: tx_ln1_pmos
- const: tx_ln1_nmos
- const: rx_ln1
power-domains:
maxItems: 1
required:
- compatible
- reg
- reg-names
- "#phy-cells"
additionalProperties: false
examples:
- |
phy@11e80000 {
compatible = "mediatek,mt8195-pcie-phy";
#phy-cells = <0>;
reg = <0x11e80000 0x10000>;
reg-names = "sif";
nvmem-cells = <&pciephy_glb_intr>,
<&pciephy_tx_ln0_pmos>,
<&pciephy_tx_ln0_nmos>,
<&pciephy_rx_ln0>,
<&pciephy_tx_ln1_pmos>,
<&pciephy_tx_ln1_nmos>,
<&pciephy_rx_ln1>;
nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
"tx_ln0_nmos", "rx_ln0",
"tx_ln1_pmos", "tx_ln1_nmos",
"rx_ln1";
power-domains = <&spm 2>;
};

2
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
View File

@ -82,9 +82,11 @@ properties:
- mediatek,mt8183-tphy
- mediatek,mt8186-tphy
- mediatek,mt8192-tphy
- mediatek,mt8365-tphy
- const: mediatek,generic-tphy-v2
- items:
- enum:
- mediatek,mt8188-tphy
- mediatek,mt8195-tphy
- const: mediatek,generic-tphy-v3
- const: mediatek,mt2701-u3phy

1
Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
View File

@ -8,6 +8,7 @@ Required properties:
* "fsl,vf610-usbphy" for Vybrid vf610
* "fsl,imx6sx-usbphy" for imx6sx
* "fsl,imx7ulp-usbphy" for imx7ulp
* "fsl,imx8dxl-usbphy" for imx8dxl
"fsl,imx23-usbphy" is still a fallback for other strings
- reg: Should contain registers location and length
- interrupts: Should contain phy interrupt

17
Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
View File

@ -4,7 +4,7 @@
$id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: NVIDIA Tegra194 P2U binding
title: NVIDIA Tegra194 & Tegra234 P2U binding
maintainers:
- Thierry Reding <treding@nvidia.com>
@ -12,13 +12,17 @@ maintainers:
description: >
Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
Speed) each interfacing with 12 and 8 P2U instances respectively.
Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet)
each interfacing with 8, 8 and 8 P2U instances respectively.
A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
lane.
interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
PCIe lane.
properties:
compatible:
const: nvidia,tegra194-p2u
enum:
- nvidia,tegra194-p2u
- nvidia,tegra234-p2u
reg:
maxItems: 1
@ -28,6 +32,11 @@ properties:
items:
- const: ctl
nvidia,skip-sz-protect-en:
description: Should be present if two PCIe retimers are present between
the root port and its immediate downstream device.
type: boolean
'#phy-cells':
const: 0

6
Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
View File

@ -41,6 +41,9 @@ properties:
"#phy-cells":
const: 0
vdda-phy-supply: true
vdda-pll-supply: true
required:
- compatible
- reg
@ -65,5 +68,8 @@ examples:
#clock-cells = <1>;
#phy-cells = <0>;
vdda-phy-supply = <&vdd_a_edp_0_1p2>;
vdda-pll-supply = <&vdd_a_edp_0_0p9>;
};
...

2
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
View File

@ -19,6 +19,7 @@ properties:
enum:
- qcom,ipq6018-qmp-pcie-phy
- qcom,ipq6018-qmp-usb3-phy
- qcom,ipq8074-qmp-gen3-pcie-phy
- qcom,ipq8074-qmp-pcie-phy
- qcom,ipq8074-qmp-usb3-phy
- qcom,msm8996-qmp-pcie-phy
@ -312,6 +313,7 @@ allOf:
contains:
enum:
- qcom,ipq6018-qmp-pcie-phy
- qcom,ipq8074-qmp-gen3-pcie-phy
- qcom,ipq8074-qmp-pcie-phy
then:
properties:

2
Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml
View File

@ -34,7 +34,7 @@ properties:
# must not be 0.
minItems: 2
items:
- const: usb3-if # The funcional clock
- const: usb3-if # The functional clock
- const: usb3s_clk # The usb3's external clock
- const: usb_extal # The usb2's external clock

15
Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
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@ -17,6 +17,7 @@ properties:
enum:
- samsung,exynos7-ufs-phy
- samsung,exynosautov9-ufs-phy
- tesla,fsd-ufs-phy
reg:
maxItems: 1
@ -40,9 +41,17 @@ properties:
- const: tx0_symbol_clk
samsung,pmu-syscon:
$ref: '/schemas/types.yaml#/definitions/phandle'
description: phandle for PMU system controller interface, used to
control pmu registers bits for ufs m-phy
$ref: '/schemas/types.yaml#/definitions/phandle-array'
maxItems: 1
items:
minItems: 1
items:
- description: phandle for PMU system controller interface, used to
control pmu registers bits for ufs m-phy
- description: offset of the pmu control register
description:
It can be phandle/offset pair. The second cell which can represent an
offset is optional.
required:
- "#phy-cells"

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -799,6 +799,8 @@ patternProperties:
description: MiraMEMS Sensing Technology Co., Ltd.
"^mitsubishi,.*":
description: Mitsubishi Electric Corporation
"^mixel,.*":
description: Mixel, Inc.
"^miyoo,.*":
description: Miyoo
"^mntre,.*":

25
Documentation/driver-api/fpga/fpga-mgr.rst
View File

@ -79,12 +79,27 @@ do the programming sequence for this particular FPGA. These ops return 0 for
success or negative error codes otherwise.
The programming sequence is::
1. .write_init
2. .write or .write_sg (may be called once or multiple times)
3. .write_complete
1. .parse_header (optional, may be called once or multiple times)
2. .write_init
3. .write or .write_sg (may be called once or multiple times)
4. .write_complete
The .write_init function will prepare the FPGA to receive the image data. The
buffer passed into .write_init will be at most .initial_header_size bytes long;
The .parse_header function will set header_size and data_size to
struct fpga_image_info. Before parse_header call, header_size is initialized
with initial_header_size. If flag skip_header of fpga_manager_ops is true,
.write function will get image buffer starting at header_size offset from the
beginning. If data_size is set, .write function will get data_size bytes of
the image buffer, otherwise .write will get data up to the end of image buffer.
This will not affect .write_sg, .write_sg will still get whole image in
sg_table form. If FPGA image is already mapped as a single contiguous buffer,
whole buffer will be passed into .parse_header. If image is in scatter-gather
form, core code will buffer up at least .initial_header_size before the first
call of .parse_header, if it is not enough, .parse_header should set desired
size into info->header_size and return -EAGAIN, then it will be called again
with greater part of image buffer on the input.
The .write_init function will prepare the FPGA to receive the image data. The
buffer passed into .write_init will be at least info->header_size bytes long;
if the whole bitstream is not immediately available then the core code will
buffer up at least this much before starting.

17
Documentation/trace/coresight/coresight-etm4x-reference.rst
View File

@ -650,13 +650,26 @@ Bit assignments shown below:-
parameter is set this value is applied to the currently indexed
address range.
.. _coresight-branch-broadcast:
**bit (4):**
ETM_MODE_BB
**description:**
Set to enable branch broadcast if supported in hardware [IDR0].
Set to enable branch broadcast if supported in hardware [IDR0]. The primary use for this feature
is when code is patched dynamically at run time and the full program flow may not be able to be
reconstructed using only conditional branches.
There is currently no support in Perf for supplying modified binaries to the decoder, so this
feature is only inteded to be used for debugging purposes or with a 3rd party tool.
Choosing this option will result in a significant increase in the amount of trace generated -
possible danger of overflows, or fewer instructions covered. Note, that this option also
overrides any setting of :ref:`ETM_MODE_RETURNSTACK <coresight-return-stack>`, so where a branch
broadcast range overlaps a return stack range, return stacks will not be available for that
range.
.. _coresight-cycle-accurate:
**bit (5):**
ETMv4_MODE_CYCACC
@ -678,6 +691,7 @@ Bit assignments shown below:-
**description:**
Set to enable virtual machine ID tracing if supported [IDR2].
.. _coresight-timestamp:
**bit (11):**
ETMv4_MODE_TIMESTAMP
@ -685,6 +699,7 @@ Bit assignments shown below:-
**description:**
Set to enable timestamp generation if supported [IDR0].
.. _coresight-return-stack:
**bit (12):**
ETM_MODE_RETURNSTACK

58
Documentation/trace/coresight/coresight.rst
View File

@ -130,7 +130,7 @@ Misc:
Device Tree Bindings
--------------------
See Documentation/devicetree/bindings/arm/coresight.txt for details.
See Documentation/devicetree/bindings/arm/arm,coresight-\*.yaml for details.
As of this writing drivers for ITM, STMs and CTIs are not provided but are
expected to be added as the solution matures.
@ -339,7 +339,8 @@ Preference is given to the former as using the sysFS interface
requires a deep understanding of the Coresight HW. The following sections
provide details on using both methods.
1) Using the sysFS interface:
Using the sysFS interface
~~~~~~~~~~~~~~~~~~~~~~~~~
Before trace collection can start, a coresight sink needs to be identified.
There is no limit on the amount of sinks (nor sources) that can be enabled at
@ -446,7 +447,8 @@ wealth of possibilities that coresight provides.
Instruction 0 0x8026B588 E8BD8000 true LDM sp!,{pc}
Timestamp Timestamp: 17107041535
2) Using perf framework:
Using perf framework
~~~~~~~~~~~~~~~~~~~~
Coresight tracers are represented using the Perf framework's Performance
Monitoring Unit (PMU) abstraction. As such the perf framework takes charge of
@ -495,7 +497,11 @@ More information on the above and other example on how to use Coresight with
the perf tools can be found in the "HOWTO.md" file of the openCSD gitHub
repository [#third]_.
2.1) AutoFDO analysis using the perf tools:
Advanced perf framework usage
-----------------------------
AutoFDO analysis using the perf tools
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
perf can be used to record and analyze trace of programs.
@ -513,7 +519,8 @@ The --itrace option controls the type and frequency of synthesized events
Note that only 64-bit programs are currently supported - further work is
required to support instruction decode of 32-bit Arm programs.
2.2) Tracing PID
Tracing PID
~~~~~~~~~~~
The kernel can be built to write the PID value into the PE ContextID registers.
For a kernel running at EL1, the PID is stored in CONTEXTIDR_EL1. A PE may
@ -547,7 +554,7 @@ wants to trace PIDs for both host and guest, the two configs "contextid1" and
Generating coverage files for Feedback Directed Optimization: AutoFDO
---------------------------------------------------------------------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
'perf inject' accepts the --itrace option in which case tracing data is
removed and replaced with the synthesized events. e.g.
@ -578,6 +585,45 @@ sort example is from the AutoFDO tutorial (https://gcc.gnu.org/wiki/AutoFDO/Tuto
Bubble sorting array of 30000 elements
5806 ms
Config option formats
~~~~~~~~~~~~~~~~~~~~~
The following strings can be provided between // on the perf command line to enable various options.
They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/
.. list-table::
:header-rows: 1
* - Option
- Description
* - branch_broadcast
- Session local version of the system wide setting:
:ref:`ETM_MODE_BB <coresight-branch-broadcast>`
* - contextid
- See `Tracing PID`_
* - contextid1
- See `Tracing PID`_
* - contextid2
- See `Tracing PID`_
* - configid
- Selection for a custom configuration. This is an implementation detail and not used directly,
see :ref:`trace/coresight/coresight-config:Using Configurations in perf`
* - preset
- Override for parameters in a custom configuration, see
:ref:`trace/coresight/coresight-config:Using Configurations in perf`
* - sinkid
- Hashed version of the string to select a sink, automatically set when using the @ notation.
This is an internal implementation detail and is not used directly, see `Using perf
framework`_.
* - cycacc
- Session local version of the system wide setting: :ref:`ETMv4_MODE_CYCACC
<coresight-cycle-accurate>`
* - retstack
- Session local version of the system wide setting: :ref:`ETM_MODE_RETURNSTACK
<coresight-return-stack>`
* - timestamp
- Session local version of the system wide setting: :ref:`ETMv4_MODE_TIMESTAMP
<coresight-timestamp>`
How to use the STM module
-------------------------

66
MAINTAINERS
View File

@ -284,38 +284,37 @@ S: Maintained
F: drivers/hwmon/abituguru3.c
ACCES 104-DIO-48E GPIO DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
M: William Breathitt Gray <william.gray@linaro.org>
L: linux-gpio@vger.kernel.org
S: Maintained
F: drivers/gpio/gpio-104-dio-48e.c
ACCES 104-IDI-48 GPIO DRIVER
M: "William Breathitt Gray" <vilhelm.gray@gmail.com>
M: William Breathitt Gray <william.gray@linaro.org>
L: linux-gpio@vger.kernel.org
S: Maintained
F: drivers/gpio/gpio-104-idi-48.c
ACCES 104-IDIO-16 GPIO DRIVER
M: "William Breathitt Gray" <vilhelm.gray@gmail.com>
M: William Breathitt Gray <william.gray@linaro.org>
L: linux-gpio@vger.kernel.org
S: Maintained
F: drivers/gpio/gpio-104-idio-16.c
ACCES 104-QUAD-8 DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
M: Syed Nayyar Waris <syednwaris@gmail.com>
M: William Breathitt Gray <william.gray@linaro.org>
L: linux-iio@vger.kernel.org
S: Maintained
F: drivers/counter/104-quad-8.c
ACCES PCI-IDIO-16 GPIO DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
M: William Breathitt Gray <william.gray@linaro.org>
L: linux-gpio@vger.kernel.org
S: Maintained
F: drivers/gpio/gpio-pci-idio-16.c
ACCES PCIe-IDIO-24 GPIO DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
M: William Breathitt Gray <william.gray@linaro.org>
L: linux-gpio@vger.kernel.org
S: Maintained
F: drivers/gpio/gpio-pcie-idio-24.c
@ -1340,7 +1339,7 @@ M: Todd Kjos <tkjos@android.com>
M: Martijn Coenen <maco@android.com>
M: Joel Fernandes <joel@joelfernandes.org>
M: Christian Brauner <christian@brauner.io>
M: Hridya Valsaraju <hridya@google.com>
M: Carlos Llamas <cmllamas@google.com>
M: Suren Baghdasaryan <surenb@google.com>
L: linux-kernel@vger.kernel.org
S: Supported
@ -1367,7 +1366,7 @@ S: Maintained
F: sound/aoa/
APEX EMBEDDED SYSTEMS STX104 IIO DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
M: William Breathitt Gray <william.gray@linaro.org>
L: linux-iio@vger.kernel.org
S: Maintained
F: drivers/iio/adc/stx104.c
@ -2002,11 +2001,9 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
F: Documentation/devicetree/bindings/arm/coresight-cti.yaml
F: Documentation/devicetree/bindings/arm/coresight.txt
F: Documentation/devicetree/bindings/arm/ete.yaml
F: Documentation/devicetree/bindings/arm/trbe.yaml
F: Documentation/devicetree/bindings/arm/arm,coresight-*.yaml
F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml
F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
F: Documentation/trace/coresight/*
F: drivers/hwtracing/coresight/*
F: include/dt-bindings/arm/coresight-cti-dt.h
@ -5256,10 +5253,10 @@ F: Documentation/hwmon/corsair-psu.rst
F: drivers/hwmon/corsair-psu.c
COUNTER SUBSYSTEM
M: William Breathitt Gray <vilhelm.gray@gmail.com>
M: William Breathitt Gray <william.gray@linaro.org>
L: linux-iio@vger.kernel.org
S: Maintained
T: git git@gitlab.com:vilhelmgray/counter.git
T: git https://git.linaro.org/people/william.gray/counter.git
F: Documentation/ABI/testing/sysfs-bus-counter
F: Documentation/driver-api/generic-counter.rst
F: drivers/counter/
@ -6019,7 +6016,7 @@ F: include/sound/da[79]*.h
F: sound/soc/codecs/da[79]*.[ch]
DIAMOND SYSTEMS GPIO-MM GPIO DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
M: William Breathitt Gray <william.gray@linaro.org>
L: linux-gpio@vger.kernel.org
S: Maintained
F: drivers/gpio/gpio-gpio-mm.c
@ -6881,6 +6878,7 @@ L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Supported
F: Documentation/devicetree/bindings/display/mediatek/
F: drivers/gpu/drm/mediatek/
F: drivers/phy/mediatek/phy-mtk-dp.c
F: drivers/phy/mediatek/phy-mtk-hdmi*
F: drivers/phy/mediatek/phy-mtk-mipi*
@ -8006,6 +8004,21 @@ F: Documentation/fpga/
F: drivers/fpga/
F: include/linux/fpga/
INTEL MAX10 BMC SECURE UPDATES
M: Russ Weight <russell.h.weight@intel.com>
L: linux-fpga@vger.kernel.org
S: Maintained
F: Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
F: drivers/fpga/intel-m10-bmc-sec-update.c
MICROCHIP POLARFIRE FPGA DRIVERS
M: Conor Dooley <conor.dooley@microchip.com>
R: Ivan Bornyakov <i.bornyakov@metrotek.ru>
L: linux-fpga@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
F: drivers/fpga/microchip-spi.c
FPU EMULATOR
M: Bill Metzenthen <billm@melbpc.org.au>
S: Maintained
@ -8508,6 +8521,7 @@ Q: https://patchwork.kernel.org/project/linux-phy/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git
F: Documentation/devicetree/bindings/phy/
F: drivers/phy/
F: include/dt-bindings/phy/
F: include/linux/phy/
GENERIC PINCTRL I2C DEMULTIPLEXER DRIVER
@ -9829,6 +9843,7 @@ F: Documentation/ABI/testing/sysfs-bus-iio*
F: Documentation/devicetree/bindings/iio/
F: drivers/iio/
F: drivers/staging/iio/
F: include/dt-bindings/iio/
F: include/linux/iio/
F: tools/iio/
@ -10664,7 +10679,7 @@ F: Documentation/devicetree/bindings/interrupt-controller/
F: drivers/irqchip/
ISA
M: William Breathitt Gray <vilhelm.gray@gmail.com>
M: William Breathitt Gray <william.gray@linaro.org>
S: Maintained
F: Documentation/driver-api/isa.rst
F: drivers/base/isa.c
@ -12440,7 +12455,7 @@ F: drivers/net/ieee802154/mcr20a.c
F: drivers/net/ieee802154/mcr20a.h
MEASUREMENT COMPUTING CIO-DAC IIO DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
M: William Breathitt Gray <william.gray@linaro.org>
L: linux-iio@vger.kernel.org
S: Maintained
F: drivers/iio/dac/cio-dac.c
@ -13359,6 +13374,14 @@ S: Supported
F: Documentation/devicetree/bindings/mtd/atmel-nand.txt
F: drivers/mtd/nand/raw/atmel/*
MICROCHIP OTPC DRIVER
M: Claudiu Beznea <claudiu.beznea@microchip.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
F: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
F: drivers/nvmem/microchip-otpc.c
F: include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
MICROCHIP PWM DRIVER
M: Claudiu Beznea <claudiu.beznea@microchip.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -21361,6 +21384,7 @@ M: Jason Wang <jasowang@redhat.com>
L: virtualization@lists.linux-foundation.org
S: Maintained
F: Documentation/ABI/testing/sysfs-bus-vdpa
F: Documentation/ABI/testing/sysfs-class-vduse
F: Documentation/devicetree/bindings/virtio/
F: drivers/block/virtio_blk.c
F: drivers/crypto/virtio/
@ -21779,13 +21803,13 @@ S: Maintained
F: drivers/media/rc/winbond-cir.c
WINSYSTEMS EBC-C384 WATCHDOG DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
M: William Breathitt Gray <william.gray@linaro.org>
L: linux-watchdog@vger.kernel.org
S: Maintained
F: drivers/watchdog/ebc-c384_wdt.c
WINSYSTEMS WS16C48 GPIO DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
M: William Breathitt Gray <william.gray@linaro.org>
L: linux-gpio@vger.kernel.org
S: Maintained
F: drivers/gpio/gpio-ws16c48.c

2
drivers/Makefile
View File

@ -176,7 +176,7 @@ obj-$(CONFIG_USB4) += thunderbolt/
obj-$(CONFIG_CORESIGHT) += hwtracing/coresight/
obj-y += hwtracing/intel_th/
obj-$(CONFIG_STM) += hwtracing/stm/
obj-$(CONFIG_ANDROID) += android/
obj-y += android/
obj-$(CONFIG_NVMEM) += nvmem/
obj-$(CONFIG_FPGA) += fpga/
obj-$(CONFIG_FSI) += fsi/

4
drivers/accessibility/speakup/.gitignore vendored Normal file
View File

@ -0,0 +1,4 @@
/makemapdata
/mapdata.h
/genmap
/speakupmap.h

28
drivers/accessibility/speakup/Makefile
View File

@ -30,3 +30,31 @@ speakup-y := \
thread.o \
varhandlers.o
speakup-$(CONFIG_SPEAKUP_SERIALIO) += serialio.o
clean-files := mapdata.h speakupmap.h
# Generate mapdata.h from headers
hostprogs += makemapdata
makemapdata-objs := makemapdata.o
quiet_cmd_mkmap = MKMAP $@
cmd_mkmap = TOPDIR=$(srctree) $(obj)/makemapdata > $@
$(obj)/mapdata.h: $(obj)/makemapdata
$(call cmd,mkmap)
# Generate speakupmap.h from mapdata.h
hostprogs += genmap
genmap-objs := genmap.o
$(obj)/genmap.o: $(obj)/mapdata.h
quiet_cmd_genmap = GENMAP $@
cmd_genmap = $(obj)/genmap $< > $@
$(obj)/speakupmap.h: $(src)/speakupmap.map $(obj)/genmap
$(call cmd,genmap)
$(obj)/main.o: $(obj)/speakupmap.h

162
drivers/accessibility/speakup/genmap.c Normal file
View File

@ -0,0 +1,162 @@
// SPDX-License-Identifier: GPL-2.0+
/* genmap.c
* originally written by: Kirk Reiser.
*
** Copyright (C) 2002 Kirk Reiser.
* Copyright (C) 2003 David Borowski.
*/
#include <stdlib.h>
#include <stdio.h>
#include <libgen.h>
#include <string.h>
#include <linux/version.h>
#include <ctype.h>
#include "utils.h"
struct st_key_init {
char *name;
int value, shift;
};
static unsigned char key_data[MAXKEYVAL][16], *kp;
#include "mapdata.h"
static const char delims[] = "\t\n ";
static char *cp;
static int map_ver = 119; /* an arbitrary number so speakup can check */
static int shift_table[17];
static int max_states = 1, flags;
/* flags reserved for later, maybe for individual console maps */
static int get_shift_value(int state)
{
int i;
for (i = 0; shift_table[i] != state; i++) {
if (shift_table[i] == -1) {
if (i >= 16)
oops("too many shift states", NULL);
shift_table[i] = state;
max_states = i+1;
break;
}
}
return i;
}
int
main(int argc, char *argv[])
{
int value, shift_state, i, spk_val = 0, lock_val = 0;
int max_key_used = 0, num_keys_used = 0;
struct st_key *this;
struct st_key_init *p_init;
char buffer[256];
bzero(key_table, sizeof(key_table));
bzero(key_data, sizeof(key_data));
shift_table[0] = 0;
for (i = 1; i <= 16; i++)
shift_table[i] = -1;
if (argc < 2) {
fputs("usage: genmap filename\n", stderr);
exit(1);
}
for (p_init = init_key_data; p_init->name[0] != '.'; p_init++)
add_key(p_init->name, p_init->value, p_init->shift);
open_input(NULL, argv[1]);
while (fgets(buffer, sizeof(buffer), infile)) {
lc++;
value = shift_state = 0;
cp = strtok(buffer, delims);
if (*cp == '#')
continue;
while (cp) {
if (*cp == '=')
break;
this = find_key(cp);
if (this == NULL)
oops("unknown key/modifier", cp);
if (this->shift == is_shift) {
if (value)
oops("modifiers must come first", cp);
shift_state += this->value;
} else if (this->shift == is_input)
value = this->value;
else
oops("bad modifier or key", cp);
cp = strtok(0, delims);
}
if (!cp)
oops("no = found", NULL);
cp = strtok(0, delims);
if (!cp)
oops("no speakup function after =", NULL);
this = find_key(cp);
if (this == NULL || this->shift != is_spk)
oops("invalid speakup function", cp);
i = get_shift_value(shift_state);
if (key_data[value][i]) {
while (--cp > buffer)
if (!*cp)
*cp = ' ';
oops("two functions on same key combination", cp);
}
key_data[value][i] = (char)this->value;
if (value > max_key_used)
max_key_used = value;
}
fclose(infile);
this = find_key("spk_key");
if (this)
spk_val = this->value;
this = find_key("spk_lock");
if (this)
lock_val = this->value;
for (lc = 1; lc <= max_key_used; lc++) {
kp = key_data[lc];
if (!memcmp(key_data[0], kp, 16))
continue;
num_keys_used++;
for (i = 0; i < max_states; i++) {
if (kp[i] != spk_val && kp[i] != lock_val)
continue;
shift_state = shift_table[i];
if (shift_state&16)
continue;
shift_state = get_shift_value(shift_state+16);
kp[shift_state] = kp[i];
/* fill in so we can process the key up, as spk bit will be set */
}
}
printf("\t%d, %d, %d,\n\t", map_ver, num_keys_used, max_states);
for (i = 0; i < max_states; i++)
printf("%d, ", shift_table[i]);
printf("%d,", flags);
for (lc = 1; lc <= max_key_used; lc++) {
kp = key_data[lc];
if (!memcmp(key_data[0], kp, 16))
continue;
printf("\n\t%d,", lc);
for (i = 0; i < max_states; i++)
printf(" %d,", (unsigned int)kp[i]);
}
printf("\n\t0, %d\n", map_ver);
exit(0);
}

125
drivers/accessibility/speakup/makemapdata.c Normal file
View File

@ -0,0 +1,125 @@
// SPDX-License-Identifier: GPL-2.0+
/* makemapdata.c
* originally written by: Kirk Reiser.
*
** Copyright (C) 2002 Kirk Reiser.
* Copyright (C) 2003 David Borowski.
*/
#include <stdlib.h>
#include <stdio.h>
#include <libgen.h>
#include <string.h>
#include <linux/version.h>
#include <ctype.h>
#include "utils.h"
static char buffer[256];
static int get_define(void)
{
char *c;
while (fgets(buffer, sizeof(buffer)-1, infile)) {
lc++;
if (strncmp(buffer, "#define", 7))
continue;
c = buffer + 7;
while (*c == ' ' || *c == '\t')
c++;
def_name = c;
while (*c && *c != ' ' && *c != '\t' && *c != '\n')
c++;
if (!*c || *c == '\n')
continue;
*c++ = '\0';
while (*c == ' ' || *c == '\t' || *c == '(')
c++;
def_val = c;
while (*c && *c != '\n' && *c != ')')
c++;
*c++ = '\0';
return 1;
}
fclose(infile);
infile = 0;
return 0;
}
int
main(int argc, char *argv[])
{
int value, i;
struct st_key *this;
const char *dir_name;
char *cp;
dir_name = getenv("TOPDIR");
if (!dir_name)
dir_name = ".";
bzero(key_table, sizeof(key_table));
add_key("shift", 1, is_shift);
add_key("altgr", 2, is_shift);
add_key("ctrl", 4, is_shift);
add_key("alt", 8, is_shift);
add_key("spk", 16, is_shift);
add_key("double", 32, is_shift);
open_input(dir_name, "include/linux/input.h");
while (get_define()) {
if (strncmp(def_name, "KEY_", 4))
continue;
value = atoi(def_val);
if (value > 0 && value < MAXKEYVAL)
add_key(def_name, value, is_input);
}
open_input(dir_name, "include/uapi/linux/input-event-codes.h");
while (get_define()) {
if (strncmp(def_name, "KEY_", 4))
continue;
value = atoi(def_val);
if (value > 0 && value < MAXKEYVAL)
add_key(def_name, value, is_input);
}
open_input(dir_name, "drivers/accessibility/speakup/spk_priv_keyinfo.h");
while (get_define()) {
if (strlen(def_val) > 5) {
//if (def_val[0] == '(')
// def_val++;
cp = strchr(def_val, '+');
if (!cp)
continue;
if (cp[-1] == ' ')
cp[-1] = '\0';
*cp++ = '\0';
this = find_key(def_val);
while (*cp == ' ')
cp++;
if (!this || *cp < '0' || *cp > '9')
continue;
value = this->value+atoi(cp);
} else if (!strncmp(def_val, "0x", 2))
sscanf(def_val+2, "%x", &value);
else if (*def_val >= '0' && *def_val <= '9')
value = atoi(def_val);
else
continue;
add_key(def_name, value, is_spk);
}
printf("struct st_key_init init_key_data[] = {\n");
for (i = 0; i < HASHSIZE; i++) {
this = &key_table[i];
if (!this->name)
continue;
do {
printf("\t{ \"%s\", %d, %d, },\n", this->name, this->value, this->shift);
this = this->next;
} while (this);
}
printf("\t{ \".\", 0, 0 }\n};\n");
exit(0);
}

66
drivers/accessibility/speakup/speakupmap.h
View File

@ -1,66 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
119, 62, 6,
0, 16, 20, 17, 32, 48, 0,
2, 0, 78, 0, 0, 0, 0,
3, 0, 79, 0, 0, 0, 0,
4, 0, 76, 0, 0, 0, 0,
5, 0, 77, 0, 0, 0, 0,
6, 0, 74, 0, 0, 0, 0,
7, 0, 75, 0, 0, 0, 0,
9, 0, 5, 46, 0, 0, 0,
10, 0, 4, 0, 0, 0, 0,
11, 0, 0, 1, 0, 0, 0,
12, 0, 27, 0, 33, 0, 0,
19, 0, 47, 0, 0, 0, 0,
21, 0, 29, 17, 0, 0, 0,
22, 0, 15, 0, 0, 0, 0,
23, 0, 14, 0, 0, 0, 28,
24, 0, 16, 0, 0, 0, 0,
25, 0, 30, 18, 0, 0, 0,
28, 0, 3, 26, 0, 0, 0,
35, 0, 31, 0, 0, 0, 0,
36, 0, 12, 0, 0, 0, 0,
37, 0, 11, 0, 0, 0, 22,
38, 0, 13, 0, 0, 0, 0,
39, 0, 32, 7, 0, 0, 0,
40, 0, 23, 0, 0, 0, 0,
44, 0, 44, 0, 0, 0, 0,
49, 0, 24, 0, 0, 0, 0,
50, 0, 9, 19, 6, 0, 0,
51, 0, 8, 0, 0, 0, 36,
52, 0, 10, 20, 0, 0, 0,
53, 0, 25, 0, 0, 0, 0,
55, 46, 1, 0, 0, 0, 0,
58, 128, 128, 0, 0, 0, 0,
59, 0, 45, 0, 0, 0, 0,
60, 0, 40, 0, 0, 0, 0,
61, 0, 41, 0, 0, 0, 0,
62, 0, 42, 0, 0, 0, 0,
63, 0, 34, 0, 0, 0, 0,
64, 0, 35, 0, 0, 0, 0,
65, 0, 37, 0, 0, 0, 0,
66, 0, 38, 0, 0, 0, 0,
67, 0, 66, 0, 39, 0, 0,
68, 0, 67, 0, 0, 0, 0,
71, 15, 19, 0, 0, 0, 0,
72, 14, 29, 0, 0, 28, 0,
73, 16, 17, 0, 0, 0, 0,
74, 27, 33, 0, 0, 0, 0,
75, 12, 31, 0, 0, 0, 0,
76, 11, 21, 0, 0, 22, 0,
77, 13, 32, 0, 0, 0, 0,
78, 23, 43, 0, 0, 0, 0,
79, 9, 20, 0, 0, 0, 0,
80, 8, 30, 0, 0, 36, 0,
81, 10, 18, 0, 0, 0, 0,
82, 128, 128, 0, 0, 0, 0,
83, 24, 25, 0, 0, 0, 0,
87, 0, 68, 0, 0, 0, 0,
88, 0, 69, 0, 0, 0, 0,
96, 3, 26, 0, 0, 0, 0,
98, 4, 5, 0, 0, 0, 0,
99, 2, 0, 0, 0, 0, 0,
104, 0, 6, 0, 0, 0, 0,
109, 0, 7, 0, 0, 0, 0,
125, 128, 128, 0, 0, 0, 0,
0, 119

102
drivers/accessibility/speakup/utils.h Normal file
View File

@ -0,0 +1,102 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* utils.h
* originally written by: Kirk Reiser.
*
** Copyright (C) 2002 Kirk Reiser.
* Copyright (C) 2003 David Borowski.
*/
#include <stdio.h>
#define MAXKEYS 512
#define MAXKEYVAL 160
#define HASHSIZE 101
#define is_shift -3
#define is_spk -2
#define is_input -1
struct st_key {
char *name;
struct st_key *next;
int value, shift;
};
struct st_key key_table[MAXKEYS];
struct st_key *extra_keys = key_table+HASHSIZE;
char *def_name, *def_val;
FILE *infile;
int lc;
char filename[256];
static inline void open_input(const char *dir_name, const char *name)
{
if (dir_name)
snprintf(filename, sizeof(filename), "%s/%s", dir_name, name);
else
snprintf(filename, sizeof(filename), "%s", name);
infile = fopen(filename, "r");
if (infile == 0) {
fprintf(stderr, "can't open %s\n", filename);
exit(1);
}
lc = 0;
}
static inline int oops(const char *msg, const char *info)
{
if (info == NULL)
info = "";
fprintf(stderr, "error: file %s line %d\n", filename, lc);
fprintf(stderr, "%s %s\n", msg, info);
exit(1);
}
static inline struct st_key *hash_name(char *name)
{
u_char *pn = (u_char *)name;
int hash = 0;
while (*pn) {
hash = (hash * 17) & 0xfffffff;
if (isupper(*pn))
*pn = tolower(*pn);
hash += (int)*pn;
pn++;
}
hash %= HASHSIZE;
return &key_table[hash];
}
static inline struct st_key *find_key(char *name)
{
struct st_key *this = hash_name(name);
while (this) {
if (this->name && !strcmp(name, this->name))
return this;
this = this->next;
}
return this;
}
static inline struct st_key *add_key(char *name, int value, int shift)
{
struct st_key *this = hash_name(name);
if (extra_keys-key_table >= MAXKEYS)
oops("out of key table space, enlarge MAXKEYS", NULL);
if (this->name != NULL) {
while (this->next) {
if (!strcmp(name, this->name))
oops("attempt to add duplicate key", name);
this = this->next;
}
this->next = extra_keys++;
this = this->next;
}
this->name = strdup(name);
this->value = value;
this->shift = shift;
return this;
}

9
drivers/android/Kconfig
View File

@ -1,13 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
menu "Android"
config ANDROID
bool "Android Drivers"
help
Enable support for various drivers needed on the Android platform
if ANDROID
config ANDROID_BINDER_IPC
bool "Android Binder IPC Driver"
depends on MMU
@ -54,6 +47,4 @@ config ANDROID_BINDER_IPC_SELFTEST
exhaustively with combinations of various buffer sizes and
alignments.
endif # if ANDROID
endmenu

199
drivers/android/binder.c
View File

@ -197,8 +197,32 @@ static inline void binder_stats_created(enum binder_stat_types type)
atomic_inc(&binder_stats.obj_created[type]);
}
struct binder_transaction_log binder_transaction_log;
struct binder_transaction_log binder_transaction_log_failed;
struct binder_transaction_log_entry {
int debug_id;
int debug_id_done;
int call_type;
int from_proc;
int from_thread;
int target_handle;
int to_proc;
int to_thread;
int to_node;
int data_size;
int offsets_size;
int return_error_line;
uint32_t return_error;
uint32_t return_error_param;
char context_name[BINDERFS_MAX_NAME + 1];
};
struct binder_transaction_log {
atomic_t cur;
bool full;
struct binder_transaction_log_entry entry[32];
};
static struct binder_transaction_log binder_transaction_log;
static struct binder_transaction_log binder_transaction_log_failed;
static struct binder_transaction_log_entry *binder_transaction_log_add(
struct binder_transaction_log *log)
@ -2626,6 +2650,56 @@ static int binder_fixup_parent(struct list_head *pf_head,
return binder_add_fixup(pf_head, buffer_offset, bp->buffer, 0);
}
/**
* binder_can_update_transaction() - Can a txn be superseded by an updated one?
* @t1: the pending async txn in the frozen process
* @t2: the new async txn to supersede the outdated pending one
*
* Return: true if t2 can supersede t1
* false if t2 can not supersede t1
*/
static bool binder_can_update_transaction(struct binder_transaction *t1,
struct binder_transaction *t2)
{
if ((t1->flags & t2->flags & (TF_ONE_WAY | TF_UPDATE_TXN)) !=
(TF_ONE_WAY | TF_UPDATE_TXN) || !t1->to_proc || !t2->to_proc)
return false;
if (t1->to_proc->tsk == t2->to_proc->tsk && t1->code == t2->code &&
t1->flags == t2->flags && t1->buffer->pid == t2->buffer->pid &&
t1->buffer->target_node->ptr == t2->buffer->target_node->ptr &&
t1->buffer->target_node->cookie == t2->buffer->target_node->cookie)
return true;
return false;
}
/**
* binder_find_outdated_transaction_ilocked() - Find the outdated transaction
* @t: new async transaction
* @target_list: list to find outdated transaction
*
* Return: the outdated transaction if found
* NULL if no outdated transacton can be found
*
* Requires the proc->inner_lock to be held.
*/
static struct binder_transaction *
binder_find_outdated_transaction_ilocked(struct binder_transaction *t,
struct list_head *target_list)
{
struct binder_work *w;
list_for_each_entry(w, target_list, entry) {
struct binder_transaction *t_queued;
if (w->type != BINDER_WORK_TRANSACTION)
continue;
t_queued = container_of(w, struct binder_transaction, work);
if (binder_can_update_transaction(t_queued, t))
return t_queued;
}
return NULL;
}
/**
* binder_proc_transaction() - sends a transaction to a process and wakes it up
* @t: transaction to send
@ -2651,6 +2725,7 @@ static int binder_proc_transaction(struct binder_transaction *t,
struct binder_node *node = t->buffer->target_node;
bool oneway = !!(t->flags & TF_ONE_WAY);
bool pending_async = false;
struct binder_transaction *t_outdated = NULL;
BUG_ON(!node);
binder_node_lock(node);
@ -2678,12 +2753,24 @@ static int binder_proc_transaction(struct binder_transaction *t,
if (!thread && !pending_async)
thread = binder_select_thread_ilocked(proc);
if (thread)
if (thread) {
binder_enqueue_thread_work_ilocked(thread, &t->work);
else if (!pending_async)
} else if (!pending_async) {
binder_enqueue_work_ilocked(&t->work, &proc->todo);
else
} else {
if ((t->flags & TF_UPDATE_TXN) && proc->is_frozen) {
t_outdated = binder_find_outdated_transaction_ilocked(t,
&node->async_todo);
if (t_outdated) {
binder_debug(BINDER_DEBUG_TRANSACTION,
"txn %d supersedes %d\n",
t->debug_id, t_outdated->debug_id);
list_del_init(&t_outdated->work.entry);
proc->outstanding_txns--;
}
}
binder_enqueue_work_ilocked(&t->work, &node->async_todo);
}
if (!pending_async)
binder_wakeup_thread_ilocked(proc, thread, !oneway /* sync */);
@ -2692,6 +2779,22 @@ static int binder_proc_transaction(struct binder_transaction *t,
binder_inner_proc_unlock(proc);
binder_node_unlock(node);
/*
* To reduce potential contention, free the outdated transaction and
* buffer after releasing the locks.
*/
if (t_outdated) {
struct binder_buffer *buffer = t_outdated->buffer;
t_outdated->buffer = NULL;
buffer->transaction = NULL;
trace_binder_transaction_update_buffer_release(buffer);
binder_transaction_buffer_release(proc, NULL, buffer, 0, 0);
binder_alloc_free_buf(&proc->alloc, buffer);
kfree(t_outdated);
binder_stats_deleted(BINDER_STAT_TRANSACTION);
}
return 0;
}
@ -6197,8 +6300,7 @@ static void print_binder_proc_stats(struct seq_file *m,
print_binder_stats(m, " ", &proc->stats);
}
int binder_state_show(struct seq_file *m, void *unused)
static int state_show(struct seq_file *m, void *unused)
{
struct binder_proc *proc;
struct binder_node *node;
@ -6237,7 +6339,7 @@ int binder_state_show(struct seq_file *m, void *unused)
return 0;
}
int binder_stats_show(struct seq_file *m, void *unused)
static int stats_show(struct seq_file *m, void *unused)
{
struct binder_proc *proc;
@ -6253,7 +6355,7 @@ int binder_stats_show(struct seq_file *m, void *unused)
return 0;
}
int binder_transactions_show(struct seq_file *m, void *unused)
static int transactions_show(struct seq_file *m, void *unused)
{
struct binder_proc *proc;
@ -6309,7 +6411,7 @@ static void print_binder_transaction_log_entry(struct seq_file *m,
"\n" : " (incomplete)\n");
}
int binder_transaction_log_show(struct seq_file *m, void *unused)
static int transaction_log_show(struct seq_file *m, void *unused)
{
struct binder_transaction_log *log = m->private;
unsigned int log_cur = atomic_read(&log->cur);
@ -6341,6 +6443,45 @@ const struct file_operations binder_fops = {
.release = binder_release,
};
DEFINE_SHOW_ATTRIBUTE(state);
DEFINE_SHOW_ATTRIBUTE(stats);
DEFINE_SHOW_ATTRIBUTE(transactions);
DEFINE_SHOW_ATTRIBUTE(transaction_log);
const struct binder_debugfs_entry binder_debugfs_entries[] = {
{
.name = "state",
.mode = 0444,
.fops = &state_fops,
.data = NULL,
},
{
.name = "stats",
.mode = 0444,
.fops = &stats_fops,
.data = NULL,
},
{
.name = "transactions",
.mode = 0444,
.fops = &transactions_fops,
.data = NULL,
},
{
.name = "transaction_log",
.mode = 0444,
.fops = &transaction_log_fops,
.data = &binder_transaction_log,
},
{
.name = "failed_transaction_log",
.mode = 0444,
.fops = &transaction_log_fops,
.data = &binder_transaction_log_failed,
},
{} /* terminator */
};
static int __init init_binder_device(const char *name)
{
int ret;
@ -6386,36 +6527,18 @@ static int __init binder_init(void)
atomic_set(&binder_transaction_log_failed.cur, ~0U);
binder_debugfs_dir_entry_root = debugfs_create_dir("binder", NULL);
if (binder_debugfs_dir_entry_root)
if (binder_debugfs_dir_entry_root) {
const struct binder_debugfs_entry *db_entry;
binder_for_each_debugfs_entry(db_entry)
debugfs_create_file(db_entry->name,
db_entry->mode,
binder_debugfs_dir_entry_root,
db_entry->data,
db_entry->fops);
binder_debugfs_dir_entry_proc = debugfs_create_dir("proc",
binder_debugfs_dir_entry_root);
if (binder_debugfs_dir_entry_root) {
debugfs_create_file("state",
0444,
binder_debugfs_dir_entry_root,
NULL,
&binder_state_fops);
debugfs_create_file("stats",
0444,
binder_debugfs_dir_entry_root,
NULL,
&binder_stats_fops);
debugfs_create_file("transactions",
0444,
binder_debugfs_dir_entry_root,
NULL,
&binder_transactions_fops);
debugfs_create_file("transaction_log",
0444,
binder_debugfs_dir_entry_root,
&binder_transaction_log,
&binder_transaction_log_fops);
debugfs_create_file("failed_transaction_log",
0444,
binder_debugfs_dir_entry_root,
&binder_transaction_log_failed,
&binder_transaction_log_fops);
}
if (!IS_ENABLED(CONFIG_ANDROID_BINDERFS) &&

46
drivers/android/binder_internal.h
View File

@ -107,41 +107,19 @@ static inline int __init init_binderfs(void)
}
#endif
int binder_stats_show(struct seq_file *m, void *unused);
DEFINE_SHOW_ATTRIBUTE(binder_stats);
int binder_state_show(struct seq_file *m, void *unused);
DEFINE_SHOW_ATTRIBUTE(binder_state);
int binder_transactions_show(struct seq_file *m, void *unused);
DEFINE_SHOW_ATTRIBUTE(binder_transactions);
int binder_transaction_log_show(struct seq_file *m, void *unused);
DEFINE_SHOW_ATTRIBUTE(binder_transaction_log);
struct binder_transaction_log_entry {
int debug_id;
int debug_id_done;
int call_type;
int from_proc;
int from_thread;
int target_handle;
int to_proc;
int to_thread;
int to_node;
int data_size;
int offsets_size;
int return_error_line;
uint32_t return_error;
uint32_t return_error_param;
char context_name[BINDERFS_MAX_NAME + 1];
struct binder_debugfs_entry {
const char *name;
umode_t mode;
const struct file_operations *fops;
void *data;
};
struct binder_transaction_log {
atomic_t cur;
bool full;
struct binder_transaction_log_entry entry[32];
};
extern const struct binder_debugfs_entry binder_debugfs_entries[];
#define binder_for_each_debugfs_entry(entry) \
for ((entry) = binder_debugfs_entries; \
(entry)->name; \
(entry)++)
enum binder_stat_types {
BINDER_STAT_PROC,
@ -580,6 +558,4 @@ struct binder_object {
};
};
extern struct binder_transaction_log binder_transaction_log;
extern struct binder_transaction_log binder_transaction_log_failed;
#endif /* _LINUX_BINDER_INTERNAL_H */

4
drivers/android/binder_trace.h
View File

@ -311,6 +311,10 @@ DEFINE_EVENT(binder_buffer_class, binder_transaction_failed_buffer_release,
TP_PROTO(struct binder_buffer *buffer),
TP_ARGS(buffer));
DEFINE_EVENT(binder_buffer_class, binder_transaction_update_buffer_release,
TP_PROTO(struct binder_buffer *buffer),
TP_ARGS(buffer));
TRACE_EVENT(binder_update_page_range,
TP_PROTO(struct binder_alloc *alloc, bool allocate,
void __user *start, void __user *end),

47
drivers/android/binderfs.c
View File

@ -629,6 +629,7 @@ static int init_binder_features(struct super_block *sb)
static int init_binder_logs(struct super_block *sb)
{
struct dentry *binder_logs_root_dir, *dentry, *proc_log_dir;
const struct binder_debugfs_entry *db_entry;
struct binderfs_info *info;
int ret = 0;
@ -639,43 +640,15 @@ static int init_binder_logs(struct super_block *sb)
goto out;
}
dentry = binderfs_create_file(binder_logs_root_dir, "stats",
&binder_stats_fops, NULL);
if (IS_ERR(dentry)) {
ret = PTR_ERR(dentry);
goto out;
}
dentry = binderfs_create_file(binder_logs_root_dir, "state",
&binder_state_fops, NULL);
if (IS_ERR(dentry)) {
ret = PTR_ERR(dentry);
goto out;
}
dentry = binderfs_create_file(binder_logs_root_dir, "transactions",
&binder_transactions_fops, NULL);
if (IS_ERR(dentry)) {
ret = PTR_ERR(dentry);
goto out;
}
dentry = binderfs_create_file(binder_logs_root_dir,
"transaction_log",
&binder_transaction_log_fops,
&binder_transaction_log);
if (IS_ERR(dentry)) {
ret = PTR_ERR(dentry);
goto out;
}
dentry = binderfs_create_file(binder_logs_root_dir,
"failed_transaction_log",
&binder_transaction_log_fops,
&binder_transaction_log_failed);
if (IS_ERR(dentry)) {
ret = PTR_ERR(dentry);
goto out;
binder_for_each_debugfs_entry(db_entry) {
dentry = binderfs_create_file(binder_logs_root_dir,
db_entry->name,
db_entry->fops,
db_entry->data);
if (IS_ERR(dentry)) {
ret = PTR_ERR(dentry);
goto out;
}
}
proc_log_dir = binderfs_create_dir(binder_logs_root_dir, "proc");

11
drivers/bus/mhi/ep/main.c
View File

@ -1242,9 +1242,13 @@ static int mhi_ep_create_device(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id)
/* Channel name is same for both UL and DL */
mhi_dev->name = mhi_chan->name;
dev_set_name(&mhi_dev->dev, "%s_%s",
ret = dev_set_name(&mhi_dev->dev, "%s_%s",
dev_name(&mhi_cntrl->mhi_dev->dev),
mhi_dev->name);
if (ret) {
put_device(&mhi_dev->dev);
return ret;
}
ret = device_add(&mhi_dev->dev);
if (ret)
@ -1408,7 +1412,10 @@ int mhi_ep_register_controller(struct mhi_ep_cntrl *mhi_cntrl,
goto err_free_irq;
}
dev_set_name(&mhi_dev->dev, "mhi_ep%u", mhi_cntrl->index);
ret = dev_set_name(&mhi_dev->dev, "mhi_ep%u", mhi_cntrl->index);
if (ret)
goto err_put_dev;
mhi_dev->name = dev_name(&mhi_dev->dev);
mhi_cntrl->mhi_dev = mhi_dev;

17
drivers/bus/mhi/host/init.c
View File

@ -178,6 +178,12 @@ int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl)
"bhi", mhi_cntrl);
if (ret)
return ret;
/*
* IRQs should be enabled during mhi_async_power_up(), so disable them explicitly here.
* Due to the use of IRQF_SHARED flag as default while requesting IRQs, we assume that
* IRQ_NOAUTOEN is not applicable.
*/
disable_irq(mhi_cntrl->irq[0]);
for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
if (mhi_event->offload_ev)
@ -199,6 +205,8 @@ int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl)
mhi_cntrl->irq[mhi_event->irq], i);
goto error_request;
}
disable_irq(mhi_cntrl->irq[mhi_event->irq]);
}
return 0;
@ -978,12 +986,16 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl,
goto err_destroy_wq;
}
ret = mhi_init_irq_setup(mhi_cntrl);
if (ret)
goto err_ida_free;
/* Register controller with MHI bus */
mhi_dev = mhi_alloc_device(mhi_cntrl);
if (IS_ERR(mhi_dev)) {
dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate MHI device\n");
ret = PTR_ERR(mhi_dev);
goto err_ida_free;
goto error_setup_irq;
}
mhi_dev->dev_type = MHI_DEVICE_CONTROLLER;
@ -1006,6 +1018,8 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl,
err_release_dev:
put_device(&mhi_dev->dev);
error_setup_irq:
mhi_deinit_free_irq(mhi_cntrl);
err_ida_free:
ida_free(&mhi_controller_ida, mhi_cntrl->index);
err_destroy_wq:
@ -1026,6 +1040,7 @@ void mhi_unregister_controller(struct mhi_controller *mhi_cntrl)
struct mhi_chan *mhi_chan = mhi_cntrl->mhi_chan;
unsigned int i;
mhi_deinit_free_irq(mhi_cntrl);
mhi_destroy_debugfs(mhi_cntrl);
destroy_workqueue(mhi_cntrl->hiprio_wq);

8
drivers/bus/mhi/host/pci_generic.c
View File

@ -557,6 +557,8 @@ static const struct pci_device_id mhi_pci_id_table[] = {
.driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
{ PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
.driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
{ PCI_DEVICE(0x1eac, 0x2001), /* EM120R-GL for FCCL (sdx24) */
.driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
/* T99W175 (sdx55), Both for eSIM and Non-eSIM */
{ PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab),
.driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
@ -569,6 +571,9 @@ static const struct pci_device_id mhi_pci_id_table[] = {
/* T99W175 (sdx55), Based on Qualcomm new baseline */
{ PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf),
.driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
/* T99W175 (sdx55) */
{ PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0c3),
.driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
/* T99W368 (sdx65) */
{ PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d8),
.driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info },
@ -578,6 +583,9 @@ static const struct pci_device_id mhi_pci_id_table[] = {
/* MV31-W (Cinterion) */
{ PCI_DEVICE(0x1269, 0x00b3),
.driver_data = (kernel_ulong_t) &mhi_mv31_info },
/* MV31-W (Cinterion), based on new baseline */
{ PCI_DEVICE(0x1269, 0x00b4),
.driver_data = (kernel_ulong_t) &mhi_mv31_info },
/* MV32-WA (Cinterion) */
{ PCI_DEVICE(0x1269, 0x00ba),
.driver_data = (kernel_ulong_t) &mhi_mv32_info },

19
drivers/bus/mhi/host/pm.c
View File

@ -500,7 +500,7 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl)
for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
if (mhi_event->offload_ev)
continue;
free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);
disable_irq(mhi_cntrl->irq[mhi_event->irq]);
tasklet_kill(&mhi_event->task);
}
@ -1060,12 +1060,13 @@ static void mhi_deassert_dev_wake(struct mhi_controller *mhi_cntrl,
int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
{
struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
enum mhi_state state;
enum mhi_ee_type current_ee;
enum dev_st_transition next_state;
struct device *dev = &mhi_cntrl->mhi_dev->dev;
u32 interval_us = 25000; /* poll register field every 25 milliseconds */
int ret;
int ret, i;
dev_info(dev, "Requested to power ON\n");
@ -1117,9 +1118,15 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
}
ret = mhi_init_irq_setup(mhi_cntrl);
if (ret)
goto error_exit;
/* IRQs have been requested during probe, so we just need to enable them. */
enable_irq(mhi_cntrl->irq[0]);
for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
if (mhi_event->offload_ev)
continue;
enable_irq(mhi_cntrl->irq[mhi_event->irq]);
}
/* Transition to next state */
next_state = MHI_IN_PBL(current_ee) ?
@ -1182,7 +1189,7 @@ void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful)
/* Wait for shutdown to complete */
flush_work(&mhi_cntrl->st_worker);
free_irq(mhi_cntrl->irq[0], mhi_cntrl);
disable_irq(mhi_cntrl->irq[0]);
}
EXPORT_SYMBOL_GPL(mhi_power_down);

6
drivers/bus/mvebu-mbus.c
View File

@ -25,8 +25,8 @@
*
* - Reads out the SDRAM address decoding windows at initialization
* time, and fills the mvebu_mbus_dram_info structure with these
* informations. The exported function mv_mbus_dram_info() allow
* device drivers to get those informations related to the SDRAM
* information. The exported function mv_mbus_dram_info() allow
* device drivers to get those information related to the SDRAM
* address decoding windows. This is because devices also have their
* own windows (configured through registers that are part of each
* device register space), and therefore the drivers for Marvell
@ -123,7 +123,7 @@ struct mvebu_mbus_soc_data {
};
/*
* Used to store the state of one MBus window accross suspend/resume.
* Used to store the state of one MBus window across suspend/resume.
*/
struct mvebu_mbus_win_data {
u32 ctrl;

5
drivers/char/Kconfig
View File

@ -247,11 +247,6 @@ config SONYPI
To compile this driver as a module, choose M here: the
module will be called sonypi.
config GPIO_TB0219
tristate "TANBAC TB0219 GPIO support"
depends on TANBAC_TB022X
select GPIO_VR41XX
source "drivers/char/pcmcia/Kconfig"
config MWAVE

1
drivers/char/Makefile
View File

@ -31,7 +31,6 @@ obj-$(CONFIG_NWFLASH) += nwflash.o
obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o
obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o
obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o
obj-$(CONFIG_GPIO_TB0219) += tb0219.o
obj-$(CONFIG_TELCLOCK) += tlclk.o
obj-$(CONFIG_MWAVE) += mwave/

2
drivers/char/apm-emulation.c
View File

@ -544,7 +544,7 @@ static int apm_suspend_notifier(struct notifier_block *nb,
wake_up_interruptible(&apm_waitqueue);
/*
* Wait for the the suspend_acks_pending variable to drop to
* Wait for the suspend_acks_pending variable to drop to
* zero, meaning everybody acked the suspend event (or the
* process was killed.)
*

4
drivers/char/random.c
View File

@ -763,8 +763,8 @@ static int random_pm_notification(struct notifier_block *nb, unsigned long actio
spin_unlock_irqrestore(&input_pool.lock, flags);
if (crng_ready() && (action == PM_RESTORE_PREPARE ||
(action == PM_POST_SUSPEND &&
!IS_ENABLED(CONFIG_PM_AUTOSLEEP) && !IS_ENABLED(CONFIG_ANDROID)))) {
(action == PM_POST_SUSPEND && !IS_ENABLED(CONFIG_PM_AUTOSLEEP) &&
!IS_ENABLED(CONFIG_PM_USERSPACE_AUTOSLEEP)))) {
crng_reseed();
pr_notice("crng reseeded on system resumption\n");
}

359
drivers/char/tb0219.c
View File

@ -1,359 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for TANBAC TB0219 base board.
*
* Copyright (C) 2005 Yoichi Yuasa <yuasa@linux-mips.org>
*/
#include <linux/platform_device.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/uaccess.h>
#include <asm/io.h>
#include <asm/reboot.h>
#include <asm/vr41xx/giu.h>
#include <asm/vr41xx/tb0219.h>
MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
MODULE_DESCRIPTION("TANBAC TB0219 base board driver");
MODULE_LICENSE("GPL");
static int major; /* default is dynamic major device number */
module_param(major, int, 0);
MODULE_PARM_DESC(major, "Major device number");
static void (*old_machine_restart)(char *command);
static void __iomem *tb0219_base;
static DEFINE_SPINLOCK(tb0219_lock);
#define tb0219_read(offset) readw(tb0219_base + (offset))
#define tb0219_write(offset, value) writew((value), tb0219_base + (offset))
#define TB0219_START 0x0a000000UL
#define TB0219_SIZE 0x20UL
#define TB0219_LED 0x00
#define TB0219_GPIO_INPUT 0x02
#define TB0219_GPIO_OUTPUT 0x04
#define TB0219_DIP_SWITCH 0x06
#define TB0219_MISC 0x08
#define TB0219_RESET 0x0e
#define TB0219_PCI_SLOT1_IRQ_STATUS 0x10
#define TB0219_PCI_SLOT2_IRQ_STATUS 0x12
#define TB0219_PCI_SLOT3_IRQ_STATUS 0x14
typedef enum {
TYPE_LED,
TYPE_GPIO_OUTPUT,
} tb0219_type_t;
/*
* Minor device number
* 0 = 7 segment LED
*
* 16 = GPIO IN 0
* 17 = GPIO IN 1
* 18 = GPIO IN 2
* 19 = GPIO IN 3
* 20 = GPIO IN 4
* 21 = GPIO IN 5
* 22 = GPIO IN 6
* 23 = GPIO IN 7
*
* 32 = GPIO OUT 0
* 33 = GPIO OUT 1
* 34 = GPIO OUT 2
* 35 = GPIO OUT 3
* 36 = GPIO OUT 4
* 37 = GPIO OUT 5
* 38 = GPIO OUT 6
* 39 = GPIO OUT 7
*
* 48 = DIP switch 1
* 49 = DIP switch 2
* 50 = DIP switch 3
* 51 = DIP switch 4
* 52 = DIP switch 5
* 53 = DIP switch 6
* 54 = DIP switch 7
* 55 = DIP switch 8
*/
static inline char get_led(void)
{
return (char)tb0219_read(TB0219_LED);
}
static inline char get_gpio_input_pin(unsigned int pin)
{
uint16_t values;
values = tb0219_read(TB0219_GPIO_INPUT);
if (values & (1 << pin))
return '1';
return '0';
}
static inline char get_gpio_output_pin(unsigned int pin)
{
uint16_t values;
values = tb0219_read(TB0219_GPIO_OUTPUT);
if (values & (1 << pin))
return '1';
return '0';
}
static inline char get_dip_switch(unsigned int pin)
{
uint16_t values;
values = tb0219_read(TB0219_DIP_SWITCH);
if (values & (1 << pin))
return '1';
return '0';
}
static inline int set_led(char command)
{
tb0219_write(TB0219_LED, command);
return 0;
}
static inline int set_gpio_output_pin(unsigned int pin, char command)
{
unsigned long flags;
uint16_t value;
if (command != '0' && command != '1')
return -EINVAL;
spin_lock_irqsave(&tb0219_lock, flags);
value = tb0219_read(TB0219_GPIO_OUTPUT);
if (command == '0')
value &= ~(1 << pin);
else
value |= 1 << pin;
tb0219_write(TB0219_GPIO_OUTPUT, value);
spin_unlock_irqrestore(&tb0219_lock, flags);
return 0;
}
static ssize_t tanbac_tb0219_read(struct file *file, char __user *buf, size_t len,
loff_t *ppos)
{
unsigned int minor;
char value;
minor = iminor(file_inode(file));
switch (minor) {
case 0:
value = get_led();
break;
case 16 ... 23:
value = get_gpio_input_pin(minor - 16);
break;
case 32 ... 39:
value = get_gpio_output_pin(minor - 32);
break;
case 48 ... 55:
value = get_dip_switch(minor - 48);
break;
default:
return -EBADF;
}
if (len <= 0)
return -EFAULT;
if (put_user(value, buf))
return -EFAULT;
return 1;
}
static ssize_t tanbac_tb0219_write(struct file *file, const char __user *data,
size_t len, loff_t *ppos)
{
unsigned int minor;
tb0219_type_t type;
size_t i;
int retval = 0;
char c;
minor = iminor(file_inode(file));
switch (minor) {
case 0:
type = TYPE_LED;
break;
case 32 ... 39:
type = TYPE_GPIO_OUTPUT;
break;
default:
return -EBADF;
}
for (i = 0; i < len; i++) {
if (get_user(c, data + i))
return -EFAULT;
switch (type) {
case TYPE_LED:
retval = set_led(c);
break;
case TYPE_GPIO_OUTPUT:
retval = set_gpio_output_pin(minor - 32, c);
break;
}
if (retval < 0)
break;
}
return i;
}
static int tanbac_tb0219_open(struct inode *inode, struct file *file)
{
unsigned int minor;
minor = iminor(inode);
switch (minor) {
case 0:
case 16 ... 23:
case 32 ... 39:
case 48 ... 55:
return stream_open(inode, file);
default:
break;
}
return -EBADF;
}
static int tanbac_tb0219_release(struct inode *inode, struct file *file)
{
return 0;
}
static const struct file_operations tb0219_fops = {
.owner = THIS_MODULE,
.read = tanbac_tb0219_read,
.write = tanbac_tb0219_write,
.open = tanbac_tb0219_open,
.release = tanbac_tb0219_release,
.llseek = no_llseek,
};
static void tb0219_restart(char *command)
{
tb0219_write(TB0219_RESET, 0);
}
static void tb0219_pci_irq_init(void)
{
/* PCI Slot 1 */
vr41xx_set_irq_trigger(TB0219_PCI_SLOT1_PIN, IRQ_TRIGGER_LEVEL, IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(TB0219_PCI_SLOT1_PIN, IRQ_LEVEL_LOW);
/* PCI Slot 2 */
vr41xx_set_irq_trigger(TB0219_PCI_SLOT2_PIN, IRQ_TRIGGER_LEVEL, IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(TB0219_PCI_SLOT2_PIN, IRQ_LEVEL_LOW);
/* PCI Slot 3 */
vr41xx_set_irq_trigger(TB0219_PCI_SLOT3_PIN, IRQ_TRIGGER_LEVEL, IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(TB0219_PCI_SLOT3_PIN, IRQ_LEVEL_LOW);
}
static int tb0219_probe(struct platform_device *dev)
{
int retval;
if (request_mem_region(TB0219_START, TB0219_SIZE, "TB0219") == NULL)
return -EBUSY;
tb0219_base = ioremap(TB0219_START, TB0219_SIZE);
if (tb0219_base == NULL) {
release_mem_region(TB0219_START, TB0219_SIZE);
return -ENOMEM;
}
retval = register_chrdev(major, "TB0219", &tb0219_fops);
if (retval < 0) {
iounmap(tb0219_base);
tb0219_base = NULL;
release_mem_region(TB0219_START, TB0219_SIZE);
return retval;
}
old_machine_restart = _machine_restart;
_machine_restart = tb0219_restart;
tb0219_pci_irq_init();
if (major == 0) {
major = retval;
printk(KERN_INFO "TB0219: major number %d\n", major);
}
return 0;
}
static int tb0219_remove(struct platform_device *dev)
{
_machine_restart = old_machine_restart;
iounmap(tb0219_base);
tb0219_base = NULL;
release_mem_region(TB0219_START, TB0219_SIZE);
return 0;
}
static struct platform_device *tb0219_platform_device;
static struct platform_driver tb0219_device_driver = {
.probe = tb0219_probe,
.remove = tb0219_remove,
.driver = {
.name = "TB0219",
},
};
static int __init tanbac_tb0219_init(void)
{
int retval;
tb0219_platform_device = platform_device_alloc("TB0219", -1);
if (!tb0219_platform_device)
return -ENOMEM;
retval = platform_device_add(tb0219_platform_device);
if (retval < 0) {
platform_device_put(tb0219_platform_device);
return retval;
}
retval = platform_driver_register(&tb0219_device_driver);
if (retval < 0)
platform_device_unregister(tb0219_platform_device);
return retval;
}
static void __exit tanbac_tb0219_exit(void)
{
platform_driver_unregister(&tb0219_device_driver);
platform_device_unregister(tb0219_platform_device);
}
module_init(tanbac_tb0219_init);
module_exit(tanbac_tb0219_exit);

203
drivers/counter/104-quad-8.c
View File

@ -33,6 +33,36 @@ MODULE_PARM_DESC(irq, "ACCES 104-QUAD-8 interrupt line numbers");
#define QUAD8_NUM_COUNTERS 8
/**
* struct channel_reg - channel register structure
* @data: Count data
* @control: Channel flags and control
*/
struct channel_reg {
u8 data;
u8 control;
};
/**
* struct quad8_reg - device register structure
* @channel: quadrature counter data and control
* @interrupt_status: channel interrupt status
* @channel_oper: enable/reset counters and interrupt functions
* @index_interrupt: enable channel interrupts
* @reserved: reserved for Factory Use
* @index_input_levels: index signal logical input level
* @cable_status: differential encoder cable status
*/
struct quad8_reg {
struct channel_reg channel[QUAD8_NUM_COUNTERS];
u8 interrupt_status;
u8 channel_oper;
u8 index_interrupt;
u8 reserved[3];
u8 index_input_levels;
u8 cable_status;
};
/**
* struct quad8 - device private data structure
* @lock: lock to prevent clobbering device states during R/W ops
@ -48,7 +78,7 @@ MODULE_PARM_DESC(irq, "ACCES 104-QUAD-8 interrupt line numbers");
* @synchronous_mode: array of index function synchronous mode configurations
* @index_polarity: array of index function polarity configurations
* @cable_fault_enable: differential encoder cable status enable configurations
* @base: base port address of the device
* @reg: I/O address offset for the device registers
*/
struct quad8 {
spinlock_t lock;
@ -63,14 +93,9 @@ struct quad8 {
unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
unsigned int index_polarity[QUAD8_NUM_COUNTERS];
unsigned int cable_fault_enable;
unsigned int base;
struct quad8_reg __iomem *reg;
};
#define QUAD8_REG_INTERRUPT_STATUS 0x10
#define QUAD8_REG_CHAN_OP 0x11
#define QUAD8_REG_INDEX_INTERRUPT 0x12
#define QUAD8_REG_INDEX_INPUT_LEVELS 0x16
#define QUAD8_DIFF_ENCODER_CABLE_STATUS 0x17
/* Borrow Toggle flip-flop */
#define QUAD8_FLAG_BT BIT(0)
/* Carry Toggle flip-flop */
@ -118,8 +143,7 @@ static int quad8_signal_read(struct counter_device *counter,
if (signal->id < 16)
return -EINVAL;
state = inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS)
& BIT(signal->id - 16);
state = ioread8(&priv->reg->index_input_levels) & BIT(signal->id - 16);
*level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
@ -130,14 +154,14 @@ static int quad8_count_read(struct counter_device *counter,
struct counter_count *count, u64 *val)
{
struct quad8 *const priv = counter_priv(counter);
const int base_offset = priv->base + 2 * count->id;
struct channel_reg __iomem *const chan = priv->reg->channel + count->id;
unsigned int flags;
unsigned int borrow;
unsigned int carry;
unsigned long irqflags;
int i;
flags = inb(base_offset + 1);
flags = ioread8(&chan->control);
borrow = flags & QUAD8_FLAG_BT;
carry = !!(flags & QUAD8_FLAG_CT);
@ -147,11 +171,11 @@ static int quad8_count_read(struct counter_device *counter,
spin_lock_irqsave(&priv->lock, irqflags);
/* Reset Byte Pointer; transfer Counter to Output Latch */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
base_offset + 1);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
&chan->control);
for (i = 0; i < 3; i++)
*val |= (unsigned long)inb(base_offset) << (8 * i);
*val |= (unsigned long)ioread8(&chan->data) << (8 * i);
spin_unlock_irqrestore(&priv->lock, irqflags);
@ -162,7 +186,7 @@ static int quad8_count_write(struct counter_device *counter,
struct counter_count *count, u64 val)
{
struct quad8 *const priv = counter_priv(counter);
const int base_offset = priv->base + 2 * count->id;
struct channel_reg __iomem *const chan = priv->reg->channel + count->id;
unsigned long irqflags;
int i;
@ -173,27 +197,27 @@ static int quad8_count_write(struct counter_device *counter,
spin_lock_irqsave(&priv->lock, irqflags);
/* Reset Byte Pointer */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
/* Counter can only be set via Preset Register */
for (i = 0; i < 3; i++)
outb(val >> (8 * i), base_offset);
iowrite8(val >> (8 * i), &chan->data);
/* Transfer Preset Register to Counter */
outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, &chan->control);
/* Reset Byte Pointer */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
/* Set Preset Register back to original value */
val = priv->preset[count->id];
for (i = 0; i < 3; i++)
outb(val >> (8 * i), base_offset);
iowrite8(val >> (8 * i), &chan->data);
/* Reset Borrow, Carry, Compare, and Sign flags */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control);
/* Reset Error flag */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control);
spin_unlock_irqrestore(&priv->lock, irqflags);
@ -246,7 +270,7 @@ static int quad8_function_write(struct counter_device *counter,
unsigned int *const quadrature_mode = priv->quadrature_mode + id;
unsigned int *const scale = priv->quadrature_scale + id;
unsigned int *const synchronous_mode = priv->synchronous_mode + id;
const int base_offset = priv->base + 2 * id + 1;
u8 __iomem *const control = &priv->reg->channel[id].control;
unsigned long irqflags;
unsigned int mode_cfg;
unsigned int idr_cfg;
@ -266,7 +290,7 @@ static int quad8_function_write(struct counter_device *counter,
if (*synchronous_mode) {
*synchronous_mode = 0;
/* Disable synchronous function mode */
outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
}
} else {
*quadrature_mode = 1;
@ -292,7 +316,7 @@ static int quad8_function_write(struct counter_device *counter,
}
/* Load mode configuration to Counter Mode Register */
outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
iowrite8(QUAD8_CTR_CMR | mode_cfg, control);
spin_unlock_irqrestore(&priv->lock, irqflags);
@ -305,10 +329,10 @@ static int quad8_direction_read(struct counter_device *counter,
{
const struct quad8 *const priv = counter_priv(counter);
unsigned int ud_flag;
const unsigned int flag_addr = priv->base + 2 * count->id + 1;
u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control;
/* U/D flag: nonzero = up, zero = down */
ud_flag = inb(flag_addr) & QUAD8_FLAG_UD;
ud_flag = ioread8(flag_addr) & QUAD8_FLAG_UD;
*direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD :
COUNTER_COUNT_DIRECTION_BACKWARD;
@ -402,7 +426,6 @@ static int quad8_events_configure(struct counter_device *counter)
struct counter_event_node *event_node;
unsigned int next_irq_trigger;
unsigned long ior_cfg;
unsigned long base_offset;
spin_lock_irqsave(&priv->lock, irqflags);
@ -437,14 +460,14 @@ static int quad8_events_configure(struct counter_device *counter)
ior_cfg = priv->ab_enable[event_node->channel] |
priv->preset_enable[event_node->channel] << 1 |
priv->irq_trigger[event_node->channel] << 3;
base_offset = priv->base + 2 * event_node->channel + 1;
outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
iowrite8(QUAD8_CTR_IOR | ior_cfg,
&priv->reg->channel[event_node->channel].control);
/* Enable IRQ line */
irq_enabled |= BIT(event_node->channel);
}
outb(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT);
iowrite8(irq_enabled, &priv->reg->index_interrupt);
spin_unlock_irqrestore(&priv->lock, irqflags);
@ -508,7 +531,7 @@ static int quad8_index_polarity_set(struct counter_device *counter,
{
struct quad8 *const priv = counter_priv(counter);
const size_t channel_id = signal->id - 16;
const int base_offset = priv->base + 2 * channel_id + 1;
u8 __iomem *const control = &priv->reg->channel[channel_id].control;
unsigned long irqflags;
unsigned int idr_cfg = index_polarity << 1;
@ -519,7 +542,7 @@ static int quad8_index_polarity_set(struct counter_device *counter,
priv->index_polarity[channel_id] = index_polarity;
/* Load Index Control configuration to Index Control Register */
outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
spin_unlock_irqrestore(&priv->lock, irqflags);
@ -549,7 +572,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
{
struct quad8 *const priv = counter_priv(counter);
const size_t channel_id = signal->id - 16;
const int base_offset = priv->base + 2 * channel_id + 1;
u8 __iomem *const control = &priv->reg->channel[channel_id].control;
unsigned long irqflags;
unsigned int idr_cfg = synchronous_mode;
@ -566,7 +589,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
priv->synchronous_mode[channel_id] = synchronous_mode;
/* Load Index Control configuration to Index Control Register */
outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
spin_unlock_irqrestore(&priv->lock, irqflags);
@ -614,7 +637,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
struct quad8 *const priv = counter_priv(counter);
unsigned int count_mode;
unsigned int mode_cfg;
const int base_offset = priv->base + 2 * count->id + 1;
u8 __iomem *const control = &priv->reg->channel[count->id].control;
unsigned long irqflags;
/* Map Generic Counter count mode to 104-QUAD-8 count mode */
@ -648,7 +671,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3;
/* Load mode configuration to Counter Mode Register */
outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
iowrite8(QUAD8_CTR_CMR | mode_cfg, control);
spin_unlock_irqrestore(&priv->lock, irqflags);
@ -669,7 +692,7 @@ static int quad8_count_enable_write(struct counter_device *counter,
struct counter_count *count, u8 enable)
{
struct quad8 *const priv = counter_priv(counter);
const int base_offset = priv->base + 2 * count->id;
u8 __iomem *const control = &priv->reg->channel[count->id].control;
unsigned long irqflags;
unsigned int ior_cfg;
@ -681,7 +704,7 @@ static int quad8_count_enable_write(struct counter_device *counter,
priv->irq_trigger[count->id] << 3;
/* Load I/O control configuration */
outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
iowrite8(QUAD8_CTR_IOR | ior_cfg, control);
spin_unlock_irqrestore(&priv->lock, irqflags);
@ -697,9 +720,9 @@ static int quad8_error_noise_get(struct counter_device *counter,
struct counter_count *count, u32 *noise_error)
{
const struct quad8 *const priv = counter_priv(counter);
const int base_offset = priv->base + 2 * count->id + 1;
u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control;
*noise_error = !!(inb(base_offset) & QUAD8_FLAG_E);
*noise_error = !!(ioread8(flag_addr) & QUAD8_FLAG_E);
return 0;
}
@ -717,17 +740,17 @@ static int quad8_count_preset_read(struct counter_device *counter,
static void quad8_preset_register_set(struct quad8 *const priv, const int id,
const unsigned int preset)
{
const unsigned int base_offset = priv->base + 2 * id;
struct channel_reg __iomem *const chan = priv->reg->channel + id;
int i;
priv->preset[id] = preset;
/* Reset Byte Pointer */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
/* Set Preset Register */
for (i = 0; i < 3; i++)
outb(preset >> (8 * i), base_offset);
iowrite8(preset >> (8 * i), &chan->data);
}
static int quad8_count_preset_write(struct counter_device *counter,
@ -816,7 +839,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter,
u8 preset_enable)
{
struct quad8 *const priv = counter_priv(counter);
const int base_offset = priv->base + 2 * count->id + 1;
u8 __iomem *const control = &priv->reg->channel[count->id].control;
unsigned long irqflags;
unsigned int ior_cfg;
@ -831,7 +854,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter,
priv->irq_trigger[count->id] << 3;
/* Load I/O control configuration to Input / Output Control Register */
outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
iowrite8(QUAD8_CTR_IOR | ior_cfg, control);
spin_unlock_irqrestore(&priv->lock, irqflags);
@ -858,7 +881,7 @@ static int quad8_signal_cable_fault_read(struct counter_device *counter,
}
/* Logic 0 = cable fault */
status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
status = ioread8(&priv->reg->cable_status);
spin_unlock_irqrestore(&priv->lock, irqflags);
@ -899,7 +922,7 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter,
/* Enable is active low in Differential Encoder Cable Status register */
cable_fault_enable = ~priv->cable_fault_enable;
outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
iowrite8(cable_fault_enable, &priv->reg->cable_status);
spin_unlock_irqrestore(&priv->lock, irqflags);
@ -923,7 +946,7 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
{
struct quad8 *const priv = counter_priv(counter);
const size_t channel_id = signal->id / 2;
const int base_offset = priv->base + 2 * channel_id;
struct channel_reg __iomem *const chan = priv->reg->channel + channel_id;
unsigned long irqflags;
spin_lock_irqsave(&priv->lock, irqflags);
@ -931,12 +954,12 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
priv->fck_prescaler[channel_id] = prescaler;
/* Reset Byte Pointer */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
/* Set filter clock factor */
outb(prescaler, base_offset);
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
base_offset + 1);
iowrite8(prescaler, &chan->data);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
&chan->control);
spin_unlock_irqrestore(&priv->lock, irqflags);
@ -1084,12 +1107,11 @@ static irqreturn_t quad8_irq_handler(int irq, void *private)
{
struct counter_device *counter = private;
struct quad8 *const priv = counter_priv(counter);
const unsigned long base = priv->base;
unsigned long irq_status;
unsigned long channel;
u8 event;
irq_status = inb(base + QUAD8_REG_INTERRUPT_STATUS);
irq_status = ioread8(&priv->reg->interrupt_status);
if (!irq_status)
return IRQ_NONE;
@ -1118,17 +1140,43 @@ static irqreturn_t quad8_irq_handler(int irq, void *private)
}
/* Clear pending interrupts on device */
outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP);
iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper);
return IRQ_HANDLED;
}
static void quad8_init_counter(struct channel_reg __iomem *const chan)
{
unsigned long i;
/* Reset Byte Pointer */
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
/* Reset filter clock factor */
iowrite8(0, &chan->data);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
&chan->control);
/* Reset Byte Pointer */
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
/* Reset Preset Register */
for (i = 0; i < 3; i++)
iowrite8(0x00, &chan->data);
/* Reset Borrow, Carry, Compare, and Sign flags */
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control);
/* Reset Error flag */
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control);
/* Binary encoding; Normal count; non-quadrature mode */
iowrite8(QUAD8_CTR_CMR, &chan->control);
/* Disable A and B inputs; preset on index; FLG1 as Carry */
iowrite8(QUAD8_CTR_IOR, &chan->control);
/* Disable index function; negative index polarity */
iowrite8(QUAD8_CTR_IDR, &chan->control);
}
static int quad8_probe(struct device *dev, unsigned int id)
{
struct counter_device *counter;
struct quad8 *priv;
int i, j;
unsigned int base_offset;
unsigned long i;
int err;
if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) {
@ -1142,6 +1190,10 @@ static int quad8_probe(struct device *dev, unsigned int id)
return -ENOMEM;
priv = counter_priv(counter);
priv->reg = devm_ioport_map(dev, base[id], QUAD8_EXTENT);
if (!priv->reg)
return -ENOMEM;
/* Initialize Counter device and driver data */
counter->name = dev_name(dev);
counter->parent = dev;
@ -1150,43 +1202,20 @@ static int quad8_probe(struct device *dev, unsigned int id)
counter->num_counts = ARRAY_SIZE(quad8_counts);
counter->signals = quad8_signals;
counter->num_signals = ARRAY_SIZE(quad8_signals);
priv->base = base[id];
spin_lock_init(&priv->lock);
/* Reset Index/Interrupt Register */
outb(0x00, base[id] + QUAD8_REG_INDEX_INTERRUPT);
iowrite8(0x00, &priv->reg->index_interrupt);
/* Reset all counters and disable interrupt function */
outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, &priv->reg->channel_oper);
/* Set initial configuration for all counters */
for (i = 0; i < QUAD8_NUM_COUNTERS; i++) {
base_offset = base[id] + 2 * i;
/* Reset Byte Pointer */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
/* Reset filter clock factor */
outb(0, base_offset);
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
base_offset + 1);
/* Reset Byte Pointer */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
/* Reset Preset Register */
for (j = 0; j < 3; j++)
outb(0x00, base_offset);
/* Reset Borrow, Carry, Compare, and Sign flags */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
/* Reset Error flag */
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
/* Binary encoding; Normal count; non-quadrature mode */
outb(QUAD8_CTR_CMR, base_offset + 1);
/* Disable A and B inputs; preset on index; FLG1 as Carry */
outb(QUAD8_CTR_IOR, base_offset + 1);
/* Disable index function; negative index polarity */
outb(QUAD8_CTR_IDR, base_offset + 1);
}
for (i = 0; i < QUAD8_NUM_COUNTERS; i++)
quad8_init_counter(priv->reg->channel + i);
/* Disable Differential Encoder Cable Status for all channels */
outb(0xFF, base[id] + QUAD8_DIFF_ENCODER_CABLE_STATUS);
iowrite8(0xFF, &priv->reg->cable_status);
/* Enable all counters and enable interrupt function */
outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base[id] + QUAD8_REG_CHAN_OP);
iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper);
err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler,
IRQF_SHARED, counter->name, counter);

1
drivers/devfreq/imx-bus.c
View File

@ -145,6 +145,7 @@ static const struct of_device_id imx_bus_of_match[] = {
{ .compatible = "fsl,imx8mq-noc", .data = "imx8mq-interconnect", },
{ .compatible = "fsl,imx8mm-noc", .data = "imx8mm-interconnect", },
{ .compatible = "fsl,imx8mn-noc", .data = "imx8mn-interconnect", },
{ .compatible = "fsl,imx8mp-noc", .data = "imx8mp-interconnect", },
{ .compatible = "fsl,imx8m-noc", },
{ .compatible = "fsl,imx8m-nic", },
{ /* sentinel */ },

6
drivers/extcon/extcon-fsa9480.c
View File

@ -324,11 +324,6 @@ static int fsa9480_probe(struct i2c_client *client,
return 0;
}
static int fsa9480_remove(struct i2c_client *client)
{
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int fsa9480_suspend(struct device *dev)
{
@ -376,7 +371,6 @@ static struct i2c_driver fsa9480_i2c_driver = {
.of_match_table = fsa9480_of_match,
},
.probe = fsa9480_probe,
.remove = fsa9480_remove,
.id_table = fsa9480_id,
};

2
drivers/extcon/extcon-palmas.c
View File

@ -107,7 +107,7 @@ static irqreturn_t palmas_id_irq_handler(int irq, void *_palmas_usb)
(id_src & PALMAS_USB_ID_INT_SRC_ID_GND)) {
palmas_usb->linkstat = PALMAS_USB_STATE_ID;
extcon_set_state_sync(edev, EXTCON_USB_HOST, true);
dev_dbg(palmas_usb->dev, " USB-HOST cable is attached\n");
dev_dbg(palmas_usb->dev, "USB-HOST cable is attached\n");
}
return IRQ_HANDLED;

1
drivers/extcon/extcon-rt8973a.c
View File

@ -192,7 +192,6 @@ static const struct regmap_irq_chip rt8973a_muic_irq_chip = {
.name = "rt8973a",
.status_base = RT8973A_REG_INT1,
.mask_base = RT8973A_REG_INTM1,
.mask_invert = false,
.num_regs = 2,
.irqs = rt8973a_irqs,
.num_irqs = ARRAY_SIZE(rt8973a_irqs),

2
drivers/extcon/extcon-sm5502.c
View File

@ -227,7 +227,6 @@ static const struct regmap_irq_chip sm5502_muic_irq_chip = {
.name = "sm5502",
.status_base = SM5502_REG_INT1,
.mask_base = SM5502_REG_INTMASK1,
.mask_invert = false,
.num_regs = 2,
.irqs = sm5502_irqs,
.num_irqs = ARRAY_SIZE(sm5502_irqs),
@ -276,7 +275,6 @@ static const struct regmap_irq_chip sm5504_muic_irq_chip = {
.name = "sm5504",
.status_base = SM5502_REG_INT1,
.mask_base = SM5502_REG_INTMASK1,
.mask_invert = false,
.num_regs = 2,
.irqs = sm5504_irqs,
.num_irqs = ARRAY_SIZE(sm5504_irqs),

12
drivers/extcon/extcon.c
View File

@ -167,6 +167,16 @@ static const struct __extcon_info {
.id = EXTCON_DISP_HMD,
.name = "HMD",
},
[EXTCON_DISP_CVBS] = {
.type = EXTCON_TYPE_DISP,
.id = EXTCON_DISP_CVBS,
.name = "CVBS",
},
[EXTCON_DISP_EDP] = {
.type = EXTCON_TYPE_DISP,
.id = EXTCON_DISP_EDP,
.name = "EDP",
},
/* Miscellaneous external connector */
[EXTCON_DOCK] = {
@ -247,7 +257,7 @@ static int find_cable_index_by_id(struct extcon_dev *edev, const unsigned int id
{
int i;
/* Find the the index of extcon cable in edev->supported_cable */
/* Find the index of extcon cable in edev->supported_cable */
for (i = 0; i < edev->max_supported; i++) {
if (edev->supported_cable[i] == id)
return i;

129
drivers/firmware/stratix10-rsu.c
View File

@ -24,12 +24,16 @@
#define RSU_DCMF1_MASK GENMASK_ULL(63, 32)
#define RSU_DCMF2_MASK GENMASK_ULL(31, 0)
#define RSU_DCMF3_MASK GENMASK_ULL(63, 32)
#define RSU_DCMF0_STATUS_MASK GENMASK_ULL(15, 0)
#define RSU_DCMF1_STATUS_MASK GENMASK_ULL(31, 16)
#define RSU_DCMF2_STATUS_MASK GENMASK_ULL(47, 32)
#define RSU_DCMF3_STATUS_MASK GENMASK_ULL(63, 48)
#define RSU_TIMEOUT (msecs_to_jiffies(SVC_RSU_REQUEST_TIMEOUT_MS))
#define INVALID_RETRY_COUNTER 0xFF
#define INVALID_DCMF_VERSION 0xFF
#define INVALID_DCMF_STATUS 0xFFFFFFFF
typedef void (*rsu_callback)(struct stratix10_svc_client *client,
struct stratix10_svc_cb_data *data);
@ -49,6 +53,10 @@ typedef void (*rsu_callback)(struct stratix10_svc_client *client,
* @dcmf_version.dcmf1: Quartus dcmf1 version
* @dcmf_version.dcmf2: Quartus dcmf2 version
* @dcmf_version.dcmf3: Quartus dcmf3 version
* @dcmf_status.dcmf0: dcmf0 status
* @dcmf_status.dcmf1: dcmf1 status
* @dcmf_status.dcmf2: dcmf2 status
* @dcmf_status.dcmf3: dcmf3 status
* @retry_counter: the current image's retry counter
* @max_retry: the preset max retry value
*/
@ -73,6 +81,13 @@ struct stratix10_rsu_priv {
unsigned int dcmf3;
} dcmf_version;
struct {
unsigned int dcmf0;
unsigned int dcmf1;
unsigned int dcmf2;
unsigned int dcmf3;
} dcmf_status;
unsigned int retry_counter;
unsigned int max_retry;
};
@ -129,7 +144,7 @@ static void rsu_command_callback(struct stratix10_svc_client *client,
struct stratix10_rsu_priv *priv = client->priv;
if (data->status == BIT(SVC_STATUS_NO_SUPPORT))
dev_warn(client->dev, "FW doesn't support notify\n");
dev_warn(client->dev, "Secure FW doesn't support notify\n");
else if (data->status == BIT(SVC_STATUS_ERROR))
dev_err(client->dev, "Failure, returned status is %lu\n",
BIT(data->status));
@ -156,7 +171,7 @@ static void rsu_retry_callback(struct stratix10_svc_client *client,
if (data->status == BIT(SVC_STATUS_OK))
priv->retry_counter = *counter;
else if (data->status == BIT(SVC_STATUS_NO_SUPPORT))
dev_warn(client->dev, "FW doesn't support retry\n");
dev_warn(client->dev, "Secure FW doesn't support retry\n");
else
dev_err(client->dev, "Failed to get retry counter %lu\n",
BIT(data->status));
@ -181,7 +196,7 @@ static void rsu_max_retry_callback(struct stratix10_svc_client *client,
if (data->status == BIT(SVC_STATUS_OK))
priv->max_retry = *max_retry;
else if (data->status == BIT(SVC_STATUS_NO_SUPPORT))
dev_warn(client->dev, "FW doesn't support max retry\n");
dev_warn(client->dev, "Secure FW doesn't support max retry\n");
else
dev_err(client->dev, "Failed to get max retry %lu\n",
BIT(data->status));
@ -215,6 +230,35 @@ static void rsu_dcmf_version_callback(struct stratix10_svc_client *client,
complete(&priv->completion);
}
/**
* rsu_dcmf_status_callback() - Callback from Intel service layer for getting
* the DCMF status
* @client: pointer to client
* @data: pointer to callback data structure
*
* Callback from Intel service layer for DCMF status
*/
static void rsu_dcmf_status_callback(struct stratix10_svc_client *client,
struct stratix10_svc_cb_data *data)
{
struct stratix10_rsu_priv *priv = client->priv;
unsigned long long *value = (unsigned long long *)data->kaddr1;
if (data->status == BIT(SVC_STATUS_OK)) {
priv->dcmf_status.dcmf0 = FIELD_GET(RSU_DCMF0_STATUS_MASK,
*value);
priv->dcmf_status.dcmf1 = FIELD_GET(RSU_DCMF1_STATUS_MASK,
*value);
priv->dcmf_status.dcmf2 = FIELD_GET(RSU_DCMF2_STATUS_MASK,
*value);
priv->dcmf_status.dcmf3 = FIELD_GET(RSU_DCMF3_STATUS_MASK,
*value);
} else
dev_err(client->dev, "failed to get DCMF status\n");
complete(&priv->completion);
}
/**
* rsu_send_msg() - send a message to Intel service layer
* @priv: pointer to rsu private data
@ -361,7 +405,8 @@ static ssize_t max_retry_show(struct device *dev,
if (!priv)
return -ENODEV;
return sprintf(buf, "0x%08x\n", priv->max_retry);
return scnprintf(buf, sizeof(priv->max_retry),
"0x%08x\n", priv->max_retry);
}
static ssize_t dcmf0_show(struct device *dev,
@ -408,6 +453,61 @@ static ssize_t dcmf3_show(struct device *dev,
return sprintf(buf, "0x%08x\n", priv->dcmf_version.dcmf3);
}
static ssize_t dcmf0_status_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct stratix10_rsu_priv *priv = dev_get_drvdata(dev);
if (!priv)
return -ENODEV;
if (priv->dcmf_status.dcmf0 == INVALID_DCMF_STATUS)
return -EIO;
return sprintf(buf, "0x%08x\n", priv->dcmf_status.dcmf0);
}
static ssize_t dcmf1_status_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct stratix10_rsu_priv *priv = dev_get_drvdata(dev);
if (!priv)
return -ENODEV;
if (priv->dcmf_status.dcmf1 == INVALID_DCMF_STATUS)
return -EIO;
return sprintf(buf, "0x%08x\n", priv->dcmf_status.dcmf1);
}
static ssize_t dcmf2_status_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct stratix10_rsu_priv *priv = dev_get_drvdata(dev);
if (!priv)
return -ENODEV;
if (priv->dcmf_status.dcmf2 == INVALID_DCMF_STATUS)
return -EIO;
return sprintf(buf, "0x%08x\n", priv->dcmf_status.dcmf2);
}
static ssize_t dcmf3_status_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct stratix10_rsu_priv *priv = dev_get_drvdata(dev);
if (!priv)
return -ENODEV;
if (priv->dcmf_status.dcmf3 == INVALID_DCMF_STATUS)
return -EIO;
return sprintf(buf, "0x%08x\n", priv->dcmf_status.dcmf3);
}
static ssize_t reboot_image_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
@ -484,6 +584,10 @@ static DEVICE_ATTR_RO(dcmf0);
static DEVICE_ATTR_RO(dcmf1);
static DEVICE_ATTR_RO(dcmf2);
static DEVICE_ATTR_RO(dcmf3);
static DEVICE_ATTR_RO(dcmf0_status);
static DEVICE_ATTR_RO(dcmf1_status);
static DEVICE_ATTR_RO(dcmf2_status);
static DEVICE_ATTR_RO(dcmf3_status);
static DEVICE_ATTR_WO(reboot_image);
static DEVICE_ATTR_WO(notify);
@ -500,6 +604,10 @@ static struct attribute *rsu_attrs[] = {
&dev_attr_dcmf1.attr,
&dev_attr_dcmf2.attr,
&dev_attr_dcmf3.attr,
&dev_attr_dcmf0_status.attr,
&dev_attr_dcmf1_status.attr,
&dev_attr_dcmf2_status.attr,
&dev_attr_dcmf3_status.attr,
&dev_attr_reboot_image.attr,
&dev_attr_notify.attr,
NULL
@ -532,6 +640,10 @@ static int stratix10_rsu_probe(struct platform_device *pdev)
priv->dcmf_version.dcmf2 = INVALID_DCMF_VERSION;
priv->dcmf_version.dcmf3 = INVALID_DCMF_VERSION;
priv->max_retry = INVALID_RETRY_COUNTER;
priv->dcmf_status.dcmf0 = INVALID_DCMF_STATUS;
priv->dcmf_status.dcmf1 = INVALID_DCMF_STATUS;
priv->dcmf_status.dcmf2 = INVALID_DCMF_STATUS;
priv->dcmf_status.dcmf3 = INVALID_DCMF_STATUS;
mutex_init(&priv->lock);
priv->chan = stratix10_svc_request_channel_byname(&priv->client,
@ -561,6 +673,13 @@ static int stratix10_rsu_probe(struct platform_device *pdev)
stratix10_svc_free_channel(priv->chan);
}
ret = rsu_send_msg(priv, COMMAND_RSU_DCMF_STATUS,
0, rsu_dcmf_status_callback);
if (ret) {
dev_err(dev, "Error, getting DCMF status %i\n", ret);
stratix10_svc_free_channel(priv->chan);
}
ret = rsu_send_msg(priv, COMMAND_RSU_RETRY, 0, rsu_retry_callback);
if (ret) {
dev_err(dev, "Error, getting RSU retry %i\n", ret);

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