PCI: dwc: Split MSI IRQ parsing/allocation to a separate function
Split handling of MSI host IRQs to a separate dw_pcie_msi_host_init() function. The code is complex enough to warrant a separate function. [bhelgaas: reorder patch earlier] Link: https://lore.kernel.org/r/20220707134733.2436629-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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@ -286,6 +286,58 @@ static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
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dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
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}
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static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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struct platform_device *pdev = to_platform_device(dev);
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int ret;
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u32 ctrl, num_ctrls;
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num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
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for (ctrl = 0; ctrl < num_ctrls; ctrl++)
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pp->irq_mask[ctrl] = ~0;
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if (!pp->msi_irq) {
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pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
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if (pp->msi_irq < 0) {
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pp->msi_irq = platform_get_irq(pdev, 0);
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if (pp->msi_irq < 0)
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return pp->msi_irq;
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}
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}
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pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
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ret = dw_pcie_allocate_domains(pp);
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if (ret)
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return ret;
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if (pp->msi_irq > 0)
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irq_set_chained_handler_and_data(pp->msi_irq,
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dw_chained_msi_isr, pp);
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ret = dma_set_mask(dev, DMA_BIT_MASK(32));
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if (ret)
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dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
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pp->msi_page = alloc_page(GFP_DMA32);
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pp->msi_data = dma_map_page(dev, pp->msi_page, 0,
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PAGE_SIZE, DMA_FROM_DEVICE);
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ret = dma_mapping_error(dev, pp->msi_data);
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if (ret) {
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dev_err(pci->dev, "Failed to map MSI data\n");
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__free_page(pp->msi_page);
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pp->msi_page = NULL;
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pp->msi_data = 0;
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dw_pcie_free_msi(pp);
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return ret;
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}
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return 0;
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}
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int dw_pcie_host_init(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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@ -364,49 +416,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
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if (ret < 0)
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goto err_deinit_host;
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} else if (pp->has_msi_ctrl) {
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u32 ctrl, num_ctrls;
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num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
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for (ctrl = 0; ctrl < num_ctrls; ctrl++)
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pp->irq_mask[ctrl] = ~0;
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if (!pp->msi_irq) {
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pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
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if (pp->msi_irq < 0) {
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pp->msi_irq = platform_get_irq(pdev, 0);
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if (pp->msi_irq < 0) {
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ret = pp->msi_irq;
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goto err_deinit_host;
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}
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}
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}
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pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
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ret = dw_pcie_allocate_domains(pp);
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if (ret)
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ret = dw_pcie_msi_host_init(pp);
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if (ret < 0)
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goto err_deinit_host;
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if (pp->msi_irq > 0)
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irq_set_chained_handler_and_data(pp->msi_irq,
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dw_chained_msi_isr,
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pp);
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ret = dma_set_mask(dev, DMA_BIT_MASK(32));
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if (ret)
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dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
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pp->msi_page = alloc_page(GFP_DMA32);
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pp->msi_data = dma_map_page(dev, pp->msi_page, 0,
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PAGE_SIZE, DMA_FROM_DEVICE);
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ret = dma_mapping_error(dev, pp->msi_data);
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if (ret) {
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dev_err(pci->dev, "Failed to map MSI data\n");
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__free_page(pp->msi_page);
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pp->msi_page = NULL;
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pp->msi_data = 0;
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goto err_free_msi;
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}
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}
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}
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