arm64: dts: renesas: Add CPU capacity-dmips-mhz
Set the capacity-dmips-mhz for R-Car Gen3 SoCs, that is based on dhrystone. The average in 10 times of dhrystone result as follows: r8a7795 SoC (A57x4 + A53x4) CPU max-freq dhrystone --------------------------------- A57 1500 MHz 11470943 lps/s A53 1200 MHz 4798583 lps/s r8a7796 SoC (A57x2 + A53x4) CPU max-freq dhrystone --------------------------------- A57 1500 MHz 11463526 lps/s A53 1200 MHz 4793276 lps/s Based on above, capacity-dmips-mhz values are calculated as follows: r8a7795 SoC A57 : 1024 / (11470943 / 1500) * (11470943 / 1500) = 1024 A53 : 1024 / (11470943 / 1500) * ( 4798583 / 1200) = 535 r8a7796 SoC A57 : 1024 / (11463526 / 1500) * (11463526 / 1500) = 1024 A53 : 1024 / (11463526 / 1500) * ( 4793276 / 1200) = 535 However, since each CPUs have different max frequencies, the final CPU capacities of A53 are scaled by this difference, the values are as follows. [r8a7795 SoC] $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 <---- CPU capacity of A57 1024 1024 1024 428 <---- CPU capacity of A53 428 428 428 [r8a7796 SoC] $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 <---- CPU capacity of A57 1024 428 <---- CPU capacity of A53 428 428 428 Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -157,6 +157,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
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operating-points-v2 = <&cluster0_opp>;
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capacity-dmips-mhz = <1024>;
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#cooling-cells = <2>;
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};
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@ -169,6 +170,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
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operating-points-v2 = <&cluster0_opp>;
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capacity-dmips-mhz = <1024>;
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#cooling-cells = <2>;
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};
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@ -181,6 +183,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
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operating-points-v2 = <&cluster0_opp>;
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capacity-dmips-mhz = <1024>;
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#cooling-cells = <2>;
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};
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@ -193,6 +196,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
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operating-points-v2 = <&cluster0_opp>;
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capacity-dmips-mhz = <1024>;
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#cooling-cells = <2>;
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};
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@ -205,6 +209,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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capacity-dmips-mhz = <535>;
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};
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a53_1: cpu@101 {
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@ -216,6 +221,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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capacity-dmips-mhz = <535>;
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};
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a53_2: cpu@102 {
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@ -227,6 +233,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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capacity-dmips-mhz = <535>;
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};
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a53_3: cpu@103 {
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@ -238,6 +245,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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capacity-dmips-mhz = <535>;
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};
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L2_CA57: cache-controller-0 {
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@ -162,6 +162,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
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operating-points-v2 = <&cluster0_opp>;
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capacity-dmips-mhz = <1024>;
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#cooling-cells = <2>;
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};
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@ -174,6 +175,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
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operating-points-v2 = <&cluster0_opp>;
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capacity-dmips-mhz = <1024>;
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#cooling-cells = <2>;
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};
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@ -186,6 +188,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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capacity-dmips-mhz = <535>;
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};
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a53_1: cpu@101 {
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@ -197,6 +200,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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capacity-dmips-mhz = <535>;
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};
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a53_2: cpu@102 {
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@ -208,6 +212,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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capacity-dmips-mhz = <535>;
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};
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a53_3: cpu@103 {
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@ -219,6 +224,7 @@
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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capacity-dmips-mhz = <535>;
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};
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L2_CA57: cache-controller-0 {
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