drm/amdgpu: implement jpeg ring functions
Implement all ring functions needed for jpeg ring v2: remove unnecessary mem read function. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Boyuan Zhang
Alex Deucher
parent
50613395ab
commit
221f36c460
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@ -1126,6 +1126,292 @@ static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, val);
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amdgpu_ring_write(ring, val);
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}
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}
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/**
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* vcn_v1_0_jpeg_ring_get_rptr - get read pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware read pointer
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*/
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static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
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}
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/**
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* vcn_v1_0_jpeg_ring_get_wptr - get write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware write pointer
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*/
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static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
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}
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/**
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* vcn_v1_0_jpeg_ring_set_wptr - set write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Commits the write pointer to the hardware
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*/
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static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
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}
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/**
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* vcn_v1_0_jpeg_ring_insert_start - insert a start command
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*
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* @ring: amdgpu_ring pointer
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*
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* Write a start command to the ring.
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*/
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static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, 0x68e04);
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amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, 0x80010000);
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}
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/**
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* vcn_v1_0_jpeg_ring_insert_end - insert a end command
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*
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* @ring: amdgpu_ring pointer
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*
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* Write a end command to the ring.
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*/
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static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, 0x68e04);
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amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, 0x00010000);
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}
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/**
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* vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command
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*
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* @ring: amdgpu_ring pointer
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* @fence: fence to emit
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*
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* Write a fence and a trap command to the ring.
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*/
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static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
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unsigned flags)
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{
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struct amdgpu_device *adev = ring->adev;
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WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, seq);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, seq);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, lower_32_bits(addr));
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, upper_32_bits(addr));
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, 0x8);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, 0x01400200);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, seq);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, lower_32_bits(addr));
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, upper_32_bits(addr));
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amdgpu_ring_write(ring,
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PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));
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amdgpu_ring_write(ring, 0xffffffff);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, 0x3fbc);
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amdgpu_ring_write(ring,
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PACKETJ(0, 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, 0x1);
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}
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/**
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* vcn_v1_0_jpeg_ring_emit_ib - execute indirect buffer
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*
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* @ring: amdgpu_ring pointer
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* @ib: indirect buffer to execute
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*
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* Write ring commands to execute the indirect buffer.
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*/
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static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
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struct amdgpu_ib *ib,
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unsigned vmid, bool ctx_switch)
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{
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struct amdgpu_device *adev = ring->adev;
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, (vmid | (vmid << 4)));
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, (vmid | (vmid << 4)));
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, ib->length_dw);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
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amdgpu_ring_write(ring,
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PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, 0x01400200);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, 0x2);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
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amdgpu_ring_write(ring, 0x2);
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}
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static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,
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uint32_t reg, uint32_t val,
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uint32_t mask)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t reg_offset = (reg << 2);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, 0x01400200);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
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amdgpu_ring_write(ring, val);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
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if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
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((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring,
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PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
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} else {
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amdgpu_ring_write(ring, reg_offset);
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amdgpu_ring_write(ring,
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PACKETJ(0, 0, 0, PACKETJ_TYPE3));
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}
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amdgpu_ring_write(ring, mask);
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}
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static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned vmid, uint64_t pd_addr)
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{
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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uint32_t data0, data1, mask;
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pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
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/* wait for register write */
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data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
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data1 = lower_32_bits(pd_addr);
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mask = 0xffffffff;
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vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
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}
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static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,
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uint32_t reg, uint32_t val)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t reg_offset = (reg << 2);
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amdgpu_ring_write(ring,
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PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
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if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
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((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring,
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PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
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} else {
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amdgpu_ring_write(ring, reg_offset);
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amdgpu_ring_write(ring,
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PACKETJ(0, 0, 0, PACKETJ_TYPE0));
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}
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amdgpu_ring_write(ring, val);
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}
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static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
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{
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int i;
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WARN_ON(ring->wptr % 2 || count % 2);
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for (i = 0; i < count / 2; i++) {
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amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
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amdgpu_ring_write(ring, 0);
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}
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}
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static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
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static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_irq_src *source,
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unsigned type,
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unsigned type,
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