drm/amd/display: Add DCN3 IRQ
Add IWQ services for DCN3, This allows us to create/init and manage irqs for DCN3 Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Bhawanpreet Lakha
Alex Deucher
parent
6725a88f88
commit
21f4809ae4
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@ -83,3 +83,13 @@ AMD_DAL_IRQ_DCN21= $(addprefix $(AMDDALPATH)/dc/irq/dcn21/,$(IRQ_DCN21))
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AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN21)
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endif
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###############################################################################
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# DCN 30
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###############################################################################
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ifdef CONFIG_DRM_AMD_DC_DCN3_0
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IRQ_DCN3 = irq_service_dcn30.o
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AMD_DAL_IRQ_DCN3 = $(addprefix $(AMDDALPATH)/dc/irq/dcn30/,$(IRQ_DCN3))
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AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN3)
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endif
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@ -0,0 +1,384 @@
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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#include "dm_services.h"
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#include "include/logger_interface.h"
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#include "../dce110/irq_service_dce110.h"
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#include "sienna_cichlid_ip_offset.h"
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#include "dcn/dcn_3_0_0_offset.h"
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#include "dcn/dcn_3_0_0_sh_mask.h"
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#include "nbio/nbio_7_4_offset.h"
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#include "dcn/dpcs_3_0_0_offset.h"
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#include "dcn/dpcs_3_0_0_sh_mask.h"
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#include "mmhub/mmhub_2_0_0_offset.h"
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#include "mmhub/mmhub_2_0_0_sh_mask.h"
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#include "irq_service_dcn30.h"
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#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
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enum dc_irq_source to_dal_irq_source_dcn30(
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struct irq_service *irq_service,
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uint32_t src_id,
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uint32_t ext_id)
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{
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switch (src_id) {
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case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
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return DC_IRQ_SOURCE_VBLANK1;
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case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
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return DC_IRQ_SOURCE_VBLANK2;
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case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
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return DC_IRQ_SOURCE_VBLANK3;
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case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
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return DC_IRQ_SOURCE_VBLANK4;
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case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
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return DC_IRQ_SOURCE_VBLANK5;
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case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
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return DC_IRQ_SOURCE_VBLANK6;
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case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
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return DC_IRQ_SOURCE_PFLIP1;
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case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
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return DC_IRQ_SOURCE_PFLIP2;
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case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
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return DC_IRQ_SOURCE_PFLIP3;
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case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
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return DC_IRQ_SOURCE_PFLIP4;
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case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
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return DC_IRQ_SOURCE_PFLIP5;
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case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
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return DC_IRQ_SOURCE_PFLIP6;
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case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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return DC_IRQ_SOURCE_VUPDATE1;
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case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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return DC_IRQ_SOURCE_VUPDATE2;
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case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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return DC_IRQ_SOURCE_VUPDATE3;
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case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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return DC_IRQ_SOURCE_VUPDATE4;
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case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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return DC_IRQ_SOURCE_VUPDATE5;
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case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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return DC_IRQ_SOURCE_VUPDATE6;
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case DCN_1_0__SRCID__DC_HPD1_INT:
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/* generic src_id for all HPD and HPDRX interrupts */
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switch (ext_id) {
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case DCN_1_0__CTXID__DC_HPD1_INT:
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return DC_IRQ_SOURCE_HPD1;
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case DCN_1_0__CTXID__DC_HPD2_INT:
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return DC_IRQ_SOURCE_HPD2;
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case DCN_1_0__CTXID__DC_HPD3_INT:
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return DC_IRQ_SOURCE_HPD3;
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case DCN_1_0__CTXID__DC_HPD4_INT:
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return DC_IRQ_SOURCE_HPD4;
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case DCN_1_0__CTXID__DC_HPD5_INT:
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return DC_IRQ_SOURCE_HPD5;
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case DCN_1_0__CTXID__DC_HPD6_INT:
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return DC_IRQ_SOURCE_HPD6;
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case DCN_1_0__CTXID__DC_HPD1_RX_INT:
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return DC_IRQ_SOURCE_HPD1RX;
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case DCN_1_0__CTXID__DC_HPD2_RX_INT:
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return DC_IRQ_SOURCE_HPD2RX;
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case DCN_1_0__CTXID__DC_HPD3_RX_INT:
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return DC_IRQ_SOURCE_HPD3RX;
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case DCN_1_0__CTXID__DC_HPD4_RX_INT:
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return DC_IRQ_SOURCE_HPD4RX;
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case DCN_1_0__CTXID__DC_HPD5_RX_INT:
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return DC_IRQ_SOURCE_HPD5RX;
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case DCN_1_0__CTXID__DC_HPD6_RX_INT:
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return DC_IRQ_SOURCE_HPD6RX;
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default:
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return DC_IRQ_SOURCE_INVALID;
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}
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break;
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default:
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return DC_IRQ_SOURCE_INVALID;
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}
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}
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static bool hpd_ack(
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struct irq_service *irq_service,
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const struct irq_source_info *info)
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{
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uint32_t addr = info->status_reg;
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uint32_t value = dm_read_reg(irq_service->ctx, addr);
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uint32_t current_status =
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get_reg_field_value(
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value,
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HPD0_DC_HPD_INT_STATUS,
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DC_HPD_SENSE_DELAYED);
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dal_irq_service_ack_generic(irq_service, info);
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value = dm_read_reg(irq_service->ctx, info->enable_reg);
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set_reg_field_value(
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value,
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current_status ? 0 : 1,
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HPD0_DC_HPD_INT_CONTROL,
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DC_HPD_INT_POLARITY);
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dm_write_reg(irq_service->ctx, info->enable_reg, value);
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return true;
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}
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static const struct irq_source_info_funcs hpd_irq_info_funcs = {
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.set = NULL,
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.ack = hpd_ack
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};
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static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
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.set = NULL,
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.ack = NULL
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};
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static const struct irq_source_info_funcs pflip_irq_info_funcs = {
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.set = NULL,
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.ack = NULL
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};
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static const struct irq_source_info_funcs vblank_irq_info_funcs = {
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.set = NULL,
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.ack = NULL
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};
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#undef BASE_INNER
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#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
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/* compile time expand base address. */
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#define BASE(seg) \
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BASE_INNER(seg)
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#define SRI(reg_name, block, id)\
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BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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mm ## block ## id ## _ ## reg_name
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#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
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.enable_reg = SRI(reg1, block, reg_num),\
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.enable_mask = \
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block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
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.enable_value = {\
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block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
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~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
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},\
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.ack_reg = SRI(reg2, block, reg_num),\
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.ack_mask = \
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block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
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.ack_value = \
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block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
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#define hpd_int_entry(reg_num)\
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[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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IRQ_REG_ENTRY(HPD, reg_num,\
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DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
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DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
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.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
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.funcs = &hpd_irq_info_funcs\
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}
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#define hpd_rx_int_entry(reg_num)\
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[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
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IRQ_REG_ENTRY(HPD, reg_num,\
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DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
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DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
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.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
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.funcs = &hpd_rx_irq_info_funcs\
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}
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#define pflip_int_entry(reg_num)\
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[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
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IRQ_REG_ENTRY(HUBPREQ, reg_num,\
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DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
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DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
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.funcs = &pflip_irq_info_funcs\
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}
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#define vupdate_int_entry(reg_num)\
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[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
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IRQ_REG_ENTRY(OTG, reg_num,\
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OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
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OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
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.funcs = &vblank_irq_info_funcs\
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}
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#define vblank_int_entry(reg_num)\
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[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
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IRQ_REG_ENTRY(OTG, reg_num,\
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OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
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OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
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.funcs = &vblank_irq_info_funcs\
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}
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#define dummy_irq_entry() \
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{\
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.funcs = &dummy_irq_info_funcs\
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}
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#define i2c_int_entry(reg_num) \
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[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
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#define dp_sink_int_entry(reg_num) \
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[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
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#define gpio_pad_int_entry(reg_num) \
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[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
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#define dc_underflow_int_entry(reg_num) \
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[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
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static const struct irq_source_info_funcs dummy_irq_info_funcs = {
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.set = dal_irq_service_dummy_set,
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.ack = dal_irq_service_dummy_ack
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};
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static const struct irq_source_info
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irq_source_info_dcn30[DAL_IRQ_SOURCES_NUMBER] = {
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[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
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hpd_int_entry(0),
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hpd_int_entry(1),
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hpd_int_entry(2),
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hpd_int_entry(3),
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hpd_int_entry(4),
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hpd_int_entry(5),
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hpd_rx_int_entry(0),
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hpd_rx_int_entry(1),
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hpd_rx_int_entry(2),
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hpd_rx_int_entry(3),
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hpd_rx_int_entry(4),
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hpd_rx_int_entry(5),
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i2c_int_entry(1),
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i2c_int_entry(2),
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i2c_int_entry(3),
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i2c_int_entry(4),
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i2c_int_entry(5),
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i2c_int_entry(6),
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dp_sink_int_entry(1),
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dp_sink_int_entry(2),
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dp_sink_int_entry(3),
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dp_sink_int_entry(4),
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dp_sink_int_entry(5),
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dp_sink_int_entry(6),
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[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
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pflip_int_entry(0),
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pflip_int_entry(1),
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pflip_int_entry(2),
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pflip_int_entry(3),
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[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
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[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
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[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
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gpio_pad_int_entry(0),
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gpio_pad_int_entry(1),
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gpio_pad_int_entry(2),
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gpio_pad_int_entry(3),
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gpio_pad_int_entry(4),
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gpio_pad_int_entry(5),
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gpio_pad_int_entry(6),
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gpio_pad_int_entry(7),
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gpio_pad_int_entry(8),
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gpio_pad_int_entry(9),
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gpio_pad_int_entry(10),
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gpio_pad_int_entry(11),
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gpio_pad_int_entry(12),
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gpio_pad_int_entry(13),
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gpio_pad_int_entry(14),
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gpio_pad_int_entry(15),
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gpio_pad_int_entry(16),
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gpio_pad_int_entry(17),
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gpio_pad_int_entry(18),
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gpio_pad_int_entry(19),
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gpio_pad_int_entry(20),
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gpio_pad_int_entry(21),
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gpio_pad_int_entry(22),
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gpio_pad_int_entry(23),
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gpio_pad_int_entry(24),
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gpio_pad_int_entry(25),
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gpio_pad_int_entry(26),
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gpio_pad_int_entry(27),
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gpio_pad_int_entry(28),
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gpio_pad_int_entry(29),
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gpio_pad_int_entry(30),
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dc_underflow_int_entry(1),
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dc_underflow_int_entry(2),
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dc_underflow_int_entry(3),
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dc_underflow_int_entry(4),
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dc_underflow_int_entry(5),
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dc_underflow_int_entry(6),
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[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
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[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
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vupdate_int_entry(0),
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vupdate_int_entry(1),
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vupdate_int_entry(2),
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vupdate_int_entry(3),
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vupdate_int_entry(4),
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vupdate_int_entry(5),
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vblank_int_entry(0),
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vblank_int_entry(1),
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vblank_int_entry(2),
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vblank_int_entry(3),
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vblank_int_entry(4),
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vblank_int_entry(5),
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};
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static const struct irq_service_funcs irq_service_funcs_dcn30 = {
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.to_dal_irq_source = to_dal_irq_source_dcn30
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};
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static void dcn30_irq_construct(
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struct irq_service *irq_service,
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struct irq_service_init_data *init_data)
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{
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dal_irq_service_construct(irq_service, init_data);
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irq_service->info = irq_source_info_dcn30;
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irq_service->funcs = &irq_service_funcs_dcn30;
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}
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struct irq_service *dal_irq_service_dcn30_create(
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struct irq_service_init_data *init_data)
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{
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struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
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GFP_KERNEL);
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if (!irq_service)
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return NULL;
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dcn30_irq_construct(irq_service, init_data);
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return irq_service;
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}
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#endif
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@ -0,0 +1,37 @@
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
|
||||
|
||||
#ifndef __DAL_IRQ_SERVICE_DCN30_H__
|
||||
#define __DAL_IRQ_SERVICE_DCN30_H__
|
||||
|
||||
#include "../irq_service.h"
|
||||
|
||||
struct irq_service *dal_irq_service_dcn30_create(
|
||||
struct irq_service_init_data *init_data);
|
||||
|
||||
#endif /* __DAL_IRQ_SERVICE_DCN30_H__ */
|
||||
#endif
|
||||
Loading…
Reference in New Issue