STi DT update:
- various DT fixes to avoid warnings when build with W=1 - DT clean-up -----BEGIN PGP SIGNATURE----- iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmIL4PwcHHBhdHJpY2Uu Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/pj9bD/9WrEqvCqp/j2/VZ7qJ WJgMj5SpMJl0xYn5Audq2sKzNXitoRQx4U8Oarlq059hWd5XzS1dQ9cNXp4jHiZC mejayjOZC2A3+xzR5PXL4Ap9VV6WAQcZS8wuMcJwyqjId0agigQFCUhzBkbk2nJI WJ40ls+X5C11tM5SWGbeVGf+nFRjPcGIHX6cxBCnMpGemtYxRir7xgt0YiCGeP+0 VfZ5xusQdbCMtP/Dv5AJgG8vGoldcLnpb5Ay/FSjttro/mWdf/lm4P9HcFYYkWyY vq9tQLCNxjNdtnIERQrAIb8uF7llz56ImgiUUbOwcN8Ho4im1jNyuDff7yxDIYSs 2PumhS+uvFqwJOi8UdIxLPfW1iziWXvfR6opsCsc2nsBkuxYgo2r8M2KC4mOK7Yf 0dwu6amvK/1JGG0xe3F+v3iDsKBcJtHS1MXs+W7wjpXXdpowFzthbVqW51MRhNLa E4TgxwDxrLJ7UgDSWtuWU5PwMKE+qTdxCufulfusHUzAg8aIrGRJbbnA3iy2+oaV nWBcym6jsydgZ6QfQjM+8LjmNIItx4CRrCnhCSvhGgd0YZIHrq/S+hkvISDCSAqm GoFKZOmO2irBivmQ7O+12btC7ZARmxKFmOHiIqKbUofSGVeg6MmQaBBiVG0GP+ui Thi70LMN8T5Vt4v1UIJVrQrfow== =m2Yv -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY6g8ACgkQmmx57+YA GNm3Jg//VDW9lYF/Z7DzPGHHvylTZwCeERAsUtFbIVch10+bPfHBNQqgfzGUvilo MHk8Zy1SAGJeLYuRg1LEceA1iAVEZkPIWMCDAmEFJGakxct9K/qEoV/m7xAINSvG nAnKyKO5yj6xoe5P/jftkosjL9dRCynyXFw0PbGBi6LEzKWsYatmEyg4ko9EFnj1 rncJRBTn6NBa2IqWTpDGFNTY6UdZFRZWyV23zXaXVEF0NCWkRJWaROZ04OGbBB2K QXWMZsazg+gAlcj0Z4gecRMRw8XGBxDvgWpHFKsbKQsv/uv7Ia2gbjDjDYtyt/8W FtL/Hz/jNE4MOGF4utd3QwInHIJypxtnIJktjWXhBCEpHQ3WdEQIR5Qf0TxEiDsx MWBqe+0NvgWjpZsPQT6eC2Y6oQN097gv1Eh2Gn2JD33rOy6oqwObe4nWpmL5VoTQ awovYAmBVulGHBj/kKK/KerfwldonrQuCzCTznQXpA21U4a1OLVjAadHsEFUudh3 YWEfhFz82UeaQES5hwK6oTD5UphLGN2UG7+IJ5olFNEar62SCodvkJUModXPnssU vcMtAYpScWW0nz1VP94ah7StIAn79aSXnRehU5lmSPAxA7fHPQAzhfzgPHibDQ4S zIaMuvzjN48Kdn5EbAPx/iiZUR39elsYKbSNld1RwijODqjorwI= =UUck -----END PGP SIGNATURE----- Merge tag 'sti-dt-for-v5.18-round1' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into arm/dt STi DT update: - various DT fixes to avoid warnings when build with W=1 - DT clean-up Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
21ed2f61cc
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@ -29,7 +29,7 @@
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*/
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clockgen-a9@92b0000 {
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compatible = "st,clkgen-c32";
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reg = <0x92b0000 0xffff>;
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reg = <0x92b0000 0x10000>;
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clockgen_a9_pll: clockgen-a9-pll {
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#clock-cells = <1>;
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@ -37,32 +37,27 @@
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clocks = <&clk_sysin>;
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};
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};
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/*
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* ARM CPU related clocks.
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*/
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clk_m_a9: clk-m-a9@92b0000 {
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#clock-cells = <0>;
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compatible = "st,stih407-clkgen-a9-mux";
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reg = <0x92b0000 0x10000>;
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clocks = <&clockgen_a9_pll 0>,
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<&clockgen_a9_pll 0>,
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<&clk_s_c0_flexgen 13>,
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<&clk_m_a9_ext2f_div2>;
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: clk-m-a9-periphs {
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clk_m_a9: clk-m-a9 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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compatible = "st,stih407-clkgen-a9-mux";
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clocks = <&clk_m_a9>;
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&clockgen_a9_pll 0>,
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<&clockgen_a9_pll 0>,
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<&clk_s_c0_flexgen 13>,
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<&clk_m_a9_ext2f_div2>;
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: clk-m-a9-periphs {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_m_a9>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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};
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@ -87,14 +82,6 @@
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};
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};
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clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
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#clock-cells = <1>;
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compatible = "st,quadfs-pll";
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reg = <0x9103000 0x1000>;
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clocks = <&clk_sysin>;
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};
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clk_s_c0: clockgen-c@9103000 {
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compatible = "st,clkgen-c32";
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reg = <0x9103000 0x1000>;
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@ -113,6 +100,13 @@
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clocks = <&clk_sysin>;
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};
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clk_s_c0_quadfs: clk-s-c0-quadfs {
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#clock-cells = <1>;
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compatible = "st,quadfs-pll";
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clocks = <&clk_sysin>;
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};
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clk_s_c0_flexgen: clk-s-c0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen", "st,flexgen-stih407-c0";
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@ -142,18 +136,17 @@
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};
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};
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clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
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#clock-cells = <1>;
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compatible = "st,quadfs-d0";
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reg = <0x9104000 0x1000>;
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clocks = <&clk_sysin>;
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};
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clockgen-d0@9104000 {
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compatible = "st,clkgen-c32";
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reg = <0x9104000 0x1000>;
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clk_s_d0_quadfs: clk-s-d0-quadfs {
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#clock-cells = <1>;
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compatible = "st,quadfs-d0";
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clocks = <&clk_sysin>;
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};
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clk_s_d0_flexgen: clk-s-d0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen", "st,flexgen-stih407-d0";
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@ -166,18 +159,17 @@
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};
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};
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clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
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#clock-cells = <1>;
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compatible = "st,quadfs-d2";
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reg = <0x9106000 0x1000>;
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clocks = <&clk_sysin>;
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};
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clockgen-d2@9106000 {
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compatible = "st,clkgen-c32";
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reg = <0x9106000 0x1000>;
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clk_s_d2_quadfs: clk-s-d2-quadfs {
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#clock-cells = <1>;
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compatible = "st,quadfs-d2";
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clocks = <&clk_sysin>;
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};
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clk_s_d2_flexgen: clk-s-d2-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen", "st,flexgen-stih407-d2";
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@ -192,18 +184,17 @@
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};
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};
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clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
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#clock-cells = <1>;
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compatible = "st,quadfs-d3";
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reg = <0x9107000 0x1000>;
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clocks = <&clk_sysin>;
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};
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clockgen-d3@9107000 {
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compatible = "st,clkgen-c32";
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reg = <0x9107000 0x1000>;
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clk_s_d3_quadfs: clk-s-d3-quadfs {
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#clock-cells = <1>;
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compatible = "st,quadfs-d3";
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clocks = <&clk_sysin>;
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};
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clk_s_d3_flexgen: clk-s-d3-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen", "st,flexgen-stih407-d3";
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@ -115,6 +115,134 @@
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status = "okay";
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};
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restart: restart-controller {
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compatible = "st,stih407-restart";
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st,syscfg = <&syscfg_sbc_reg>;
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status = "okay";
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};
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powerdown: powerdown-controller {
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compatible = "st,stih407-powerdown";
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#reset-cells = <1>;
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};
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softreset: softreset-controller {
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compatible = "st,stih407-softreset";
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#reset-cells = <1>;
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};
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picophyreset: picophyreset-controller {
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compatible = "st,stih407-picophyreset";
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#reset-cells = <1>;
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};
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irq-syscfg {
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compatible = "st,stih407-irq-syscfg";
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st,syscfg = <&syscfg_core>;
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st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
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<ST_IRQ_SYSCFG_PMU_1>;
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st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
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<ST_IRQ_SYSCFG_DISABLED>;
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};
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usb2_picophy0: phy1 {
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compatible = "st,stih407-usb2-phy";
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0x100 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY2_RESET>;
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reset-names = "global", "port";
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};
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miphy28lp_phy: miphy28lp {
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compatible = "st,miphy28lp-phy";
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st,syscfg = <&syscfg_core>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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phy_port0: port@9b22000 {
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reg = <0x9b22000 0xff>,
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<0x9b09000 0xff>,
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<0x9b04000 0xff>;
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reg-names = "sata-up",
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"pcie-up",
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"pipew";
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st,syscfg = <0x114 0x818 0xe0 0xec>;
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#phy-cells = <1>;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
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};
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phy_port1: port@9b2a000 {
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reg = <0x9b2a000 0xff>,
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<0x9b19000 0xff>,
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<0x9b14000 0xff>;
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reg-names = "sata-up",
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"pcie-up",
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"pipew";
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st,syscfg = <0x118 0x81c 0xe4 0xf0>;
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#phy-cells = <1>;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
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};
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phy_port2: port@8f95000 {
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reg = <0x8f95000 0xff>,
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<0x8f90000 0xff>;
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reg-names = "pipew",
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"usb3-up";
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st,syscfg = <0x11c 0x820>;
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#phy-cells = <1>;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
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};
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};
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st231_gp0: st231-gp0 {
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compatible = "st,st231-rproc";
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memory-region = <&gp0_reserved>;
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resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
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reset-names = "sw_reset";
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clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
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clock-frequency = <600000000>;
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st,syscfg = <&syscfg_core 0x22c>;
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#mbox-cells = <1>;
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mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
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mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
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};
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st231_delta: st231-delta {
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compatible = "st,st231-rproc";
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memory-region = <&delta_reserved>;
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resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
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reset-names = "sw_reset";
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clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
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clock-frequency = <600000000>;
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st,syscfg = <&syscfg_core 0x224>;
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#mbox-cells = <1>;
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mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
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mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
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};
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delta0 {
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compatible = "st,st-delta";
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clock-names = "delta",
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"delta-st231",
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"delta-flash-promip";
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clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
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<&clk_s_c0_flexgen CLK_ST231_DMU>,
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<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -122,31 +250,6 @@
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ranges;
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compatible = "simple-bus";
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restart: restart-controller@0 {
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compatible = "st,stih407-restart";
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reg = <0 0>;
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st,syscfg = <&syscfg_sbc_reg>;
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status = "okay";
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};
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powerdown: powerdown-controller@0 {
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compatible = "st,stih407-powerdown";
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reg = <0 0>;
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#reset-cells = <1>;
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};
|
||||
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softreset: softreset-controller@0 {
|
||||
compatible = "st,stih407-softreset";
|
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reg = <0 0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
picophyreset: picophyreset-controller@0 {
|
||||
compatible = "st,stih407-picophyreset";
|
||||
reg = <0 0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
syscfg_sbc: sbc-syscfg@9620000 {
|
||||
compatible = "st,stih407-sbc-syscfg", "syscon";
|
||||
reg = <0x9620000 0x1000>;
|
||||
|
|
@ -189,16 +292,6 @@
|
|||
reg = <0x94b5100 0x1000>;
|
||||
};
|
||||
|
||||
irq-syscfg@0 {
|
||||
compatible = "st,stih407-irq-syscfg";
|
||||
reg = <0 0>;
|
||||
st,syscfg = <&syscfg_core>;
|
||||
st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
|
||||
<ST_IRQ_SYSCFG_PMU_1>;
|
||||
st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
|
||||
<ST_IRQ_SYSCFG_DISABLED>;
|
||||
};
|
||||
|
||||
/* Display */
|
||||
vtg_main: sti-vtg-main@8d02800 {
|
||||
compatible = "st,vtg";
|
||||
|
|
@ -389,70 +482,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_picophy0: phy1@0 {
|
||||
compatible = "st,stih407-usb2-phy";
|
||||
reg = <0 0>;
|
||||
#phy-cells = <0>;
|
||||
st,syscfg = <&syscfg_core 0x100 0xf4>;
|
||||
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
|
||||
<&picophyreset STIH407_PICOPHY2_RESET>;
|
||||
reset-names = "global", "port";
|
||||
};
|
||||
|
||||
miphy28lp_phy: miphy28lp@0 {
|
||||
compatible = "st,miphy28lp-phy";
|
||||
st,syscfg = <&syscfg_core>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
reg = <0 0>;
|
||||
|
||||
phy_port0: port@9b22000 {
|
||||
reg = <0x9b22000 0xff>,
|
||||
<0x9b09000 0xff>,
|
||||
<0x9b04000 0xff>;
|
||||
reg-names = "sata-up",
|
||||
"pcie-up",
|
||||
"pipew";
|
||||
|
||||
st,syscfg = <0x114 0x818 0xe0 0xec>;
|
||||
#phy-cells = <1>;
|
||||
|
||||
reset-names = "miphy-sw-rst";
|
||||
resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
|
||||
};
|
||||
|
||||
phy_port1: port@9b2a000 {
|
||||
reg = <0x9b2a000 0xff>,
|
||||
<0x9b19000 0xff>,
|
||||
<0x9b14000 0xff>;
|
||||
reg-names = "sata-up",
|
||||
"pcie-up",
|
||||
"pipew";
|
||||
|
||||
st,syscfg = <0x118 0x81c 0xe4 0xf0>;
|
||||
|
||||
#phy-cells = <1>;
|
||||
|
||||
reset-names = "miphy-sw-rst";
|
||||
resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
|
||||
};
|
||||
|
||||
phy_port2: port@8f95000 {
|
||||
reg = <0x8f95000 0xff>,
|
||||
<0x8f90000 0xff>;
|
||||
reg-names = "pipew",
|
||||
"usb3-up";
|
||||
|
||||
st,syscfg = <0x11c 0x820>;
|
||||
|
||||
#phy-cells = <1>;
|
||||
|
||||
reset-names = "miphy-sw-rst";
|
||||
resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@9840000 {
|
||||
compatible = "st,comms-ssc4-spi";
|
||||
reg = <0x9840000 0x110>;
|
||||
|
|
@ -815,34 +844,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
st231_gp0: st231-gp0@0 {
|
||||
compatible = "st,st231-rproc";
|
||||
reg = <0 0>;
|
||||
memory-region = <&gp0_reserved>;
|
||||
resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
|
||||
reset-names = "sw_reset";
|
||||
clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
|
||||
clock-frequency = <600000000>;
|
||||
st,syscfg = <&syscfg_core 0x22c>;
|
||||
#mbox-cells = <1>;
|
||||
mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
|
||||
mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
|
||||
};
|
||||
|
||||
st231_delta: st231-delta@0 {
|
||||
compatible = "st,st231-rproc";
|
||||
reg = <0 0>;
|
||||
memory-region = <&delta_reserved>;
|
||||
resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
|
||||
reset-names = "sw_reset";
|
||||
clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
|
||||
clock-frequency = <600000000>;
|
||||
st,syscfg = <&syscfg_core 0x224>;
|
||||
#mbox-cells = <1>;
|
||||
mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
|
||||
mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
|
||||
};
|
||||
|
||||
/* fdma audio */
|
||||
fdma0: dma-controller@8e20000 {
|
||||
compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
|
||||
|
|
@ -986,16 +987,5 @@
|
|||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
delta0@0 {
|
||||
compatible = "st,st-delta";
|
||||
reg = <0 0>;
|
||||
clock-names = "delta",
|
||||
"delta-st231",
|
||||
"delta-flash-promip";
|
||||
clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
|
||||
<&clk_s_c0_flexgen CLK_ST231_DMU>,
|
||||
<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -24,6 +24,14 @@
|
|||
ethernet0 = ðernet0;
|
||||
};
|
||||
|
||||
usb2_picophy1: phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2_picophy2: phy3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
soc {
|
||||
|
||||
mmc0: sdhci@9060000 {
|
||||
|
|
@ -33,14 +41,6 @@
|
|||
sd-uhs-ddr50;
|
||||
};
|
||||
|
||||
usb2_picophy1: phy2@0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2_picophy2: phy3@0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ohci0: usb@9a03c00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -75,6 +75,21 @@
|
|||
};
|
||||
};
|
||||
|
||||
miphy28lp_phy: miphy28lp {
|
||||
|
||||
phy_port1: port@9b2a000 {
|
||||
st,osc-force-ext;
|
||||
};
|
||||
};
|
||||
|
||||
usb2_picophy1: phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2_picophy2: phy3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
soc {
|
||||
/* Low speed expansion connector */
|
||||
uart0: serial@9830000 {
|
||||
|
|
@ -145,14 +160,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
usb2_picophy1: phy2@0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2_picophy2: phy3@0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ohci0: usb@9a03c00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -196,13 +203,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
miphy28lp_phy: miphy28lp@0 {
|
||||
|
||||
phy_port1: port@9b2a000 {
|
||||
st,osc-force-ext;
|
||||
};
|
||||
};
|
||||
|
||||
sata1: sata@9b28000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@
|
|||
*/
|
||||
clockgen-a9@92b0000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x92b0000 0xffff>;
|
||||
reg = <0x92b0000 0x10000>;
|
||||
|
||||
clockgen_a9_pll: clockgen-a9-pll {
|
||||
#clock-cells = <1>;
|
||||
|
|
@ -40,29 +40,29 @@
|
|||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* ARM CPU related clocks.
|
||||
*/
|
||||
clk_m_a9: clk-m-a9@92b0000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
|
||||
reg = <0x92b0000 0x10000>;
|
||||
|
||||
clocks = <&clockgen_a9_pll 0>,
|
||||
<&clockgen_a9_pll 0>,
|
||||
<&clk_s_c0_flexgen 13>,
|
||||
<&clk_m_a9_ext2f_div2>;
|
||||
/*
|
||||
* ARM Peripheral clock for timers
|
||||
* ARM CPU related clocks.
|
||||
*/
|
||||
arm_periph_clk: clk-m-a9-periphs {
|
||||
clk_m_a9: clk-m-a9 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&clk_m_a9>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
|
||||
|
||||
clocks = <&clockgen_a9_pll 0>,
|
||||
<&clockgen_a9_pll 0>,
|
||||
<&clk_s_c0_flexgen 13>,
|
||||
<&clk_m_a9_ext2f_div2>;
|
||||
|
||||
/*
|
||||
* ARM Peripheral clock for timers
|
||||
*/
|
||||
arm_periph_clk: clk-m-a9-periphs {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&clk_m_a9>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -87,14 +87,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-pll";
|
||||
reg = <0x9103000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clk_s_c0: clockgen-c@9103000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x9103000 0x1000>;
|
||||
|
|
@ -113,6 +105,13 @@
|
|||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clk_s_c0_quadfs: clk-s-c0-quadfs {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-pll";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clk_s_c0_flexgen: clk-s-c0-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen", "st,flexgen-stih410-c0";
|
||||
|
|
@ -142,18 +141,17 @@
|
|||
};
|
||||
};
|
||||
|
||||
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-d0";
|
||||
reg = <0x9104000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clockgen-d0@9104000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x9104000 0x1000>;
|
||||
|
||||
clk_s_d0_quadfs: clk-s-d0-quadfs {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-d0";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clk_s_d0_flexgen: clk-s-d0-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen", "st,flexgen-stih410-d0";
|
||||
|
|
@ -166,18 +164,17 @@
|
|||
};
|
||||
};
|
||||
|
||||
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-d2";
|
||||
reg = <0x9106000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clockgen-d2@9106000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x9106000 0x1000>;
|
||||
|
||||
clk_s_d2_quadfs: clk-s-d2-quadfs {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-d2";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clk_s_d2_flexgen: clk-s-d2-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen", "st,flexgen-stih407-d2";
|
||||
|
|
@ -192,18 +189,17 @@
|
|||
};
|
||||
};
|
||||
|
||||
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-d3";
|
||||
reg = <0x9107000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clockgen-d3@9107000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x9107000 0x1000>;
|
||||
|
||||
clk_s_d3_quadfs: clk-s-d3-quadfs {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-d3";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clk_s_d3_flexgen: clk-s-d3-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen", "st,flexgen-stih407-d3";
|
||||
|
|
|
|||
|
|
@ -12,31 +12,29 @@
|
|||
bdisp0 = &bdisp0;
|
||||
};
|
||||
|
||||
usb2_picophy1: phy2 {
|
||||
compatible = "st,stih407-usb2-phy";
|
||||
#phy-cells = <0>;
|
||||
st,syscfg = <&syscfg_core 0xf8 0xf4>;
|
||||
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
|
||||
<&picophyreset STIH407_PICOPHY0_RESET>;
|
||||
reset-names = "global", "port";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_picophy2: phy3 {
|
||||
compatible = "st,stih407-usb2-phy";
|
||||
#phy-cells = <0>;
|
||||
st,syscfg = <&syscfg_core 0xfc 0xf4>;
|
||||
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
|
||||
<&picophyreset STIH407_PICOPHY1_RESET>;
|
||||
reset-names = "global", "port";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
soc {
|
||||
usb2_picophy1: phy2@0 {
|
||||
compatible = "st,stih407-usb2-phy";
|
||||
reg = <0 0>;
|
||||
#phy-cells = <0>;
|
||||
st,syscfg = <&syscfg_core 0xf8 0xf4>;
|
||||
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
|
||||
<&picophyreset STIH407_PICOPHY0_RESET>;
|
||||
reset-names = "global", "port";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_picophy2: phy3@0 {
|
||||
compatible = "st,stih407-usb2-phy";
|
||||
reg = <0 0>;
|
||||
#phy-cells = <0>;
|
||||
st,syscfg = <&syscfg_core 0xfc 0xf4>;
|
||||
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
|
||||
<&picophyreset STIH407_PICOPHY1_RESET>;
|
||||
reset-names = "global", "port";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@9a03c00 {
|
||||
compatible = "st,st-ohci-300x";
|
||||
reg = <0x9a03c00 0x100>;
|
||||
|
|
@ -274,16 +272,6 @@
|
|||
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
delta0@0 {
|
||||
compatible = "st,st-delta";
|
||||
clock-names = "delta",
|
||||
"delta-st231",
|
||||
"delta-flash-promip";
|
||||
clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
|
||||
<&clk_s_c0_flexgen CLK_ST231_DMU>,
|
||||
<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
|
||||
};
|
||||
|
||||
sti-cec@94a087c {
|
||||
compatible = "st,stih-cec";
|
||||
reg = <0x94a087c 0x64>;
|
||||
|
|
|
|||
|
|
@ -37,6 +37,17 @@
|
|||
};
|
||||
};
|
||||
|
||||
miphy28lp_phy: miphy28lp {
|
||||
|
||||
phy_port0: port@9b22000 {
|
||||
st,osc-rdy;
|
||||
};
|
||||
|
||||
phy_port1: port@9b2a000 {
|
||||
st,osc-force-ext;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
sbc_serial0: serial@9530000 {
|
||||
status = "okay";
|
||||
|
|
@ -84,17 +95,6 @@
|
|||
non-removable;
|
||||
};
|
||||
|
||||
miphy28lp_phy: miphy28lp@0 {
|
||||
|
||||
phy_port0: port@9b22000 {
|
||||
st,osc-rdy;
|
||||
};
|
||||
|
||||
phy_port1: port@9b2a000 {
|
||||
st,osc-force-ext;
|
||||
};
|
||||
};
|
||||
|
||||
st_dwc3: dwc3@8f94000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@
|
|||
*/
|
||||
clockgen-a9@92b0000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x92b0000 0xffff>;
|
||||
reg = <0x92b0000 0x10000>;
|
||||
|
||||
clockgen_a9_pll: clockgen-a9-pll {
|
||||
#clock-cells = <1>;
|
||||
|
|
@ -40,30 +40,29 @@
|
|||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* ARM CPU related clocks.
|
||||
*/
|
||||
clk_m_a9: clk-m-a9@92b0000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
|
||||
reg = <0x92b0000 0x10000>;
|
||||
|
||||
clocks = <&clockgen_a9_pll 0>,
|
||||
<&clockgen_a9_pll 0>,
|
||||
<&clk_s_c0_flexgen 13>,
|
||||
<&clk_m_a9_ext2f_div2>;
|
||||
|
||||
/*
|
||||
* ARM Peripheral clock for timers
|
||||
* ARM CPU related clocks.
|
||||
*/
|
||||
arm_periph_clk: clk-m-a9-periphs {
|
||||
clk_m_a9: clk-m-a9 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&clk_m_a9>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
|
||||
|
||||
clocks = <&clockgen_a9_pll 0>,
|
||||
<&clockgen_a9_pll 0>,
|
||||
<&clk_s_c0_flexgen 13>,
|
||||
<&clk_m_a9_ext2f_div2>;
|
||||
|
||||
/*
|
||||
* ARM Peripheral clock for timers
|
||||
*/
|
||||
arm_periph_clk: clk-m-a9-periphs {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&clk_m_a9>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -88,14 +87,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-pll";
|
||||
reg = <0x9103000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clk_s_c0: clockgen-c@9103000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x9103000 0x1000>;
|
||||
|
|
@ -114,6 +105,13 @@
|
|||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clk_s_c0_quadfs: clk-s-c0-quadfs {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-pll";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clk_s_c0_flexgen: clk-s-c0-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen", "st,flexgen-stih418-c0";
|
||||
|
|
@ -143,18 +141,17 @@
|
|||
};
|
||||
};
|
||||
|
||||
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-d0";
|
||||
reg = <0x9104000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clockgen-d0@9104000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x9104000 0x1000>;
|
||||
|
||||
clk_s_d0_quadfs: clk-s-d0-quadfs {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-d0";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clk_s_d0_flexgen: clk-s-d0-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen", "st,flexgen-stih410-d0";
|
||||
|
|
@ -167,18 +164,17 @@
|
|||
};
|
||||
};
|
||||
|
||||
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-d2";
|
||||
reg = <0x9106000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clockgen-d2@9106000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x9106000 0x1000>;
|
||||
|
||||
clk_s_d2_quadfs: clk-s-d2-quadfs {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-d2";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clk_s_d2_flexgen: clk-s-d2-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen", "st,flexgen-stih418-d2";
|
||||
|
|
@ -193,18 +189,17 @@
|
|||
};
|
||||
};
|
||||
|
||||
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-d3";
|
||||
reg = <0x9107000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clockgen-d3@9107000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x9107000 0x1000>;
|
||||
|
||||
clk_s_d3_quadfs: clk-s-d3-quadfs {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-d3";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
};
|
||||
|
||||
clk_s_d3_flexgen: clk-s-d3-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen", "st,flexgen-stih407-d3";
|
||||
|
|
|
|||
|
|
@ -26,31 +26,29 @@
|
|||
};
|
||||
};
|
||||
|
||||
usb2_picophy1: phy2 {
|
||||
compatible = "st,stih407-usb2-phy";
|
||||
#phy-cells = <0>;
|
||||
st,syscfg = <&syscfg_core 0xf8 0xf4>;
|
||||
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
|
||||
<&picophyreset STIH407_PICOPHY0_RESET>;
|
||||
reset-names = "global", "port";
|
||||
};
|
||||
|
||||
usb2_picophy2: phy3 {
|
||||
compatible = "st,stih407-usb2-phy";
|
||||
#phy-cells = <0>;
|
||||
st,syscfg = <&syscfg_core 0xfc 0xf4>;
|
||||
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
|
||||
<&picophyreset STIH407_PICOPHY1_RESET>;
|
||||
reset-names = "global", "port";
|
||||
};
|
||||
|
||||
soc {
|
||||
rng11: rng@8a8a000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_picophy1: phy2@0 {
|
||||
compatible = "st,stih407-usb2-phy";
|
||||
reg = <0 0>;
|
||||
#phy-cells = <0>;
|
||||
st,syscfg = <&syscfg_core 0xf8 0xf4>;
|
||||
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
|
||||
<&picophyreset STIH407_PICOPHY0_RESET>;
|
||||
reset-names = "global", "port";
|
||||
};
|
||||
|
||||
usb2_picophy2: phy3@0 {
|
||||
compatible = "st,stih407-usb2-phy";
|
||||
reg = <0 0>;
|
||||
#phy-cells = <0>;
|
||||
st,syscfg = <&syscfg_core 0xfc 0xf4>;
|
||||
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
|
||||
<&picophyreset STIH407_PICOPHY1_RESET>;
|
||||
reset-names = "global", "port";
|
||||
};
|
||||
|
||||
ohci0: usb@9a03c00 {
|
||||
compatible = "st,st-ohci-300x";
|
||||
reg = <0x9a03c00 0x100>;
|
||||
|
|
|
|||
|
|
@ -71,6 +71,17 @@
|
|||
};
|
||||
};
|
||||
|
||||
miphy28lp_phy: miphy28lp {
|
||||
|
||||
phy_port0: port@9b22000 {
|
||||
st,osc-rdy;
|
||||
};
|
||||
|
||||
phy_port1: port@9b2a000 {
|
||||
st,osc-force-ext;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
sbc_serial0: serial@9530000 {
|
||||
status = "okay";
|
||||
|
|
@ -128,17 +139,6 @@
|
|||
st,i2c-min-sda-pulse-width-us = <5>;
|
||||
};
|
||||
|
||||
miphy28lp_phy: miphy28lp@0 {
|
||||
|
||||
phy_port0: port@9b22000 {
|
||||
st,osc-rdy;
|
||||
};
|
||||
|
||||
phy_port1: port@9b2a000 {
|
||||
st,osc-force-ext;
|
||||
};
|
||||
};
|
||||
|
||||
st_dwc3: dwc3@8f94000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue