x86: coding style fixes to x86/kernel/cpu/cpufreq/cpufreq-nforce2.c
Before: total: 22 errors, 8 warnings, 440 lines checked After: total: 0 errors, 8 warnings, 442 lines checked paolo@paolo-desktop:~/linux.trees.git$ md5sum /tmp/cpufreq-nforce2.o.* 3d4330a5d188fe904446e5948a618b48 /tmp/cpufreq-nforce2.o.after 1477e6b0dcd6f59b1fb6b4490042eca6 /tmp/cpufreq-nforce2.o.before ^^^ I guess this is because I fixed a few "do not initialise statics to 0 or NULL" paolo@paolo-desktop:~/linux.trees.git$ size /tmp/cpufreq-nforce2.o.* text data bss dec hex filename 1923 72 16 2011 7db /tmp/cpufreq-nforce2.o.after 1923 72 16 2011 7db /tmp/cpufreq-nforce2.o.before Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -26,9 +26,10 @@
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#define NFORCE2_SAFE_DISTANCE 50
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/* Delay in ms between FSB changes */
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//#define NFORCE2_DELAY 10
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/* #define NFORCE2_DELAY 10 */
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/* nforce2_chipset:
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/*
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* nforce2_chipset:
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* FSB is changed using the chipset
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*/
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static struct pci_dev *nforce2_chipset_dev;
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@ -36,13 +37,13 @@ static struct pci_dev *nforce2_chipset_dev;
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/* fid:
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* multiplier * 10
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*/
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static int fid = 0;
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static int fid;
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/* min_fsb, max_fsb:
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* minimum and maximum FSB (= FSB at boot time)
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*/
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static int min_fsb = 0;
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static int max_fsb = 0;
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static int min_fsb;
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static int max_fsb;
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MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
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MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
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@ -139,7 +140,7 @@ static unsigned int nforce2_fsb_read(int bootfsb)
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/* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
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nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
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0x01EF,PCI_ANY_ID,PCI_ANY_ID,NULL);
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0x01EF, PCI_ANY_ID, PCI_ANY_ID, NULL);
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if (!nforce2_sub5)
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return 0;
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@ -147,13 +148,13 @@ static unsigned int nforce2_fsb_read(int bootfsb)
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fsb /= 1000000;
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/* Check if PLL register is already set */
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pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
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pci_read_config_byte(nforce2_chipset_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
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if(bootfsb || !temp)
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if (bootfsb || !temp)
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return fsb;
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/* Use PLL register FSB value */
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pci_read_config_dword(nforce2_chipset_dev,NFORCE2_PLLREG, &temp);
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pci_read_config_dword(nforce2_chipset_dev, NFORCE2_PLLREG, &temp);
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fsb = nforce2_calc_fsb(temp);
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return fsb;
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@ -184,7 +185,7 @@ static int nforce2_set_fsb(unsigned int fsb)
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}
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/* First write? Then set actual value */
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pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
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pci_read_config_byte(nforce2_chipset_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
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if (!temp) {
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pll = nforce2_calc_pll(tfsb);
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@ -210,7 +211,8 @@ static int nforce2_set_fsb(unsigned int fsb)
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tfsb--;
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/* Calculate the PLL reg. value */
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if ((pll = nforce2_calc_pll(tfsb)) == -1)
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pll = nforce2_calc_pll(tfsb);
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if (pll == -1)
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return -EINVAL;
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nforce2_write_pll(pll);
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@ -249,7 +251,7 @@ static unsigned int nforce2_get(unsigned int cpu)
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static int nforce2_target(struct cpufreq_policy *policy,
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unsigned int target_freq, unsigned int relation)
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{
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// unsigned long flags;
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/* unsigned long flags; */
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struct cpufreq_freqs freqs;
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unsigned int target_fsb;
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@ -271,7 +273,7 @@ static int nforce2_target(struct cpufreq_policy *policy,
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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/* Disable IRQs */
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//local_irq_save(flags);
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/* local_irq_save(flags); */
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if (nforce2_set_fsb(target_fsb) < 0)
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printk(KERN_ERR "cpufreq: Changing FSB to %d failed\n",
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@ -281,7 +283,7 @@ static int nforce2_target(struct cpufreq_policy *policy,
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target_fsb);
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/* Enable IRQs */
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//local_irq_restore(flags);
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/* local_irq_restore(flags); */
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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@ -347,7 +349,7 @@ static int nforce2_cpu_init(struct cpufreq_policy *policy)
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/* Set maximum FSB to FSB at boot time */
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max_fsb = nforce2_fsb_read(1);
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if(!max_fsb)
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if (!max_fsb)
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return -EIO;
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if (!min_fsb)
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