scsi: ufs: host: ufs-exynos: Add support for FSD UFS HCI
Adds support of UFS HCI which is found in Tesla Full Self-Driving (FSD) SoC. Link: https://lore.kernel.org/r/20220610104119.66401-7-alim.akhtar@samsung.com Co-developed-by: Bharat Uppal <bharat.uppal@samsung.com> Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Alim Akhtar
Martin K. Petersen
parent
daa782a51e
commit
216f74e805
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@ -146,6 +146,10 @@ enum {
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#define UNIPRO_DME_PWR_REQ_REMOTEL2TIMER1 0x0A8
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#define UNIPRO_DME_PWR_REQ_REMOTEL2TIMER2 0x0AC
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#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0 0x78B8
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#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1 0x78BC
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#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2 0x78C0
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/*
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* UFS Protector registers
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*/
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@ -1474,6 +1478,99 @@ static int exynosauto_ufs_vh_init(struct ufs_hba *hba)
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return 0;
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}
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static int fsd_ufs_pre_link(struct exynos_ufs *ufs)
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{
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int i;
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struct ufs_hba *hba = ufs->hba;
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),
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DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
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for_each_ufs_tx_lane(ufs, i) {
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i),
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DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
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}
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for_each_ufs_rx_lane(ufs, i) {
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
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DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
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}
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), 0x2e820183);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
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exynos_ufs_establish_connt(ufs);
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return 0;
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}
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static int fsd_ufs_post_link(struct exynos_ufs *ufs)
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{
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int i;
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struct ufs_hba *hba = ufs->hba;
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u32 hw_cap_min_tactivate;
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u32 peer_rx_min_actv_time_cap;
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u32 max_rx_hibern8_time_cap;
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ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
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&hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */
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ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
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&peer_rx_min_actv_time_cap); /* PA_TActivate */
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ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
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&max_rx_hibern8_time_cap); /* PA_Hibern8Time */
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if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
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ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
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peer_rx_min_actv_time_cap + 1);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), max_rx_hibern8_time_cap + 1);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x01);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xFA);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x00);
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
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for_each_ufs_rx_lane(ufs, i) {
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
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}
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
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return 0;
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}
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static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
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struct ufs_pa_layer_attr *pwr)
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{
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struct ufs_hba *hba = ufs->hba;
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
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unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0);
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unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1);
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unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2);
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return 0;
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}
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static struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
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.name = "exynos_ufs",
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.init = exynos_ufs_init,
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@ -1596,6 +1693,47 @@ static struct exynos_ufs_drv_data exynos_ufs_drvs = {
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.post_pwr_change = exynos7_ufs_post_pwr_change,
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};
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static struct exynos_ufs_uic_attr fsd_uic_attr = {
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.tx_trailingclks = 0x10,
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.tx_dif_p_nsec = 3000000, /* unit: ns */
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.tx_dif_n_nsec = 1000000, /* unit: ns */
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.tx_high_z_cnt_nsec = 20000, /* unit: ns */
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.tx_base_unit_nsec = 100000, /* unit: ns */
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.tx_gran_unit_nsec = 4000, /* unit: ns */
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.tx_sleep_cnt = 1000, /* unit: ns */
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.tx_min_activatetime = 0xa,
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.rx_filler_enable = 0x2,
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.rx_dif_p_nsec = 1000000, /* unit: ns */
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.rx_hibern8_wait_nsec = 4000000, /* unit: ns */
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.rx_base_unit_nsec = 100000, /* unit: ns */
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.rx_gran_unit_nsec = 4000, /* unit: ns */
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.rx_sleep_cnt = 1280, /* unit: ns */
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.rx_stall_cnt = 320, /* unit: ns */
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.rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
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.rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
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.rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
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.rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
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.rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
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.rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
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.pa_dbg_option_suite = 0x2E820183,
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};
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struct exynos_ufs_drv_data fsd_ufs_drvs = {
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.uic_attr = &fsd_uic_attr,
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.quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
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UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
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UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
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UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING |
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UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
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.opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
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EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
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EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
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EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
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.pre_link = fsd_ufs_pre_link,
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.post_link = fsd_ufs_post_link,
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.pre_pwr_change = fsd_ufs_pre_pwr_change,
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};
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static const struct of_device_id exynos_ufs_of_match[] = {
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{ .compatible = "samsung,exynos7-ufs",
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.data = &exynos_ufs_drvs },
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@ -1603,6 +1741,8 @@ static const struct of_device_id exynos_ufs_of_match[] = {
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.data = &exynosauto_ufs_drvs },
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{ .compatible = "samsung,exynosautov9-ufs-vh",
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.data = &exynosauto_ufs_vh_drvs },
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{ .compatible = "tesla,fsd-ufs",
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.data = &fsd_ufs_drvs },
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{},
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};
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@ -22,6 +22,7 @@
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#define PA_DBG_RXPHY_CFGUPDT 0x9519
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#define PA_DBG_MODE 0x9529
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#define PA_DBG_SKIP_RESET_PHY 0x9539
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#define PA_DBG_AUTOMODE_THLD 0x9536
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#define PA_DBG_OV_TM 0x9540
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#define PA_DBG_SKIP_LINE_RESET 0x9541
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#define PA_DBG_LINE_RESET_REQ 0x9543
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