drm/amd/display: update audio wall clock programming
[why] for audio on real TV issue. [how] -add wall clock programming for DPREF based when Pixel clock is done by DP DTO. Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -140,6 +140,8 @@ static void check_audio_bandwidth_hdmi(
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bool limit_freq_to_88_2_khz = false;
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bool limit_freq_to_96_khz = false;
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bool limit_freq_to_174_4_khz = false;
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if (!crtc_info)
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return;
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/* For two channels supported return whatever sink support,unmodified*/
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if (channel_count > 2) {
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@ -784,7 +786,7 @@ void dce_aud_wall_dto_setup(
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struct azalia_clock_info clock_info = { 0 };
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if (dc_is_hdmi_signal(signal)) {
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if (dc_is_hdmi_tmds_signal(signal)) {
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uint32_t src_sel;
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/*DTO0 Programming goal:
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@ -1148,7 +1148,7 @@ static void build_audio_output(
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pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
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/*for HDMI, audio ACR is with deep color ratio factor*/
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if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
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if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
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audio_output->crtc_info.requested_pixel_clock_100Hz ==
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(stream->timing.pix_clk_100hz)) {
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if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
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@ -1963,10 +1963,8 @@ static void dce110_setup_audio_dto(
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if (pipe_ctx->top_pipe)
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continue;
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if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
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continue;
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if (pipe_ctx->stream_res.audio != NULL) {
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struct audio_output audio_output;
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