irqchip/meson: Add support for gpio interrupt controller
Add support for the interrupt gpio controller found on Amlogic's meson SoC family. This controller is a separate controller from the gpio controller. It is able to spy on the SoC pad. It is essentially a 256 to 8 router with a filtering block to select level or edge and polarity. The number of actual mappable inputs depends on the SoC. Cc: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Jerome Brunet
Marc Zyngier
parent
df48d3b5ef
commit
215f4cc0fb
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@ -324,4 +324,12 @@ config IRQ_UNIPHIER_AIDET
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help
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Support for the UniPhier AIDET (ARM Interrupt Detector).
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config MESON_IRQ_GPIO
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bool "Meson GPIO Interrupt Multiplexer"
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depends on ARCH_MESON || COMPILE_TEST
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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help
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Support Meson SoC Family GPIO Interrupt Multiplexer
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endmenu
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@ -79,3 +79,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
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obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
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obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
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obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
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obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o
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@ -0,0 +1,414 @@
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/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#define NUM_CHANNEL 8
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#define MAX_INPUT_MUX 256
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#define REG_EDGE_POL 0x00
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#define REG_PIN_03_SEL 0x04
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#define REG_PIN_47_SEL 0x08
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#define REG_FILTER_SEL 0x0c
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#define REG_EDGE_POL_MASK(x) (BIT(x) | BIT(16 + (x)))
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#define REG_EDGE_POL_EDGE(x) BIT(x)
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#define REG_EDGE_POL_LOW(x) BIT(16 + (x))
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#define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
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#define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
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struct meson_gpio_irq_params {
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unsigned int nr_hwirq;
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};
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static const struct meson_gpio_irq_params meson8b_params = {
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.nr_hwirq = 119,
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};
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static const struct meson_gpio_irq_params gxbb_params = {
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.nr_hwirq = 133,
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};
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static const struct meson_gpio_irq_params gxl_params = {
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.nr_hwirq = 110,
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};
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static const struct of_device_id meson_irq_gpio_matches[] = {
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{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
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{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
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{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
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{ }
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};
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struct meson_gpio_irq_controller {
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unsigned int nr_hwirq;
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void __iomem *base;
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u32 channel_irqs[NUM_CHANNEL];
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DECLARE_BITMAP(channel_map, NUM_CHANNEL);
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spinlock_t lock;
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};
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static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
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unsigned int reg, u32 mask, u32 val)
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{
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u32 tmp;
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tmp = readl_relaxed(ctl->base + reg);
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tmp &= ~mask;
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tmp |= val;
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writel_relaxed(tmp, ctl->base + reg);
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}
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static unsigned int meson_gpio_irq_channel_to_reg(unsigned int channel)
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{
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return (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
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}
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static int
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meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
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unsigned long hwirq,
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u32 **channel_hwirq)
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{
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unsigned int reg, idx;
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spin_lock(&ctl->lock);
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/* Find a free channel */
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idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
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if (idx >= NUM_CHANNEL) {
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spin_unlock(&ctl->lock);
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pr_err("No channel available\n");
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return -ENOSPC;
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}
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/* Mark the channel as used */
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set_bit(idx, ctl->channel_map);
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/*
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* Setup the mux of the channel to route the signal of the pad
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* to the appropriate input of the GIC
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*/
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reg = meson_gpio_irq_channel_to_reg(idx);
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meson_gpio_irq_update_bits(ctl, reg,
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0xff << REG_PIN_SEL_SHIFT(idx),
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hwirq << REG_PIN_SEL_SHIFT(idx));
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/*
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* Get the hwirq number assigned to this channel through
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* a pointer the channel_irq table. The added benifit of this
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* method is that we can also retrieve the channel index with
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* it, using the table base.
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*/
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*channel_hwirq = &(ctl->channel_irqs[idx]);
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spin_unlock(&ctl->lock);
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pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
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hwirq, idx, **channel_hwirq);
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return 0;
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}
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static unsigned int
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meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
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u32 *channel_hwirq)
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{
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return channel_hwirq - ctl->channel_irqs;
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}
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static void
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meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
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u32 *channel_hwirq)
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{
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unsigned int idx;
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idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
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clear_bit(idx, ctl->channel_map);
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}
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static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
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unsigned int type,
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u32 *channel_hwirq)
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{
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u32 val = 0;
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unsigned int idx;
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idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
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/*
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* The controller has a filter block to operate in either LEVEL or
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* EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
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* EDGE_FALLING support (which the GIC does not support), the filter
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* block is also able to invert the input signal it gets before
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* providing it to the GIC.
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*/
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type &= IRQ_TYPE_SENSE_MASK;
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if (type == IRQ_TYPE_EDGE_BOTH)
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return -EINVAL;
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
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val |= REG_EDGE_POL_EDGE(idx);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
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val |= REG_EDGE_POL_LOW(idx);
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spin_lock(&ctl->lock);
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meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
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REG_EDGE_POL_MASK(idx), val);
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spin_unlock(&ctl->lock);
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return 0;
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}
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static unsigned int meson_gpio_irq_type_output(unsigned int type)
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{
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unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
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type &= ~IRQ_TYPE_SENSE_MASK;
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/*
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* The polarity of the signal provided to the GIC should always
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* be high.
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*/
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if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
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type |= IRQ_TYPE_LEVEL_HIGH;
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else if (sense & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
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type |= IRQ_TYPE_EDGE_RISING;
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return type;
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}
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static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct meson_gpio_irq_controller *ctl = data->domain->host_data;
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u32 *channel_hwirq = irq_data_get_irq_chip_data(data);
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int ret;
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ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq);
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if (ret)
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return ret;
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return irq_chip_set_type_parent(data,
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meson_gpio_irq_type_output(type));
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}
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static struct irq_chip meson_gpio_irq_chip = {
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.name = "meson-gpio-irqchip",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_type = meson_gpio_irq_set_type,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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.flags = IRQCHIP_SET_TYPE_MASKED,
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};
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static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1];
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return 0;
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}
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return -EINVAL;
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}
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static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
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unsigned int virq,
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u32 hwirq,
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unsigned int type)
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{
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struct irq_fwspec fwspec;
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fwspec.fwnode = domain->parent->fwnode;
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fwspec.param_count = 3;
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fwspec.param[0] = 0; /* SPI */
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fwspec.param[1] = hwirq;
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fwspec.param[2] = meson_gpio_irq_type_output(type);
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return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
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}
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static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs,
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void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct meson_gpio_irq_controller *ctl = domain->host_data;
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unsigned long hwirq;
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u32 *channel_hwirq;
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unsigned int type;
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int ret;
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if (WARN_ON(nr_irqs != 1))
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return -EINVAL;
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ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq);
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if (ret)
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return ret;
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ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
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*channel_hwirq, type);
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if (ret < 0) {
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pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
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meson_gpio_irq_release_channel(ctl, channel_hwirq);
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return ret;
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}
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irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&meson_gpio_irq_chip, channel_hwirq);
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return 0;
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}
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static void meson_gpio_irq_domain_free(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs)
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{
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struct meson_gpio_irq_controller *ctl = domain->host_data;
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struct irq_data *irq_data;
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u32 *channel_hwirq;
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if (WARN_ON(nr_irqs != 1))
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return;
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irq_domain_free_irqs_parent(domain, virq, 1);
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irq_data = irq_domain_get_irq_data(domain, virq);
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channel_hwirq = irq_data_get_irq_chip_data(irq_data);
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meson_gpio_irq_release_channel(ctl, channel_hwirq);
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}
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static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
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.alloc = meson_gpio_irq_domain_alloc,
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.free = meson_gpio_irq_domain_free,
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.translate = meson_gpio_irq_domain_translate,
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};
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static int __init meson_gpio_irq_parse_dt(struct device_node *node,
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struct meson_gpio_irq_controller *ctl)
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{
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const struct of_device_id *match;
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const struct meson_gpio_irq_params *params;
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int ret;
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match = of_match_node(meson_irq_gpio_matches, node);
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if (!match)
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return -ENODEV;
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params = match->data;
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ctl->nr_hwirq = params->nr_hwirq;
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ret = of_property_read_variable_u32_array(node,
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"amlogic,channel-interrupts",
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ctl->channel_irqs,
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NUM_CHANNEL,
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NUM_CHANNEL);
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if (ret < 0) {
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pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
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return ret;
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}
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return 0;
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}
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static int __init meson_gpio_irq_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *domain, *parent_domain;
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struct meson_gpio_irq_controller *ctl;
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int ret;
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if (!parent) {
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pr_err("missing parent interrupt node\n");
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return -ENODEV;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("unable to obtain parent domain\n");
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return -ENXIO;
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}
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ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
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if (!ctl)
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return -ENOMEM;
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spin_lock_init(&ctl->lock);
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ctl->base = of_iomap(node, 0);
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if (!ctl->base) {
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ret = -ENOMEM;
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goto free_ctl;
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}
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ret = meson_gpio_irq_parse_dt(node, ctl);
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if (ret)
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goto free_channel_irqs;
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domain = irq_domain_create_hierarchy(parent_domain, 0, ctl->nr_hwirq,
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of_node_to_fwnode(node),
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&meson_gpio_irq_domain_ops,
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ctl);
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if (!domain) {
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pr_err("failed to add domain\n");
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ret = -ENODEV;
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goto free_channel_irqs;
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}
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pr_info("%d to %d gpio interrupt mux initialized\n",
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ctl->nr_hwirq, NUM_CHANNEL);
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return 0;
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free_channel_irqs:
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iounmap(ctl->base);
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free_ctl:
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kfree(ctl);
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return ret;
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}
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IRQCHIP_DECLARE(meson_gpio_intc, "amlogic,meson-gpio-intc",
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meson_gpio_irq_of_init);
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