RDMA/hns: Remove Receive Queue of CMDQ
The CRQ of CMDQ is unused, so remove code about it. Link: https://lore.kernel.org/r/1621482876-35780-3-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Reviewed-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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@ -1209,8 +1209,6 @@ static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
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kfree(ring->desc);
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ring->desc = NULL;
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dev_err_ratelimited(hr_dev->dev,
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"failed to map cmq desc addr.\n");
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return -ENOMEM;
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}
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@ -1228,44 +1226,32 @@ static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
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kfree(ring->desc);
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}
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static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
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static int init_csq(struct hns_roce_dev *hr_dev,
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struct hns_roce_v2_cmq_ring *csq)
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{
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struct hns_roce_v2_priv *priv = hr_dev->priv;
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struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
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&priv->cmq.csq : &priv->cmq.crq;
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dma_addr_t dma;
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int ret;
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ring->flag = ring_type;
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ring->head = 0;
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csq->desc_num = CMD_CSQ_DESC_NUM;
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spin_lock_init(&csq->lock);
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csq->flag = TYPE_CSQ;
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csq->head = 0;
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return hns_roce_alloc_cmq_desc(hr_dev, ring);
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}
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ret = hns_roce_alloc_cmq_desc(hr_dev, csq);
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if (ret)
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return ret;
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static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
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{
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struct hns_roce_v2_priv *priv = hr_dev->priv;
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struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
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&priv->cmq.csq : &priv->cmq.crq;
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dma_addr_t dma = ring->desc_dma_addr;
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dma = csq->desc_dma_addr;
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roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma));
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roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma));
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roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
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(u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
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if (ring_type == TYPE_CSQ) {
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roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
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roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
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upper_32_bits(dma));
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roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
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(u32)ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
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/* Make sure to write CI first and then PI */
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roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
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roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
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/* Make sure to write tail first and then head */
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roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
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roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
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} else {
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roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
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roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
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upper_32_bits(dma));
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roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
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(u32)ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
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roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
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roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
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}
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return 0;
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}
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static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
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@ -1273,43 +1259,11 @@ static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
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struct hns_roce_v2_priv *priv = hr_dev->priv;
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int ret;
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/* Setup the queue entries for command queue */
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priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
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priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
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/* Setup the lock for command queue */
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spin_lock_init(&priv->cmq.csq.lock);
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spin_lock_init(&priv->cmq.crq.lock);
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/* Setup Tx write back timeout */
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priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
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/* Init CSQ */
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ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
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if (ret) {
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dev_err_ratelimited(hr_dev->dev,
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"failed to init CSQ, ret = %d.\n", ret);
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return ret;
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}
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/* Init CRQ */
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ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
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if (ret) {
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dev_err_ratelimited(hr_dev->dev,
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"failed to init CRQ, ret = %d.\n", ret);
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goto err_crq;
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}
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/* Init CSQ REG */
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hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
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/* Init CRQ REG */
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hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
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return 0;
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err_crq:
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hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
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ret = init_csq(hr_dev, &priv->cmq.csq);
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if (ret)
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dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret);
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return ret;
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}
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@ -1319,7 +1273,6 @@ static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
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struct hns_roce_v2_priv *priv = hr_dev->priv;
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hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
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hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
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}
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static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
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@ -1712,7 +1712,6 @@ struct hns_roce_v2_cmq_ring {
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struct hns_roce_v2_cmq {
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struct hns_roce_v2_cmq_ring csq;
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struct hns_roce_v2_cmq_ring crq;
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u16 tx_timeout;
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};
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