ARM: at91/dt: move at91sam9rl SoC to the new slow/main clock models
Move at91sam9rl SoC to the new main/slow clock model. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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@ -48,6 +48,18 @@
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reg = <0x20000000 0x04000000>;
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reg = <0x20000000 0x04000000>;
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};
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};
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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ahb {
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ahb {
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compatible = "simple-bus";
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compatible = "simple-bus";
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#address-cells = <1>;
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#address-cells = <1>;
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@ -548,17 +560,11 @@
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#size-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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#interrupt-cells = <1>;
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clk32k: slck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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main: mainck {
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main: mainck {
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compatible = "atmel,at91rm9200-clk-main";
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compatible = "atmel,at91rm9200-clk-main";
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#clock-cells = <0>;
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#clock-cells = <0>;
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interrupts-extended = <&pmc AT91_PMC_MOSCS>;
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interrupts-extended = <&pmc AT91_PMC_MOSCS>;
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clocks = <&clk32k>;
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clocks = <&main_xtal>;
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};
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};
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plla: pllack {
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plla: pllack {
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@ -769,6 +775,32 @@
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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status = "disabled";
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status = "disabled";
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};
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};
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sckc@fffffd50 {
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compatible = "atmel,at91sam9x5-sckc";
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reg = <0xfffffd50 0x4>;
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slow_osc: slow_osc {
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compatible = "atmel,at91sam9x5-clk-slow-osc";
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#clock-cells = <0>;
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atmel,startup-time-usec = <1200000>;
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clocks = <&slow_xtal>;
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};
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slow_rc_osc: slow_rc_osc {
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compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
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#clock-cells = <0>;
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atmel,startup-time-usec = <75>;
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clock-frequency = <32768>;
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clock-accuracy = <50000000>;
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};
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clk32k: slck {
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compatible = "atmel,at91sam9x5-clk-slow";
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#clock-cells = <0>;
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clocks = <&slow_rc_osc &slow_osc>;
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};
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};
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};
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};
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};
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};
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