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xtensa: rearrange CCOUNT calibration 

DT-enabled kernel should have a CPU node connected to a clock. This clock
is the CCOUNT clock. Use old platform_calibrate_ccount call as a fallback
when CPU node cannot be found or has no clock and in non-DT-enabled
configurations.

Drop no longer needed code that updates CPU clock-frequency property in
the DT; drop DT-related code from the platform_calibrate_ccount too.

Move of_clk_init to the top of time_init, so that clocks are initialized
before CCOUNT calibration is attempted.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2016-09-20 11:11:08 -07:00
parent 58c3e3ac7a
commit 205ad548a7
4 changed files with 41 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/xtensa/boot/dts/xtfpga.dtsi
View File

@ -19,9 +19,7 @@
cpu@0 {
compatible = "cdns,xtensa-cpu";
reg = <0>;
/* Filled in by platform_setup from FPGA register
* clock-frequency = <100000000>;
*/
clocks = <&osc>;
};
};

2
arch/xtensa/kernel/setup.c
View File

@ -23,7 +23,6 @@
#include <linux/bootmem.h>
#include <linux/kernel.h>
#include <linux/percpu.h>
#include <linux/clk-provider.h>
#include <linux/cpu.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
@ -249,7 +248,6 @@ void __init early_init_devtree(void *params)
static int __init xtensa_device_probe(void)
{
of_clk_init(NULL);
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
return 0;
}

40
arch/xtensa/kernel/time.c
View File

@ -12,6 +12,8 @@
* Chris Zankel <chris@zankel.net>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/time.h>
@ -134,16 +136,52 @@ void local_timer_setup(unsigned cpu)
0xf, 0xffffffff);
}
#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
#ifdef CONFIG_OF
static void __init calibrate_ccount(void)
{
struct device_node *cpu;
struct clk *clk;
cpu = of_find_compatible_node(NULL, NULL, "cdns,xtensa-cpu");
if (cpu) {
clk = of_clk_get(cpu, 0);
if (!IS_ERR(clk)) {
ccount_freq = clk_get_rate(clk);
return;
} else {
pr_warn("%s: CPU input clock not found\n",
__func__);
}
} else {
pr_warn("%s: CPU node not found in the device tree\n",
__func__);
}
platform_calibrate_ccount();
}
#else
static inline void calibrate_ccount(void)
{
platform_calibrate_ccount();
}
#endif
#endif
void __init time_init(void)
{
of_clk_init(NULL);
#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
printk("Calibrating CPU frequency ");
platform_calibrate_ccount();
calibrate_ccount();
printk("%d.%02d MHz\n", (int)ccount_freq/1000000,
(int)(ccount_freq/10000)%100);
#else
ccount_freq = CONFIG_XTENSA_CPU_CLOCK*1000000UL;
#endif
WARN(!ccount_freq,
"%s: CPU clock frequency is not set up correctly\n",
__func__);
clocksource_register_hz(&ccount_clocksource, ccount_freq);
local_timer_setup(0);
setup_irq(this_cpu_ptr(&ccount_timer)->evt.irq, &timer_irqaction);

39
arch/xtensa/platforms/xtfpga/setup.c
View File

@ -66,29 +66,6 @@ void __init platform_setup(char **cmdline)
#ifdef CONFIG_OF
static void __init update_clock_frequency(struct device_node *node)
{
struct property *newfreq;
u32 freq;
if (!of_property_read_u32(node, "clock-frequency", &freq) && freq != 0)
return;
newfreq = kzalloc(sizeof(*newfreq) + sizeof(u32), GFP_KERNEL);
if (!newfreq)
return;
newfreq->value = newfreq + 1;
newfreq->length = sizeof(freq);
newfreq->name = kstrdup("clock-frequency", GFP_KERNEL);
if (!newfreq->name) {
kfree(newfreq);
return;
}
*(u32 *)newfreq->value = cpu_to_be32(*(u32 *)XTFPGA_CLKFRQ_VADDR);
of_update_property(node, newfreq);
}
static void __init xtfpga_clk_setup(struct device_node *np)
{
void __iomem *base = of_iomap(np, 0);
@ -172,21 +149,7 @@ void platform_heartbeat(void)
void __init platform_calibrate_ccount(void)
{
long clk_freq = 0;
#ifdef CONFIG_OF
struct device_node *cpu =
of_find_compatible_node(NULL, NULL, "cdns,xtensa-cpu");
if (cpu) {
u32 freq;
update_clock_frequency(cpu);
if (!of_property_read_u32(cpu, "clock-frequency", &freq))
clk_freq = freq;
}
#endif
if (!clk_freq)
clk_freq = *(long *)XTFPGA_CLKFRQ_VADDR;
ccount_freq = clk_freq;
ccount_freq = *(long *)XTFPGA_CLKFRQ_VADDR;
}
#endif