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net: lan966x: Add registers to configure PCP, DEI, DSCP 

Add the registers that are needed to configure the PCP, DEI and DSCP
of the switch both at ingress and also at egress.

Reviewed-by: Daniel Machon <daniel.machon@microchip.com>
Reviewed-by: Piotr Raczynski <piotr.raczynski@intel.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Horatiu Vultur 2023-05-16 22:14:02 +02:00 committed by Paolo Abeni
parent b50a8b0d57
commit 1fd2221135
1 changed files with 132 additions and 0 deletions
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132
drivers/net/ethernet/microchip/lan966x/lan966x_regs.h
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@ -283,6 +283,18 @@ enum lan966x_target {
#define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\
FIELD_GET(ANA_VLAN_CFG_VLAN_POP_CNT, x)
#define ANA_VLAN_CFG_VLAN_PCP GENMASK(15, 13)
#define ANA_VLAN_CFG_VLAN_PCP_SET(x)\
FIELD_PREP(ANA_VLAN_CFG_VLAN_PCP, x)
#define ANA_VLAN_CFG_VLAN_PCP_GET(x)\
FIELD_GET(ANA_VLAN_CFG_VLAN_PCP, x)
#define ANA_VLAN_CFG_VLAN_DEI BIT(12)
#define ANA_VLAN_CFG_VLAN_DEI_SET(x)\
FIELD_PREP(ANA_VLAN_CFG_VLAN_DEI, x)
#define ANA_VLAN_CFG_VLAN_DEI_GET(x)\
FIELD_GET(ANA_VLAN_CFG_VLAN_DEI, x)
#define ANA_VLAN_CFG_VLAN_VID GENMASK(11, 0)
#define ANA_VLAN_CFG_VLAN_VID_SET(x)\
FIELD_PREP(ANA_VLAN_CFG_VLAN_VID, x)
@ -316,6 +328,39 @@ enum lan966x_target {
#define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\
FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x)
/* ANA:PORT:QOS_CFG */
#define ANA_QOS_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 8, 0, 1, 4)
#define ANA_QOS_CFG_DP_DEFAULT_VAL BIT(8)
#define ANA_QOS_CFG_DP_DEFAULT_VAL_SET(x)\
FIELD_PREP(ANA_QOS_CFG_DP_DEFAULT_VAL, x)
#define ANA_QOS_CFG_DP_DEFAULT_VAL_GET(x)\
FIELD_GET(ANA_QOS_CFG_DP_DEFAULT_VAL, x)
#define ANA_QOS_CFG_QOS_DEFAULT_VAL GENMASK(7, 5)
#define ANA_QOS_CFG_QOS_DEFAULT_VAL_SET(x)\
FIELD_PREP(ANA_QOS_CFG_QOS_DEFAULT_VAL, x)
#define ANA_QOS_CFG_QOS_DEFAULT_VAL_GET(x)\
FIELD_GET(ANA_QOS_CFG_QOS_DEFAULT_VAL, x)
#define ANA_QOS_CFG_QOS_DSCP_ENA BIT(4)
#define ANA_QOS_CFG_QOS_DSCP_ENA_SET(x)\
FIELD_PREP(ANA_QOS_CFG_QOS_DSCP_ENA, x)
#define ANA_QOS_CFG_QOS_DSCP_ENA_GET(x)\
FIELD_GET(ANA_QOS_CFG_QOS_DSCP_ENA, x)
#define ANA_QOS_CFG_QOS_PCP_ENA BIT(3)
#define ANA_QOS_CFG_QOS_PCP_ENA_SET(x)\
FIELD_PREP(ANA_QOS_CFG_QOS_PCP_ENA, x)
#define ANA_QOS_CFG_QOS_PCP_ENA_GET(x)\
FIELD_GET(ANA_QOS_CFG_QOS_PCP_ENA, x)
#define ANA_QOS_CFG_DSCP_REWR_CFG GENMASK(1, 0)
#define ANA_QOS_CFG_DSCP_REWR_CFG_SET(x)\
FIELD_PREP(ANA_QOS_CFG_DSCP_REWR_CFG, x)
#define ANA_QOS_CFG_DSCP_REWR_CFG_GET(x)\
FIELD_GET(ANA_QOS_CFG_DSCP_REWR_CFG, x)
/* ANA:PORT:VCAP_CFG */
#define ANA_VCAP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 12, 0, 1, 4)
@ -415,6 +460,21 @@ enum lan966x_target {
#define ANA_VCAP_S2_CFG_OAM_DIS_GET(x)\
FIELD_GET(ANA_VCAP_S2_CFG_OAM_DIS, x)
/* ANA:PORT:QOS_PCP_DEI_MAP_CFG */
#define ANA_PCP_DEI_CFG(g, r) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 32, r, 16, 4)
#define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL BIT(3)
#define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_SET(x)\
FIELD_PREP(ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL, x)
#define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_GET(x)\
FIELD_GET(ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL, x)
#define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL GENMASK(2, 0)
#define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_SET(x)\
FIELD_PREP(ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL, x)
#define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_GET(x)\
FIELD_GET(ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL, x)
/* ANA:PORT:CPU_FWD_CFG */
#define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4)
@ -478,6 +538,15 @@ enum lan966x_target {
#define ANA_PORT_CFG_PORTID_VAL_GET(x)\
FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x)
/* ANA:COMMON:DSCP_REWR_CFG */
#define ANA_DSCP_REWR_CFG(r) __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 332, r, 16, 4)
#define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL GENMASK(5, 0)
#define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_SET(x)\
FIELD_PREP(ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL, x)
#define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_GET(x)\
FIELD_GET(ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL, x)
/* ANA:PORT:POL_CFG */
#define ANA_POL_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 116, 0, 1, 4)
@ -547,6 +616,33 @@ enum lan966x_target {
#define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_GET(x)\
FIELD_GET(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x)
/* ANA:COMMON:DSCP_CFG */
#define ANA_DSCP_CFG(r) __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 76, r, 64, 4)
#define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11)
#define ANA_DSCP_CFG_DP_DSCP_VAL_SET(x)\
FIELD_PREP(ANA_DSCP_CFG_DP_DSCP_VAL, x)
#define ANA_DSCP_CFG_DP_DSCP_VAL_GET(x)\
FIELD_GET(ANA_DSCP_CFG_DP_DSCP_VAL, x)
#define ANA_DSCP_CFG_QOS_DSCP_VAL GENMASK(10, 8)
#define ANA_DSCP_CFG_QOS_DSCP_VAL_SET(x)\
FIELD_PREP(ANA_DSCP_CFG_QOS_DSCP_VAL, x)
#define ANA_DSCP_CFG_QOS_DSCP_VAL_GET(x)\
FIELD_GET(ANA_DSCP_CFG_QOS_DSCP_VAL, x)
#define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1)
#define ANA_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\
FIELD_PREP(ANA_DSCP_CFG_DSCP_TRUST_ENA, x)
#define ANA_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\
FIELD_GET(ANA_DSCP_CFG_DSCP_TRUST_ENA, x)
#define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0)
#define ANA_DSCP_CFG_DSCP_REWR_ENA_SET(x)\
FIELD_PREP(ANA_DSCP_CFG_DSCP_REWR_ENA, x)
#define ANA_DSCP_CFG_DSCP_REWR_ENA_GET(x)\
FIELD_GET(ANA_DSCP_CFG_DSCP_REWR_ENA, x)
/* ANA:POL:POL_PIR_CFG */
#define ANA_POL_PIR_CFG(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 0, 0, 1, 4)
@ -1468,6 +1564,18 @@ enum lan966x_target {
#define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\
FIELD_GET(REW_TAG_CFG_TAG_TPID_CFG, x)
#define REW_TAG_CFG_TAG_PCP_CFG GENMASK(3, 2)
#define REW_TAG_CFG_TAG_PCP_CFG_SET(x)\
FIELD_PREP(REW_TAG_CFG_TAG_PCP_CFG, x)
#define REW_TAG_CFG_TAG_PCP_CFG_GET(x)\
FIELD_GET(REW_TAG_CFG_TAG_PCP_CFG, x)
#define REW_TAG_CFG_TAG_DEI_CFG GENMASK(1, 0)
#define REW_TAG_CFG_TAG_DEI_CFG_SET(x)\
FIELD_PREP(REW_TAG_CFG_TAG_DEI_CFG, x)
#define REW_TAG_CFG_TAG_DEI_CFG_GET(x)\
FIELD_GET(REW_TAG_CFG_TAG_DEI_CFG, x)
/* REW:PORT:PORT_CFG */
#define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4)
@ -1483,6 +1591,30 @@ enum lan966x_target {
#define REW_PORT_CFG_NO_REWRITE_GET(x)\
FIELD_GET(REW_PORT_CFG_NO_REWRITE, x)
/* REW:PORT:DSCP_CFG */
#define REW_DSCP_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 12, 0, 1, 4)
#define REW_DSCP_CFG_DSCP_REWR_CFG GENMASK(1, 0)
#define REW_DSCP_CFG_DSCP_REWR_CFG_SET(x)\
FIELD_PREP(REW_DSCP_CFG_DSCP_REWR_CFG, x)
#define REW_DSCP_CFG_DSCP_REWR_CFG_GET(x)\
FIELD_GET(REW_DSCP_CFG_DSCP_REWR_CFG, x)
/* REW:PORT:PCP_DEI_QOS_MAP_CFG */
#define REW_PCP_DEI_CFG(g, r) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 16, r, 16, 4)
#define REW_PCP_DEI_CFG_DEI_QOS_VAL BIT(3)
#define REW_PCP_DEI_CFG_DEI_QOS_VAL_SET(x)\
FIELD_PREP(REW_PCP_DEI_CFG_DEI_QOS_VAL, x)
#define REW_PCP_DEI_CFG_DEI_QOS_VAL_GET(x)\
FIELD_GET(REW_PCP_DEI_CFG_DEI_QOS_VAL, x)
#define REW_PCP_DEI_CFG_PCP_QOS_VAL GENMASK(2, 0)
#define REW_PCP_DEI_CFG_PCP_QOS_VAL_SET(x)\
FIELD_PREP(REW_PCP_DEI_CFG_PCP_QOS_VAL, x)
#define REW_PCP_DEI_CFG_PCP_QOS_VAL_GET(x)\
FIELD_GET(REW_PCP_DEI_CFG_PCP_QOS_VAL, x)
/* REW:COMMON:STAT_CFG */
#define REW_STAT_CFG __REG(TARGET_REW, 0, 1, 3072, 0, 1, 528, 520, 0, 1, 4)