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clk: renesas: r9a07g044: Add GPT clock and reset entry 

Add GPT clock and reset entry to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220510110653.7326-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2022-05-10 12:06:52 +01:00 committed by Geert Uytterhoeven
parent f2906aa863
commit 1fb7a9fb62
1 changed files with 4 additions and 1 deletions
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5
drivers/clk/renesas/r9a07g044-cpg.c
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@ -182,7 +182,7 @@ static const struct {
}; };
static const struct { static const struct {
struct rzg2l_mod_clk common[71]; struct rzg2l_mod_clk common[72];
#ifdef CONFIG_CLK_R9A07G054 #ifdef CONFIG_CLK_R9A07G054
struct rzg2l_mod_clk drp[0]; struct rzg2l_mod_clk drp[0];
#endif #endif
@ -204,6 +204,8 @@ static const struct {
0x534, 1), 0x534, 1),
DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
0x534, 2), 0x534, 2),
DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
0x540, 0),
DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
0x548, 0), 0x548, 0),
DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
@ -346,6 +348,7 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0), DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2), DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0), DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1), DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2), DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),