ixgbe: fix to use correct timeout interval for memory read completion
Currently we were just always polling for a hard coded 80 ms and not respecting the system-wide timeout interval. Since up until now all devices have been tested with this 80ms value we continue to use this value as a hard minimum. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2436,6 +2436,55 @@ out:
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}
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}
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/**
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* ixgbe_pcie_timeout_poll - Return number of times to poll for completion
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* @hw: pointer to hardware structure
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*
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* System-wide timeout range is encoded in PCIe Device Control2 register.
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*
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* Add 10% to specified maximum and return the number of times to poll for
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* completion timeout, in units of 100 microsec. Never return less than
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* 800 = 80 millisec.
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**/
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static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
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{
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struct ixgbe_adapter *adapter = hw->back;
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s16 devctl2;
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u32 pollcnt;
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pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_CONTROL2,
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&devctl2);
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devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
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switch (devctl2) {
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case IXGBE_PCIDEVCTRL2_65_130ms:
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pollcnt = 1300; /* 130 millisec */
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break;
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case IXGBE_PCIDEVCTRL2_260_520ms:
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pollcnt = 5200; /* 520 millisec */
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break;
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case IXGBE_PCIDEVCTRL2_1_2s:
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pollcnt = 20000; /* 2 sec */
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break;
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case IXGBE_PCIDEVCTRL2_4_8s:
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pollcnt = 80000; /* 8 sec */
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break;
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case IXGBE_PCIDEVCTRL2_17_34s:
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pollcnt = 34000; /* 34 sec */
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break;
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case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
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case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
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case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
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case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
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default:
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pollcnt = 800; /* 80 millisec minimum */
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break;
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}
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/* add 10% to spec maximum */
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return (pollcnt * 11) / 10;
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}
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/**
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* ixgbe_disable_pcie_master - Disable PCI-express master access
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* @hw: pointer to hardware structure
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@ -2449,7 +2498,7 @@ static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
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{
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struct ixgbe_adapter *adapter = hw->back;
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s32 status = 0;
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u32 i;
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u32 i, poll;
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u16 value;
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/* Always set this bit to ensure any future transactions are blocked */
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@ -2481,7 +2530,8 @@ static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
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* Before proceeding, make sure that the PCIe block does not have
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* transactions pending.
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*/
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for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
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poll = ixgbe_pcie_timeout_poll(hw);
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for (i = 0; i < poll; i++) {
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udelay(100);
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pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
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&value);
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@ -1854,8 +1854,19 @@ enum {
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#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
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#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
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#define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf
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#define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0
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#define IXGBE_PCIDEVCTRL2_50_100us 0x1
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#define IXGBE_PCIDEVCTRL2_1_2ms 0x2
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#define IXGBE_PCIDEVCTRL2_16_32ms 0x5
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#define IXGBE_PCIDEVCTRL2_65_130ms 0x6
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#define IXGBE_PCIDEVCTRL2_260_520ms 0x9
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#define IXGBE_PCIDEVCTRL2_1_2s 0xa
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#define IXGBE_PCIDEVCTRL2_4_8s 0xd
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#define IXGBE_PCIDEVCTRL2_17_34s 0xe
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/* Number of 100 microseconds we wait for PCI Express master disable */
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#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
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#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
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/* RAH */
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#define IXGBE_RAH_VIND_MASK 0x003C0000
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