ARM: sun5i: gr8: Use common sun5i DTSI
Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of the extra nodes defined there actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it, and include the sun5i DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Maxime Ripard
parent
bea13693b2
commit
1f4ce3b6ca
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@ -171,7 +171,7 @@
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins>;
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pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
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status = "disabled";
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};
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@ -220,7 +220,7 @@
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
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pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;
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status = "okay";
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};
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@ -281,7 +281,7 @@
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pins_a>;
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pinctrl-0 = <&pwm0_pins>;
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status = "okay";
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};
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@ -332,7 +332,7 @@
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
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pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;
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status = "okay";
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};
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@ -42,429 +42,20 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "sun5i.dtsi"
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#include <dt-bindings/clock/sun5i-ccu.h>
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#include <dt-bindings/dma/sun4i-a10.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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#include <dt-bindings/reset/sun5i-ccu.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a8";
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reg = <0x0>;
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clocks = <&ccu CLK_CPU>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: clk@01c20050 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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};
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display-engine {
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compatible = "allwinner,sun5i-a13-display-engine";
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allwinner,pipelines = <&fe0>;
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};
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soc@01c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram-controller@01c00000 {
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compatible = "allwinner,sun4i-a10-sram-controller";
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reg = <0x01c00000 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_a: sram@00000000 {
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compatible = "mmio-sram";
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reg = <0x00000000 0xc000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00000000 0xc000>;
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};
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sram_d: sram@00010000 {
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compatible = "mmio-sram";
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reg = <0x00010000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00010000 0x1000>;
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otg_sram: sram-section@0000 {
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compatible = "allwinner,sun4i-a10-sram-d";
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reg = <0x0000 0x1000>;
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status = "disabled";
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};
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};
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};
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun4i-a10-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <27>;
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clocks = <&ccu CLK_AHB_DMA>;
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#dma-cells = <2>;
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};
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nfc: nand@01c03000 {
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compatible = "allwinner,sun4i-a10-nand";
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reg = <0x01c03000 0x1000>;
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interrupts = <37>;
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clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 3>;
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dma-names = "rxtx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi0: spi@01c05000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c05000 0x1000>;
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interrupts = <10>;
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clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 27>,
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<&dma SUN4I_DMA_DEDICATED 26>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@01c06000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c06000 0x1000>;
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interrupts = <11>;
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clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 9>,
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<&dma SUN4I_DMA_DEDICATED 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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tve0: tv-encoder@01c0a000 {
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compatible = "allwinner,sun4i-a10-tv-encoder";
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reg = <0x01c0a000 0x1000>;
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clocks = <&ccu CLK_AHB_TVE>;
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resets = <&ccu RST_TVE>;
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status = "disabled";
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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tve0_in_tcon0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_out_tve0>;
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};
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};
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};
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tcon0: lcd-controller@01c0c000 {
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compatible = "allwinner,sun5i-a13-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <44>;
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resets = <&ccu RST_LCD>;
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reset-names = "lcd";
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clocks = <&ccu CLK_AHB_LCD>,
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<&ccu CLK_TCON_CH0>,
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<&ccu CLK_TCON_CH1>;
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clock-names = "ahb",
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"tcon-ch0",
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"tcon-ch1";
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clock-output-names = "tcon-pixel-clock";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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tcon0_in_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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tcon0_out_tve0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&tve0_in_tcon0>;
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};
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};
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};
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};
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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interrupts = <32>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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interrupts = <33>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@01c11000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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interrupts = <34>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usb_otg: usb@01c13000 {
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compatible = "allwinner,sun4i-a10-musb";
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reg = <0x01c13000 0x0400>;
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clocks = <&ccu CLK_AHB_OTG>;
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interrupts = <38>;
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interrupt-names = "mc";
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phys = <&usbphy 0>;
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phy-names = "usb";
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extcon = <&usbphy 0>;
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allwinner,sram = <&otg_sram 1>;
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status = "disabled";
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dr_mode = "otg";
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};
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usbphy: phy@01c13400 {
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#phy-cells = <1>;
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compatible = "allwinner,sun5i-a13-usb-phy";
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reg = <0x01c13400 0x10 0x01c14800 0x4>;
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reg-names = "phy_ctrl", "pmu1";
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clocks = <&ccu CLK_USB_PHY0>;
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clock-names = "usb_phy";
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resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
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reset-names = "usb0_reset", "usb1_reset";
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status = "disabled";
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};
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ehci0: usb@01c14000 {
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compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
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reg = <0x01c14000 0x100>;
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interrupts = <39>;
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clocks = <&ccu CLK_AHB_EHCI>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci0: usb@01c14400 {
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compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
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reg = <0x01c14400 0x100>;
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interrupts = <40>;
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clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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spi2: spi@01c17000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c17000 0x1000>;
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interrupts = <12>;
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clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 29>,
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<&dma SUN4I_DMA_DEDICATED 28>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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ccu: clock@01c20000 {
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compatible = "nextthing,gr8-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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intc: interrupt-controller@01c20400 {
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compatible = "allwinner,sun4i-a10-ic";
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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pio: pinctrl@01c20800 {
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compatible = "nextthing,gr8-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <28>;
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clocks = <&ccu CLK_APB0_PIO>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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i2c0_pins_a: i2c0@0 {
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pins = "PB0", "PB1";
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function = "i2c0";
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};
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i2c1_pins_a: i2c1@0 {
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pins = "PB15", "PB16";
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function = "i2c1";
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};
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i2c2_pins_a: i2c2@0 {
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pins = "PB17", "PB18";
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function = "i2c2";
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};
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i2s0_data_pins_a: i2s0-data@0 {
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pins = "PB6", "PB7", "PB8", "PB9";
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function = "i2s0";
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};
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i2s0_mclk_pins_a: i2s0-mclk@0 {
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pins = "PB5";
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function = "i2s0";
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};
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ir0_rx_pins_a: ir0@0 {
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pins = "PB4";
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function = "ir0";
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};
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lcd_rgb666_pins: lcd-rgb666@0 {
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pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
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"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
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"PD24", "PD25", "PD26", "PD27";
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function = "lcd0";
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};
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mmc0_pins_a: mmc0@0 {
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pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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};
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nand_pins_a: nand-base0@0 {
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pins = "PC0", "PC1", "PC2",
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"PC5", "PC8", "PC9", "PC10",
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"PC11", "PC12", "PC13", "PC14",
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"PC15";
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function = "nand0";
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};
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nand_cs0_pins_a: nand-cs@0 {
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pins = "PC4";
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function = "nand0";
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};
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nand_rb0_pins_a: nand-rb@0 {
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pins = "PC6";
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function = "nand0";
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};
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pwm0_pins_a: pwm0@0 {
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pins = "PB2";
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function = "pwm0";
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};
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pwm1_pins: pwm1 {
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pins = "PG13";
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function = "pwm1";
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};
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spdif_tx_pins_a: spdif@0 {
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pins = "PB10";
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function = "spdif";
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bias-pull-up;
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};
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uart1_pins_a: uart1@1 {
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pins = "PG3", "PG4";
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function = "uart1";
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};
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uart1_cts_rts_pins_a: uart1-cts-rts@0 {
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pins = "PG5", "PG6";
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function = "uart1";
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};
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uart2_pins_a: uart2@1 {
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pins = "PD2", "PD3";
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function = "uart2";
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};
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uart2_cts_rts_pins_a: uart2-cts-rts@0 {
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pins = "PD4", "PD5";
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function = "uart2";
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};
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uart3_pins_a: uart3@1 {
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pins = "PG9", "PG10";
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function = "uart3";
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};
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uart3_cts_rts_pins_a: uart3-cts-rts@0 {
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pins = "PG11", "PG12";
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function = "uart3";
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};
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};
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pwm: pwm@01c20e00 {
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compatible = "allwinner,sun5i-a10s-pwm";
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reg = <0x01c20e00 0xc>;
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|
|
@ -473,18 +64,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@01c20c00 {
|
||||
compatible = "allwinner,sun4i-a10-timer";
|
||||
reg = <0x01c20c00 0x90>;
|
||||
interrupts = <22>;
|
||||
clocks = <&ccu CLK_HOSC>;
|
||||
};
|
||||
|
||||
wdt: watchdog@01c20c90 {
|
||||
compatible = "allwinner,sun4i-a10-wdt";
|
||||
reg = <0x01c20c90 0x10>;
|
||||
};
|
||||
|
||||
spdif: spdif@01c21000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-spdif";
|
||||
|
|
@ -498,15 +77,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ir0: ir@01c21800 {
|
||||
compatible = "allwinner,sun4i-a10-ir";
|
||||
clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
|
||||
clock-names = "apb", "ir";
|
||||
interrupts = <5>;
|
||||
reg = <0x01c21800 0x40>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s0: i2s@01c22400 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-i2s";
|
||||
|
|
@ -519,168 +89,39 @@
|
|||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lradc: lradc@01c22800 {
|
||||
compatible = "allwinner,sun4i-a10-lradc-keys";
|
||||
reg = <0x01c22800 0x100>;
|
||||
interrupts = <31>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
codec: codec@01c22c00 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-codec";
|
||||
reg = <0x01c22c00 0x40>;
|
||||
interrupts = <30>;
|
||||
clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
|
||||
clock-names = "apb", "codec";
|
||||
dmas = <&dma SUN4I_DMA_NORMAL 19>,
|
||||
<&dma SUN4I_DMA_NORMAL 19>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtp: rtp@01c25000 {
|
||||
compatible = "allwinner,sun5i-a13-ts";
|
||||
reg = <0x01c25000 0x100>;
|
||||
interrupts = <29>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
uart1: serial@01c28400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28400 0x400>;
|
||||
interrupts = <2>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&ccu CLK_APB1_UART1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@01c28800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28800 0x400>;
|
||||
interrupts = <3>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&ccu CLK_APB1_UART2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@01c28c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28c00 0x400>;
|
||||
interrupts = <4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&ccu CLK_APB1_UART3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@01c2ac00 {
|
||||
compatible = "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2ac00 0x400>;
|
||||
interrupts = <7>;
|
||||
clocks = <&ccu CLK_APB1_I2C0>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@01c2b000 {
|
||||
compatible = "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2b000 0x400>;
|
||||
interrupts = <8>;
|
||||
clocks = <&ccu CLK_APB1_I2C1>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@01c2b400 {
|
||||
compatible = "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2b400 0x400>;
|
||||
interrupts = <9>;
|
||||
clocks = <&ccu CLK_APB1_I2C2>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
timer@01c60000 {
|
||||
compatible = "allwinner,sun5i-a13-hstimer";
|
||||
reg = <0x01c60000 0x1000>;
|
||||
interrupts = <82>, <83>;
|
||||
clocks = <&ccu CLK_AHB_HSTIMER>;
|
||||
};
|
||||
|
||||
fe0: display-frontend@01e00000 {
|
||||
compatible = "allwinner,sun5i-a13-display-frontend";
|
||||
reg = <0x01e00000 0x20000>;
|
||||
interrupts = <47>;
|
||||
clocks = <&ccu CLK_AHB_DE_FE>, <&ccu CLK_DE_FE>,
|
||||
<&ccu CLK_DRAM_DE_FE>;
|
||||
clock-names = "ahb", "mod",
|
||||
"ram";
|
||||
resets = <&ccu RST_DE_FE>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fe0_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
fe0_out_be0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&be0_in_fe0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
be0: display-backend@01e60000 {
|
||||
compatible = "allwinner,sun5i-a13-display-backend";
|
||||
reg = <0x01e60000 0x10000>;
|
||||
clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
|
||||
<&ccu CLK_DRAM_DE_BE>;
|
||||
clock-names = "ahb", "mod",
|
||||
"ram";
|
||||
resets = <&ccu RST_DE_BE>;
|
||||
status = "disabled";
|
||||
|
||||
assigned-clocks = <&ccu CLK_DE_BE>;
|
||||
assigned-clock-rates = <300000000>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
be0_in: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
be0_in_fe0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&fe0_out_be0>;
|
||||
};
|
||||
&ccu {
|
||||
compatible = "nextthing,gr8-ccu";
|
||||
};
|
||||
|
||||
be0_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
&pio {
|
||||
compatible = "nextthing,gr8-pinctrl";
|
||||
|
||||
be0_out_tcon0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon0_in_be0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
i2s0_data_pins_a: i2s0-data@0 {
|
||||
pins = "PB6", "PB7", "PB8", "PB9";
|
||||
function = "i2s0";
|
||||
};
|
||||
|
||||
i2s0_mclk_pins_a: i2s0-mclk@0 {
|
||||
pins = "PB5";
|
||||
function = "i2s0";
|
||||
};
|
||||
|
||||
pwm1_pins: pwm1 {
|
||||
pins = "PG13";
|
||||
function = "pwm1";
|
||||
};
|
||||
|
||||
spdif_tx_pins_a: spdif@0 {
|
||||
pins = "PB10";
|
||||
function = "spdif";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
uart1_cts_rts_pins_a: uart1-cts-rts@0 {
|
||||
pins = "PG5", "PG6";
|
||||
function = "uart1";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -159,6 +159,19 @@
|
|||
#dma-cells = <2>;
|
||||
};
|
||||
|
||||
nfc: nand@01c03000 {
|
||||
compatible = "allwinner,sun4i-a10-nand";
|
||||
reg = <0x01c03000 0x1000>;
|
||||
interrupts = <37>;
|
||||
clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma SUN4I_DMA_DEDICATED 3>;
|
||||
dma-names = "rxtx";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi0: spi@01c05000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c05000 0x1000>;
|
||||
|
|
@ -406,6 +419,11 @@
|
|||
function = "i2c2";
|
||||
};
|
||||
|
||||
ir0_rx_pins_a: ir0@0 {
|
||||
pins = "PB4";
|
||||
function = "ir0";
|
||||
};
|
||||
|
||||
lcd_rgb565_pins: lcd_rgb565@0 {
|
||||
pins = "PD3", "PD4", "PD5", "PD6", "PD7",
|
||||
"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
|
||||
|
|
@ -447,6 +465,24 @@
|
|||
bias-pull-up;
|
||||
};
|
||||
|
||||
nand_pins_a: nand-base0@0 {
|
||||
pins = "PC0", "PC1", "PC2",
|
||||
"PC5", "PC8", "PC9", "PC10",
|
||||
"PC11", "PC12", "PC13", "PC14",
|
||||
"PC15";
|
||||
function = "nand0";
|
||||
};
|
||||
|
||||
nand_cs0_pins_a: nand-cs@0 {
|
||||
pins = "PC4";
|
||||
function = "nand0";
|
||||
};
|
||||
|
||||
nand_rb0_pins_a: nand-rb@0 {
|
||||
pins = "PC6";
|
||||
function = "nand0";
|
||||
};
|
||||
|
||||
spi2_pins_a: spi2@0 {
|
||||
pins = "PE1", "PE2", "PE3";
|
||||
function = "spi2";
|
||||
|
|
@ -505,6 +541,15 @@
|
|||
reg = <0x01c20c90 0x10>;
|
||||
};
|
||||
|
||||
ir0: ir@01c21800 {
|
||||
compatible = "allwinner,sun4i-a10-ir";
|
||||
clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
|
||||
clock-names = "apb", "ir";
|
||||
interrupts = <5>;
|
||||
reg = <0x01c21800 0x40>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lradc: lradc@01c22800 {
|
||||
compatible = "allwinner,sun4i-a10-lradc-keys";
|
||||
reg = <0x01c22800 0x100>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue