net: dsa: microchip: ptp: add periodic output signal
LAN937x and KSZ PTP supported switches has Three Trigger output unit. This TOU can used to generate the periodic signal for PTP. TOU has the cycle width register of 32 bit in size and period width register of 24 bit, each value is of 8ns so the pulse width can be maximum 125ms. Tested using ./testptp -d /dev/ptp0 -p 1000000000 -w 100000000 for generating the 10ms pulse width Signed-off-by: Christian Eggers <ceggers@arri.de> Co-developed-by: Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Christian Eggers
David S. Miller
parent
a32190b154
commit
1f12ae5b67
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@ -477,6 +477,19 @@ static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask,
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return ret;
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}
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static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask,
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u32 value)
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{
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int ret;
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ret = regmap_update_bits(dev->regmap[2], reg, mask, value);
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if (ret)
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dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg,
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ERR_PTR(ret));
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return ret;
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}
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static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
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{
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u32 val[2];
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@ -25,12 +25,210 @@
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* = (2^30-1) * (2 ^ 32) / 40 ns * 1 ns = 6249999
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*/
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#define KSZ_MAX_DRIFT_CORR 6249999
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#define KSZ_MAX_PULSE_WIDTH 125000000LL
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#define KSZ_PTP_INC_NS 40ULL /* HW clock is incremented every 40 ns (by 40) */
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#define KSZ_PTP_SUBNS_BITS 32
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#define KSZ_PTP_INT_START 13
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static int ksz_ptp_tou_reset(struct ksz_device *dev, u8 unit)
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{
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u32 data;
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int ret;
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/* Reset trigger unit (clears TRIGGER_EN, but not GPIOSTATx) */
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ret = ksz_rmw32(dev, REG_PTP_CTRL_STAT__4, TRIG_RESET, TRIG_RESET);
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data = FIELD_PREP(TRIG_DONE_M, BIT(unit));
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ret = ksz_write32(dev, REG_PTP_TRIG_STATUS__4, data);
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if (ret)
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return ret;
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data = FIELD_PREP(TRIG_INT_M, BIT(unit));
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ret = ksz_write32(dev, REG_PTP_INT_STATUS__4, data);
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if (ret)
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return ret;
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/* Clear reset and set GPIO direction */
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return ksz_rmw32(dev, REG_PTP_CTRL_STAT__4, (TRIG_RESET | TRIG_ENABLE),
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0);
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}
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static int ksz_ptp_tou_pulse_verify(u64 pulse_ns)
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{
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u32 data;
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if (pulse_ns & 0x3)
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return -EINVAL;
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data = (pulse_ns / 8);
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if (!FIELD_FIT(TRIG_PULSE_WIDTH_M, data))
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return -ERANGE;
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return 0;
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}
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static int ksz_ptp_tou_target_time_set(struct ksz_device *dev,
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struct timespec64 const *ts)
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{
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int ret;
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/* Hardware has only 32 bit */
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if ((ts->tv_sec & 0xffffffff) != ts->tv_sec)
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return -EINVAL;
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ret = ksz_write32(dev, REG_TRIG_TARGET_NANOSEC, ts->tv_nsec);
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if (ret)
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return ret;
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ret = ksz_write32(dev, REG_TRIG_TARGET_SEC, ts->tv_sec);
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if (ret)
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return ret;
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return 0;
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}
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static int ksz_ptp_tou_start(struct ksz_device *dev, u8 unit)
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{
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u32 data;
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int ret;
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ret = ksz_rmw32(dev, REG_PTP_CTRL_STAT__4, TRIG_ENABLE, TRIG_ENABLE);
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if (ret)
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return ret;
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/* Check error flag:
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* - the ACTIVE flag is NOT cleared an error!
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*/
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ret = ksz_read32(dev, REG_PTP_TRIG_STATUS__4, &data);
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if (ret)
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return ret;
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if (FIELD_GET(TRIG_ERROR_M, data) & (1 << unit)) {
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dev_err(dev->dev, "%s: Trigger unit%d error!\n", __func__,
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unit);
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ret = -EIO;
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/* Unit will be reset on next access */
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return ret;
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}
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return 0;
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}
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static int ksz_ptp_configure_perout(struct ksz_device *dev,
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u32 cycle_width_ns, u32 pulse_width_ns,
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struct timespec64 const *target_time,
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u8 index)
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{
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u32 data;
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int ret;
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data = FIELD_PREP(TRIG_NOTIFY, 1) |
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FIELD_PREP(TRIG_GPO_M, index) |
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FIELD_PREP(TRIG_PATTERN_M, TRIG_POS_PERIOD);
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ret = ksz_write32(dev, REG_TRIG_CTRL__4, data);
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if (ret)
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return ret;
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ret = ksz_write32(dev, REG_TRIG_CYCLE_WIDTH, cycle_width_ns);
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if (ret)
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return ret;
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/* Set cycle count 0 - Infinite */
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ret = ksz_rmw32(dev, REG_TRIG_CYCLE_CNT, TRIG_CYCLE_CNT_M, 0);
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if (ret)
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return ret;
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data = (pulse_width_ns / 8);
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ret = ksz_write32(dev, REG_TRIG_PULSE_WIDTH__4, data);
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if (ret)
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return ret;
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ret = ksz_ptp_tou_target_time_set(dev, target_time);
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if (ret)
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return ret;
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return 0;
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}
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static int ksz_ptp_enable_perout(struct ksz_device *dev,
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struct ptp_perout_request const *request,
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int on)
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{
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struct ksz_ptp_data *ptp_data = &dev->ptp_data;
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u64 req_pulse_width_ns;
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u64 cycle_width_ns;
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u64 pulse_width_ns;
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int pin = 0;
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u32 data32;
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int ret;
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if (request->flags & ~PTP_PEROUT_DUTY_CYCLE)
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return -EOPNOTSUPP;
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if (ptp_data->tou_mode != KSZ_PTP_TOU_PEROUT &&
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ptp_data->tou_mode != KSZ_PTP_TOU_IDLE)
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return -EBUSY;
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data32 = FIELD_PREP(PTP_GPIO_INDEX, pin) |
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FIELD_PREP(PTP_TOU_INDEX, request->index);
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ret = ksz_rmw32(dev, REG_PTP_UNIT_INDEX__4,
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PTP_GPIO_INDEX | PTP_TOU_INDEX, data32);
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if (ret)
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return ret;
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ret = ksz_ptp_tou_reset(dev, request->index);
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if (ret)
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return ret;
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if (!on) {
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ptp_data->tou_mode = KSZ_PTP_TOU_IDLE;
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return 0;
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}
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ptp_data->perout_target_time_first.tv_sec = request->start.sec;
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ptp_data->perout_target_time_first.tv_nsec = request->start.nsec;
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ptp_data->perout_period.tv_sec = request->period.sec;
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ptp_data->perout_period.tv_nsec = request->period.nsec;
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cycle_width_ns = timespec64_to_ns(&ptp_data->perout_period);
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if ((cycle_width_ns & TRIG_CYCLE_WIDTH_M) != cycle_width_ns)
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return -EINVAL;
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if (request->flags & PTP_PEROUT_DUTY_CYCLE) {
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pulse_width_ns = request->on.sec * NSEC_PER_SEC +
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request->on.nsec;
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} else {
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/* Use a duty cycle of 50%. Maximum pulse width supported by the
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* hardware is a little bit more than 125 ms.
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*/
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req_pulse_width_ns = (request->period.sec * NSEC_PER_SEC +
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request->period.nsec) / 2;
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pulse_width_ns = min_t(u64, req_pulse_width_ns,
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KSZ_MAX_PULSE_WIDTH);
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}
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ret = ksz_ptp_tou_pulse_verify(pulse_width_ns);
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if (ret)
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return ret;
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ret = ksz_ptp_configure_perout(dev, cycle_width_ns, pulse_width_ns,
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&ptp_data->perout_target_time_first,
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pin);
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if (ret)
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return ret;
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ret = ksz_ptp_tou_start(dev, request->index);
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if (ret)
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return ret;
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ptp_data->tou_mode = KSZ_PTP_TOU_PEROUT;
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return 0;
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}
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static int ksz_ptp_enable_mode(struct ksz_device *dev)
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{
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struct ksz_tagger_data *tagger_data = ksz_tagger_data(dev->ds);
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@ -368,6 +566,51 @@ static int ksz_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
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return ret;
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}
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static int ksz_ptp_restart_perout(struct ksz_device *dev)
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{
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struct ksz_ptp_data *ptp_data = &dev->ptp_data;
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s64 now_ns, first_ns, period_ns, next_ns;
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struct ptp_perout_request request;
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struct timespec64 next;
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struct timespec64 now;
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unsigned int count;
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int ret;
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dev_info(dev->dev, "Restarting periodic output signal\n");
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ret = _ksz_ptp_gettime(dev, &now);
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if (ret)
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return ret;
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now_ns = timespec64_to_ns(&now);
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first_ns = timespec64_to_ns(&ptp_data->perout_target_time_first);
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/* Calculate next perout event based on start time and period */
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period_ns = timespec64_to_ns(&ptp_data->perout_period);
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if (first_ns < now_ns) {
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count = div_u64(now_ns - first_ns, period_ns);
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next_ns = first_ns + count * period_ns;
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} else {
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next_ns = first_ns;
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}
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/* Ensure 100 ms guard time prior next event */
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while (next_ns < now_ns + 100000000)
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next_ns += period_ns;
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/* Restart periodic output signal */
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next = ns_to_timespec64(next_ns);
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request.start.sec = next.tv_sec;
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request.start.nsec = next.tv_nsec;
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request.period.sec = ptp_data->perout_period.tv_sec;
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request.period.nsec = ptp_data->perout_period.tv_nsec;
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request.index = 0;
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request.flags = 0;
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return ksz_ptp_enable_perout(dev, &request, 1);
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}
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static int ksz_ptp_settime(struct ptp_clock_info *ptp,
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const struct timespec64 *ts)
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{
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@ -394,6 +637,18 @@ static int ksz_ptp_settime(struct ptp_clock_info *ptp,
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if (ret)
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goto unlock;
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switch (ptp_data->tou_mode) {
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case KSZ_PTP_TOU_IDLE:
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break;
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case KSZ_PTP_TOU_PEROUT:
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ret = ksz_ptp_restart_perout(dev);
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if (ret)
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goto unlock;
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break;
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}
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spin_lock_bh(&ptp_data->clock_lock);
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ptp_data->clock_time = *ts;
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spin_unlock_bh(&ptp_data->clock_lock);
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@ -483,6 +738,18 @@ static int ksz_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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if (ret)
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goto unlock;
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switch (ptp_data->tou_mode) {
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case KSZ_PTP_TOU_IDLE:
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break;
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case KSZ_PTP_TOU_PEROUT:
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ret = ksz_ptp_restart_perout(dev);
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if (ret)
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goto unlock;
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break;
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}
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spin_lock_bh(&ptp_data->clock_lock);
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ptp_data->clock_time = timespec64_add(ptp_data->clock_time, delta64);
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spin_unlock_bh(&ptp_data->clock_lock);
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@ -492,6 +759,26 @@ unlock:
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return ret;
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}
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static int ksz_ptp_enable(struct ptp_clock_info *ptp,
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struct ptp_clock_request *req, int on)
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{
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struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp);
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struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data);
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int ret;
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switch (req->type) {
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case PTP_CLK_REQ_PEROUT:
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mutex_lock(&ptp_data->lock);
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ret = ksz_ptp_enable_perout(dev, &req->perout, on);
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mutex_unlock(&ptp_data->lock);
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break;
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default:
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return -EOPNOTSUPP;
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}
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return ret;
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}
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/* Function is pointer to the do_aux_work in the ptp_clock capability */
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static long ksz_ptp_do_aux_work(struct ptp_clock_info *ptp)
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{
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@ -548,6 +835,8 @@ int ksz_ptp_clock_register(struct dsa_switch *ds)
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ptp_data->caps.adjfine = ksz_ptp_adjfine;
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ptp_data->caps.adjtime = ksz_ptp_adjtime;
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ptp_data->caps.do_aux_work = ksz_ptp_do_aux_work;
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ptp_data->caps.enable = ksz_ptp_enable;
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ptp_data->caps.n_per_out = 3;
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ret = ksz_ptp_start_clock(dev);
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if (ret)
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@ -12,6 +12,11 @@
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#include <linux/ptp_clock_kernel.h>
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enum ksz_ptp_tou_mode {
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KSZ_PTP_TOU_IDLE,
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KSZ_PTP_TOU_PEROUT,
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};
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struct ksz_ptp_data {
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struct ptp_clock_info caps;
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struct ptp_clock *clock;
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@ -20,6 +25,9 @@ struct ksz_ptp_data {
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/* lock for accessing the clock_time */
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spinlock_t clock_lock;
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struct timespec64 clock_time;
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enum ksz_ptp_tou_mode tou_mode;
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struct timespec64 perout_target_time_first; /* start of first pulse */
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struct timespec64 perout_period;
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};
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int ksz_ptp_clock_register(struct dsa_switch *ds);
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@ -49,6 +49,69 @@
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#define PTP_MASTER BIT(1)
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#define PTP_1STEP BIT(0)
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#define REG_PTP_UNIT_INDEX__4 0x0520
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#define PTP_GPIO_INDEX GENMASK(19, 16)
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#define PTP_TSI_INDEX BIT(8)
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#define PTP_TOU_INDEX GENMASK(1, 0)
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#define REG_PTP_TRIG_STATUS__4 0x0524
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#define TRIG_ERROR_M GENMASK(18, 16)
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#define TRIG_DONE_M GENMASK(2, 0)
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#define REG_PTP_INT_STATUS__4 0x0528
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#define TRIG_INT_M GENMASK(18, 16)
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#define TS_INT_M GENMASK(1, 0)
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#define REG_PTP_CTRL_STAT__4 0x052C
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#define GPIO_IN BIT(7)
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#define GPIO_OUT BIT(6)
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#define TS_INT_ENABLE BIT(5)
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#define TRIG_ACTIVE BIT(4)
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#define TRIG_ENABLE BIT(3)
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#define TRIG_RESET BIT(2)
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#define TS_ENABLE BIT(1)
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#define TS_RESET BIT(0)
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#define REG_TRIG_TARGET_NANOSEC 0x0530
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#define REG_TRIG_TARGET_SEC 0x0534
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#define REG_TRIG_CTRL__4 0x0538
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#define TRIG_CASCADE_ENABLE BIT(31)
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#define TRIG_CASCADE_TAIL BIT(30)
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#define TRIG_CASCADE_UPS_M GENMASK(29, 26)
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#define TRIG_NOW BIT(25)
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#define TRIG_NOTIFY BIT(24)
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#define TRIG_EDGE BIT(23)
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#define TRIG_PATTERN_M GENMASK(22, 20)
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#define TRIG_NEG_EDGE 0
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#define TRIG_POS_EDGE 1
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#define TRIG_NEG_PULSE 2
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#define TRIG_POS_PULSE 3
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#define TRIG_NEG_PERIOD 4
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#define TRIG_POS_PERIOD 5
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#define TRIG_REG_OUTPUT 6
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#define TRIG_GPO_M GENMASK(19, 16)
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#define TRIG_CASCADE_ITERATE_CNT_M GENMASK(15, 0)
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#define REG_TRIG_CYCLE_WIDTH 0x053C
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#define TRIG_CYCLE_WIDTH_M GENMASK(31, 0)
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#define REG_TRIG_CYCLE_CNT 0x0540
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#define TRIG_CYCLE_CNT_M GENMASK(31, 16)
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#define TRIG_BIT_PATTERN_M GENMASK(15, 0)
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#define REG_TRIG_ITERATE_TIME 0x0544
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#define REG_TRIG_PULSE_WIDTH__4 0x0548
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#define TRIG_PULSE_WIDTH_M GENMASK(23, 0)
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/* Port PTP Register */
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#define REG_PTP_PORT_RX_DELAY__2 0x0C00
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#define REG_PTP_PORT_TX_DELAY__2 0x0C02
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|
|
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Loading…
Reference in New Issue