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pinctrl: renesas: Updates for v5.18 (take two) 

- Share more pin group data, to reduce kernel size and ease review,
   - Improve the pin control table validator,
   - Add support for the new R-Car S4-8 SoC,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-pinctrl-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.18 (take two)

  - Share more pin group data, to reduce kernel size and ease review,
  - Improve the pin control table validator,
  - Add support for the new R-Car S4-8 SoC,
  - Miscellaneous fixes and improvements.
This commit is contained in:
Linus Walleij 2022-02-27 02:18:54 +01:00
parent 4649b97042 babe298e9c
commit 1f02c8efa1
32 changed files with 3919 additions and 3130 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
View File

@ -44,6 +44,7 @@ properties:
- renesas,pfc-r8a77990 # R-Car E3
- renesas,pfc-r8a77995 # R-Car D3
- renesas,pfc-r8a779a0 # R-Car V3U
- renesas,pfc-r8a779f0 # R-Car S4-8
- renesas,pfc-sh73a0 # SH-Mobile AG5
reg:

5
drivers/pinctrl/renesas/Kconfig
View File

@ -37,6 +37,7 @@ config PINCTRL_RENESAS
select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0
select PINCTRL_RZG2L if ARCH_R9A07G044
select PINCTRL_RZG2L if ARCH_R9A07G054
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
@ -133,6 +134,10 @@ config PINCTRL_PFC_R8A77961
bool "pin control support for R-Car M3-W+" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A779F0
bool "pin control support for R-Car S4-8" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7792
bool "pin control support for R-Car V2H" if COMPILE_TEST
select PINCTRL_SH_PFC

1
drivers/pinctrl/renesas/Makefile
View File

@ -30,6 +30,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o

219
drivers/pinctrl/renesas/core.c
View File

@ -636,6 +636,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
.data = &r8a779a0_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A779F0
{
.compatible = "renesas,pfc-r8a779f0",
.data = &r8a779f0_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
{
.compatible = "renesas,pfc-sh73a0",
@ -741,10 +747,13 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
#ifdef DEBUG
#define SH_PFC_MAX_REGS 300
#define SH_PFC_MAX_ENUMS 3000
#define SH_PFC_MAX_ENUMS 5000
static unsigned int sh_pfc_errors __initdata;
static unsigned int sh_pfc_warnings __initdata;
static bool sh_pfc_bias_done __initdata;
static bool sh_pfc_drive_done __initdata;
static bool sh_pfc_power_done __initdata;
static struct {
u32 reg;
u32 bits;
@ -758,6 +767,15 @@ static u32 sh_pfc_num_enums __initdata;
pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \
sh_pfc_errors++; \
} while (0)
#define sh_pfc_err_once(type, fmt, ...) \
do { \
if (!sh_pfc_ ## type ## _done) { \
sh_pfc_ ## type ## _done = true; \
sh_pfc_err(fmt, ##__VA_ARGS__); \
} \
} while (0)
#define sh_pfc_warn(fmt, ...) \
do { \
pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \
@ -777,10 +795,7 @@ static bool __init is0s(const u16 *enum_ids, unsigned int n)
static bool __init same_name(const char *a, const char *b)
{
if (!a || !b)
return false;
return !strcmp(a, b);
return a && b && !strcmp(a, b);
}
static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits)
@ -839,21 +854,22 @@ static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg,
}
}
static void __init sh_pfc_check_pin(const struct sh_pfc_soc_info *info,
u32 reg, unsigned int pin)
static const struct sh_pfc_pin __init *sh_pfc_find_pin(
const struct sh_pfc_soc_info *info, u32 reg, unsigned int pin)
{
const char *drvname = info->name;
unsigned int i;
if (pin == SH_PFC_PIN_NONE)
return;
return NULL;
for (i = 0; i < info->nr_pins; i++) {
if (pin == info->pins[i].pin)
return;
return &info->pins[i];
}
sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);
return NULL;
}
static void __init sh_pfc_check_cfg_reg(const char *drvname,
@ -865,7 +881,8 @@ static void __init sh_pfc_check_cfg_reg(const char *drvname,
GENMASK(cfg_reg->reg_width - 1, 0));
if (cfg_reg->field_width) {
n = cfg_reg->reg_width / cfg_reg->field_width;
fw = cfg_reg->field_width;
n = (cfg_reg->reg_width / fw) << fw;
/* Skip field checks (done at build time) */
goto check_enum_ids;
}
@ -893,6 +910,8 @@ check_enum_ids:
static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
const struct pinmux_drive_reg *drive)
{
const char *drvname = info->name;
const struct sh_pfc_pin *pin;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
@ -905,13 +924,18 @@ static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
GENMASK(field->offset + field->size - 1,
field->offset));
sh_pfc_check_pin(info, drive->reg, field->pin);
pin = sh_pfc_find_pin(info, drive->reg, field->pin);
if (pin && !(pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH))
sh_pfc_err("drive_reg 0x%x: field %u: pin %s lacks SH_PFC_PIN_CFG_DRIVE_STRENGTH flag\n",
drive->reg, i, pin->name);
}
}
static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
const struct pinmux_bias_reg *bias)
{
const char *drvname = info->name;
const struct sh_pfc_pin *pin;
unsigned int i;
u32 bits;
@ -923,12 +947,66 @@ static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
sh_pfc_check_reg(info->name, bias->puen, bits);
if (bias->pud)
sh_pfc_check_reg(info->name, bias->pud, bits);
for (i = 0; i < ARRAY_SIZE(bias->pins); i++)
sh_pfc_check_pin(info, bias->puen, bias->pins[i]);
for (i = 0; i < ARRAY_SIZE(bias->pins); i++) {
pin = sh_pfc_find_pin(info, bias->puen, bias->pins[i]);
if (!pin)
continue;
if (bias->puen && bias->pud) {
/*
* Pull-enable and pull-up/down control registers
* As some SoCs have pins that support only pull-up
* or pull-down, we just check for one of them
*/
if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN))
sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks one or more SH_PFC_PIN_CFG_PULL_* flags\n",
bias->puen, i, pin->name);
} else if (bias->puen) {
/* Pull-up control register only */
if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP))
sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_UP flag\n",
bias->puen, i, pin->name);
} else if (bias->pud) {
/* Pull-down control register only */
if (!(pin->configs & SH_PFC_PIN_CFG_PULL_DOWN))
sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_DOWN flag\n",
bias->pud, i, pin->name);
}
}
}
static void __init sh_pfc_compare_groups(const char *drvname,
const struct sh_pfc_pin_group *a,
const struct sh_pfc_pin_group *b)
{
unsigned int i;
size_t len;
if (same_name(a->name, b->name))
sh_pfc_err("group %s: name conflict\n", a->name);
if (a->nr_pins > b->nr_pins)
swap(a, b);
len = a->nr_pins * sizeof(a->pins[0]);
for (i = 0; i <= b->nr_pins - a->nr_pins; i++) {
if (a->pins == b->pins + i || a->mux == b->mux + i ||
memcmp(a->pins, b->pins + i, len) ||
memcmp(a->mux, b->mux + i, len))
continue;
if (a->nr_pins == b->nr_pins)
sh_pfc_warn("group %s can be an alias for %s\n",
a->name, b->name);
else
sh_pfc_warn("group %s is a subset of %s\n", a->name,
b->name);
}
}
static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
{
const struct pinmux_drive_reg *drive_regs = info->drive_regs;
const struct pinmux_bias_reg *bias_regs = info->bias_regs;
const char *drvname = info->name;
unsigned int *refcnts;
@ -937,10 +1015,14 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
pr_info("sh_pfc: Checking %s\n", drvname);
sh_pfc_num_regs = 0;
sh_pfc_num_enums = 0;
sh_pfc_bias_done = false;
sh_pfc_drive_done = false;
sh_pfc_power_done = false;
/* Check pins */
for (i = 0; i < info->nr_pins; i++) {
const struct sh_pfc_pin *pin = &info->pins[i];
unsigned int x;
if (!pin->name) {
sh_pfc_err("empty pin %u\n", i);
@ -962,6 +1044,65 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
pin->name, pin2->name,
pin->enum_id);
}
if (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) {
if (!info->ops || !info->ops->get_bias ||
!info->ops->set_bias)
sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_* flag set but .[gs]et_bias() not implemented\n");
if (!bias_regs &&
(!info->ops || !info->ops->pin_to_portcr))
sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_UP flag set but no bias_regs defined and .pin_to_portcr() not implemented\n");
}
if ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) {
const struct pinmux_bias_reg *bias_reg =
rcar_pin_to_bias_reg(info, pin->pin, &x);
if (!bias_reg ||
((pin->configs & SH_PFC_PIN_CFG_PULL_UP) &&
!bias_reg->puen))
sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs\n",
pin->name);
if (!bias_reg ||
((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) &&
!bias_reg->pud))
sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs\n",
pin->name);
}
if (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) {
if (!drive_regs) {
sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n");
} else {
for (j = 0; drive_regs[j / 8].reg; j++) {
if (!drive_regs[j / 8].fields[j % 8].pin &&
!drive_regs[j / 8].fields[j % 8].offset &&
!drive_regs[j / 8].fields[j % 8].size)
continue;
if (drive_regs[j / 8].fields[j % 8].pin == pin->pin)
break;
}
if (!drive_regs[j / 8].reg)
sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n",
pin->name);
}
}
if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) {
if (!info->ops || !info->ops->pin_to_pocctrl)
sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\n");
else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0)
sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n",
pin->name);
} else if (info->ops && info->ops->pin_to_pocctrl &&
info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) {
sh_pfc_warn("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE not set but valid pin_to_pocctrl()\n",
pin->name);
}
}
/* Check groups and functions */
@ -1003,11 +1144,9 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
sh_pfc_err("empty group %u\n", i);
continue;
}
for (j = 0; j < i; j++) {
if (same_name(group->name, info->groups[j].name))
sh_pfc_err("group %s: name conflict\n",
group->name);
}
for (j = 0; j < i; j++)
sh_pfc_compare_groups(drvname, group, &info->groups[j]);
if (!refcnts[i])
sh_pfc_err("orphan group %s\n", group->name);
else if (refcnts[i] > 1)
@ -1022,13 +1161,53 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
/* Check drive strength registers */
for (i = 0; info->drive_regs && info->drive_regs[i].reg; i++)
sh_pfc_check_drive_reg(info, &info->drive_regs[i]);
for (i = 0; drive_regs && drive_regs[i].reg; i++)
sh_pfc_check_drive_reg(info, &drive_regs[i]);
for (i = 0; drive_regs && drive_regs[i / 8].reg; i++) {
if (!drive_regs[i / 8].fields[i % 8].pin &&
!drive_regs[i / 8].fields[i % 8].offset &&
!drive_regs[i / 8].fields[i % 8].size)
continue;
for (j = 0; j < i; j++) {
if (drive_regs[i / 8].fields[i % 8].pin ==
drive_regs[j / 8].fields[j % 8].pin &&
drive_regs[j / 8].fields[j % 8].offset &&
drive_regs[j / 8].fields[j % 8].size) {
sh_pfc_err("drive_reg 0x%x:%u/0x%x:%u: pin conflict\n",
drive_regs[i / 8].reg, i % 8,
drive_regs[j / 8].reg, j % 8);
}
}
}
/* Check bias registers */
for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++)
sh_pfc_check_bias_reg(info, &bias_regs[i]);
for (i = 0; bias_regs &&
(bias_regs[i / 32].puen || bias_regs[i / 32].pud); i++) {
if (bias_regs[i / 32].pins[i % 32] == SH_PFC_PIN_NONE)
continue;
for (j = 0; j < i; j++) {
if (bias_regs[i / 32].pins[i % 32] !=
bias_regs[j / 32].pins[j % 32])
continue;
if (bias_regs[i / 32].puen && bias_regs[j / 32].puen)
sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n",
bias_regs[i / 32].puen, i % 32,
bias_regs[j / 32].puen, j % 32);
if (bias_regs[i / 32].pud && bias_regs[j / 32].pud)
sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n",
bias_regs[i / 32].pud, i % 32,
bias_regs[j / 32].pud, j % 32);
}
}
/* Check ioctrl registers */
for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX);

71
drivers/pinctrl/renesas/pfc-emev2.c
View File

@ -749,23 +749,14 @@ static const unsigned int cf_ctrl_mux[] = {
CF_CDB2_MARK,
};
static const unsigned int cf_data8_pins[] = {
/* CF_D[0:7] */
77, 78, 79, 80,
81, 82, 83, 84,
};
static const unsigned int cf_data8_mux[] = {
CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
};
static const unsigned int cf_data16_pins[] = {
static const unsigned int cf_data_pins[] = {
/* CF_D[0:15] */
77, 78, 79, 80,
81, 82, 83, 84,
85, 86, 87, 88,
89, 90, 91, 92,
};
static const unsigned int cf_data16_mux[] = {
static const unsigned int cf_data_mux[] = {
CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
@ -895,26 +886,12 @@ static const unsigned int sdi0_ctrl_mux[] = {
SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK,
};
static const unsigned int sdi0_data1_pins[] = {
/* SDI0_DATA[0] */
53,
};
static const unsigned int sdi0_data1_mux[] = {
SDI0_DATA0_MARK,
};
static const unsigned int sdi0_data4_pins[] = {
/* SDI0_DATA[0:3] */
53, 54, 55, 56,
};
static const unsigned int sdi0_data4_mux[] = {
SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
};
static const unsigned int sdi0_data8_pins[] = {
static const unsigned int sdi0_data_pins[] = {
/* SDI0_DATA[0:7] */
53, 54, 55, 56,
57, 58, 59, 60
};
static const unsigned int sdi0_data8_mux[] = {
static const unsigned int sdi0_data_mux[] = {
SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK,
};
@ -928,18 +905,11 @@ static const unsigned int sdi1_ctrl_mux[] = {
SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK,
};
static const unsigned int sdi1_data1_pins[] = {
/* SDI1_DATA[0] */
64,
};
static const unsigned int sdi1_data1_mux[] = {
SDI1_DATA0_MARK,
};
static const unsigned int sdi1_data4_pins[] = {
static const unsigned int sdi1_data_pins[] = {
/* SDI1_DATA[0:3] */
64, 65, 66, 67,
};
static const unsigned int sdi1_data4_mux[] = {
static const unsigned int sdi1_data_mux[] = {
SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
};
@ -952,18 +922,11 @@ static const unsigned int sdi2_ctrl_mux[] = {
SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
};
static const unsigned int sdi2_data1_pins[] = {
/* SDI2_DATA[0] */
89,
};
static const unsigned int sdi2_data1_mux[] = {
SDI2_DATA0_MARK,
};
static const unsigned int sdi2_data4_pins[] = {
static const unsigned int sdi2_data_pins[] = {
/* SDI2_DATA[0:3] */
89, 90, 91, 92,
};
static const unsigned int sdi2_data4_mux[] = {
static const unsigned int sdi2_data_mux[] = {
SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK,
};
@ -1131,8 +1094,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(cam),
SH_PFC_PIN_GROUP(cf_ctrl),
SH_PFC_PIN_GROUP(cf_data8),
SH_PFC_PIN_GROUP(cf_data16),
BUS_DATA_PIN_GROUP(cf_data, 8),
BUS_DATA_PIN_GROUP(cf_data, 16),
SH_PFC_PIN_GROUP(dtv_a),
SH_PFC_PIN_GROUP(dtv_b),
@ -1161,17 +1124,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(sd_cki),
SH_PFC_PIN_GROUP(sdi0_ctrl),
SH_PFC_PIN_GROUP(sdi0_data1),
SH_PFC_PIN_GROUP(sdi0_data4),
SH_PFC_PIN_GROUP(sdi0_data8),
BUS_DATA_PIN_GROUP(sdi0_data, 1),
BUS_DATA_PIN_GROUP(sdi0_data, 4),
BUS_DATA_PIN_GROUP(sdi0_data, 8),
SH_PFC_PIN_GROUP(sdi1_ctrl),
SH_PFC_PIN_GROUP(sdi1_data1),
SH_PFC_PIN_GROUP(sdi1_data4),
BUS_DATA_PIN_GROUP(sdi1_data, 1),
BUS_DATA_PIN_GROUP(sdi1_data, 4),
SH_PFC_PIN_GROUP(sdi2_ctrl),
SH_PFC_PIN_GROUP(sdi2_data1),
SH_PFC_PIN_GROUP(sdi2_data4),
BUS_DATA_PIN_GROUP(sdi2_data, 1),
BUS_DATA_PIN_GROUP(sdi2_data, 4),
SH_PFC_PIN_GROUP(tp33),

97
drivers/pinctrl/renesas/pfc-r8a73a4.c
View File

@ -1449,25 +1449,11 @@ IRQC_PINS_MUX(327, 55);
IRQC_PINS_MUX(328, 56);
IRQC_PINS_MUX(329, 57);
/* - MMCIF0 ----------------------------------------------------------------- */
static const unsigned int mmc0_data1_pins[] = {
/* D[0] */
164,
};
static const unsigned int mmc0_data1_mux[] = {
MMCD0_0_MARK,
};
static const unsigned int mmc0_data4_pins[] = {
/* D[0:3] */
164, 165, 166, 167,
};
static const unsigned int mmc0_data4_mux[] = {
MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
};
static const unsigned int mmc0_data8_pins[] = {
static const unsigned int mmc0_data_pins[] = {
/* D[0:7] */
164, 165, 166, 167, 168, 169, 170, 171,
};
static const unsigned int mmc0_data8_mux[] = {
static const unsigned int mmc0_data_mux[] = {
MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
};
@ -1479,25 +1465,11 @@ static const unsigned int mmc0_ctrl_mux[] = {
MMCCMD0_MARK, MMCCLK0_MARK,
};
/* - MMCIF1 ----------------------------------------------------------------- */
static const unsigned int mmc1_data1_pins[] = {
/* D[0] */
199,
};
static const unsigned int mmc1_data1_mux[] = {
MMCD1_0_MARK,
};
static const unsigned int mmc1_data4_pins[] = {
/* D[0:3] */
199, 198, 197, 196,
};
static const unsigned int mmc1_data4_mux[] = {
MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
};
static const unsigned int mmc1_data8_pins[] = {
static const unsigned int mmc1_data_pins[] = {
/* D[0:7] */
199, 198, 197, 196, 195, 194, 193, 192,
};
static const unsigned int mmc1_data8_mux[] = {
static const unsigned int mmc1_data_mux[] = {
MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
};
@ -1704,18 +1676,11 @@ static const unsigned int scifb3_ctrl_b_mux[] = {
SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
302,
};
static const unsigned int sdhi0_data1_mux[] = {
SDHID0_0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
302, 303, 304, 305,
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
@ -1740,18 +1705,11 @@ static const unsigned int sdhi0_wp_mux[] = {
SDHIWP0_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
289,
};
static const unsigned int sdhi1_data1_mux[] = {
SDHID1_0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
289, 290, 291, 292,
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
@ -1762,18 +1720,11 @@ static const unsigned int sdhi1_ctrl_mux[] = {
SDHICLK1_MARK, SDHICMD1_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
295,
};
static const unsigned int sdhi2_data1_mux[] = {
SDHID2_0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:3] */
295, 296, 297, 298,
};
static const unsigned int sdhi2_data4_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
@ -1843,13 +1794,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(irqc_irq55),
SH_PFC_PIN_GROUP(irqc_irq56),
SH_PFC_PIN_GROUP(irqc_irq57),
SH_PFC_PIN_GROUP(mmc0_data1),
SH_PFC_PIN_GROUP(mmc0_data4),
SH_PFC_PIN_GROUP(mmc0_data8),
BUS_DATA_PIN_GROUP(mmc0_data, 1),
BUS_DATA_PIN_GROUP(mmc0_data, 4),
BUS_DATA_PIN_GROUP(mmc0_data, 8),
SH_PFC_PIN_GROUP(mmc0_ctrl),
SH_PFC_PIN_GROUP(mmc1_data1),
SH_PFC_PIN_GROUP(mmc1_data4),
SH_PFC_PIN_GROUP(mmc1_data8),
BUS_DATA_PIN_GROUP(mmc1_data, 1),
BUS_DATA_PIN_GROUP(mmc1_data, 4),
BUS_DATA_PIN_GROUP(mmc1_data, 8),
SH_PFC_PIN_GROUP(mmc1_ctrl),
SH_PFC_PIN_GROUP(scifa0_data),
SH_PFC_PIN_GROUP(scifa0_clk),
@ -1878,16 +1829,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scifb3_data_b),
SH_PFC_PIN_GROUP(scifb3_clk_b),
SH_PFC_PIN_GROUP(scifb3_ctrl_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
};
@ -2655,9 +2606,9 @@ static const unsigned int r8a73a4_portcr_offsets[] = {
0x00002000, 0x00003000, 0x00003000,
};
static void __iomem *r8a73a4_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
static int r8a73a4_pin_to_portcr(unsigned int pin)
{
return pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
return r8a73a4_portcr_offsets[pin >> 5] + pin;
}
static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {

282
drivers/pinctrl/renesas/pfc-r8a7740.c
View File

@ -1638,33 +1638,14 @@ static const struct sh_pfc_pin pinmux_pins[] = {
};
/* - BSC -------------------------------------------------------------------- */
static const unsigned int bsc_data8_pins[] = {
/* D[0:7] */
157, 156, 155, 154, 153, 152, 151, 150,
};
static const unsigned int bsc_data8_mux[] = {
D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
};
static const unsigned int bsc_data16_pins[] = {
/* D[0:15] */
157, 156, 155, 154, 153, 152, 151, 150,
149, 148, 147, 146, 145, 144, 143, 142,
};
static const unsigned int bsc_data16_mux[] = {
D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
};
static const unsigned int bsc_data32_pins[] = {
static const unsigned int bsc_data_pins[] = {
/* D[0:31] */
157, 156, 155, 154, 153, 152, 151, 150,
149, 148, 147, 146, 145, 144, 143, 142,
171, 170, 169, 168, 167, 166, 173, 172,
165, 164, 163, 162, 161, 160, 159, 158,
};
static const unsigned int bsc_data32_mux[] = {
static const unsigned int bsc_data_mux[] = {
D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
@ -1723,25 +1704,11 @@ static const unsigned int bsc_cs6a_pins[] = {
static const unsigned int bsc_cs6a_mux[] = {
CS6A_MARK,
};
static const unsigned int bsc_rd_we8_pins[] = {
/* RD, WE[0] */
115, 113,
};
static const unsigned int bsc_rd_we8_mux[] = {
RD_FSC_MARK, WE0_FWE_MARK,
};
static const unsigned int bsc_rd_we16_pins[] = {
/* RD, WE[0:1] */
115, 113, 112,
};
static const unsigned int bsc_rd_we16_mux[] = {
RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
};
static const unsigned int bsc_rd_we32_pins[] = {
static const unsigned int bsc_rd_we_pins[] = {
/* RD, WE[0:3] */
115, 113, 112, 108, 107,
};
static const unsigned int bsc_rd_we32_mux[] = {
static const unsigned int bsc_rd_we_mux[] = {
RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
};
static const unsigned int bsc_bs_pins[] = {
@ -2064,58 +2031,6 @@ IRQC_PINS_MUX(31, 0, 41);
IRQC_PINS_MUX(31, 1, 167);
/* - LCD0 ------------------------------------------------------------------- */
static const unsigned int lcd0_data8_pins[] = {
/* D[0:7] */
58, 57, 56, 55, 54, 53, 52, 51,
};
static const unsigned int lcd0_data8_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
};
static const unsigned int lcd0_data9_pins[] = {
/* D[0:8] */
58, 57, 56, 55, 54, 53, 52, 51,
50,
};
static const unsigned int lcd0_data9_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK,
};
static const unsigned int lcd0_data12_pins[] = {
/* D[0:11] */
58, 57, 56, 55, 54, 53, 52, 51,
50, 49, 48, 47,
};
static const unsigned int lcd0_data12_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
};
static const unsigned int lcd0_data16_pins[] = {
/* D[0:15] */
58, 57, 56, 55, 54, 53, 52, 51,
50, 49, 48, 47, 46, 45, 44, 43,
};
static const unsigned int lcd0_data16_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
};
static const unsigned int lcd0_data18_pins[] = {
/* D[0:17] */
58, 57, 56, 55, 54, 53, 52, 51,
50, 49, 48, 47, 46, 45, 44, 43,
42, 41,
};
static const unsigned int lcd0_data18_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
LCD0_D16_MARK, LCD0_D17_MARK,
};
static const unsigned int lcd0_data24_0_pins[] = {
/* D[0:23] */
58, 57, 56, 55, 54, 53, 52, 51,
@ -2182,65 +2097,13 @@ static const unsigned int lcd0_sys_mux[] = {
LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
};
/* - LCD1 ------------------------------------------------------------------- */
static const unsigned int lcd1_data8_pins[] = {
/* D[0:7] */
4, 3, 2, 1, 0, 91, 92, 23,
};
static const unsigned int lcd1_data8_mux[] = {
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
};
static const unsigned int lcd1_data9_pins[] = {
/* D[0:8] */
4, 3, 2, 1, 0, 91, 92, 23,
93,
};
static const unsigned int lcd1_data9_mux[] = {
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
LCD1_D8_MARK,
};
static const unsigned int lcd1_data12_pins[] = {
/* D[0:11] */
4, 3, 2, 1, 0, 91, 92, 23,
93, 94, 21, 201,
};
static const unsigned int lcd1_data12_mux[] = {
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
};
static const unsigned int lcd1_data16_pins[] = {
/* D[0:15] */
4, 3, 2, 1, 0, 91, 92, 23,
93, 94, 21, 201, 200, 199, 196, 195,
};
static const unsigned int lcd1_data16_mux[] = {
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
};
static const unsigned int lcd1_data18_pins[] = {
/* D[0:17] */
4, 3, 2, 1, 0, 91, 92, 23,
93, 94, 21, 201, 200, 199, 196, 195,
194, 193,
};
static const unsigned int lcd1_data18_mux[] = {
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
LCD1_D16_MARK, LCD1_D17_MARK,
};
static const unsigned int lcd1_data24_pins[] = {
static const unsigned int lcd1_data_pins[] = {
/* D[0:23] */
4, 3, 2, 1, 0, 91, 92, 23,
93, 94, 21, 201, 200, 199, 196, 195,
194, 193, 198, 197, 75, 74, 15, 14,
};
static const unsigned int lcd1_data24_mux[] = {
static const unsigned int lcd1_data_mux[] = {
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
@ -2277,25 +2140,11 @@ static const unsigned int lcd1_sys_mux[] = {
LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
};
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc0_data1_0_pins[] = {
/* D[0] */
68,
};
static const unsigned int mmc0_data1_0_mux[] = {
MMC0_D0_PORT68_MARK,
};
static const unsigned int mmc0_data4_0_pins[] = {
/* D[0:3] */
68, 69, 70, 71,
};
static const unsigned int mmc0_data4_0_mux[] = {
MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
};
static const unsigned int mmc0_data8_0_pins[] = {
static const unsigned int mmc0_data_0_pins[] = {
/* D[0:7] */
68, 69, 70, 71, 72, 73, 74, 75,
};
static const unsigned int mmc0_data8_0_mux[] = {
static const unsigned int mmc0_data_0_mux[] = {
MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
};
@ -2307,25 +2156,11 @@ static const unsigned int mmc0_ctrl_0_mux[] = {
MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
};
static const unsigned int mmc0_data1_1_pins[] = {
/* D[0] */
149,
};
static const unsigned int mmc0_data1_1_mux[] = {
MMC1_D0_PORT149_MARK,
};
static const unsigned int mmc0_data4_1_pins[] = {
/* D[0:3] */
149, 148, 147, 146,
};
static const unsigned int mmc0_data4_1_mux[] = {
MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
};
static const unsigned int mmc0_data8_1_pins[] = {
static const unsigned int mmc0_data_1_pins[] = {
/* D[0:7] */
149, 148, 147, 146, 145, 144, 143, 142,
};
static const unsigned int mmc0_data8_1_mux[] = {
static const unsigned int mmc0_data_1_mux[] = {
MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
};
@ -2591,18 +2426,11 @@ static const unsigned int scifb_ctrl_1_mux[] = {
SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
77,
};
static const unsigned int sdhi0_data1_mux[] = {
SDHI0_D0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
77, 78, 79, 80,
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
@ -2627,18 +2455,11 @@ static const unsigned int sdhi0_wp_mux[] = {
SDHI0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
68,
};
static const unsigned int sdhi1_data1_mux[] = {
SDHI1_D0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
68, 69, 70, 71,
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
@ -2663,18 +2484,11 @@ static const unsigned int sdhi1_wp_mux[] = {
SDHI1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
205,
};
static const unsigned int sdhi2_data1_mux[] = {
SDHI2_D0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:3] */
205, 206, 207, 208,
};
static const unsigned int sdhi2_data4_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
@ -2750,9 +2564,9 @@ static const unsigned int tpu0_to3_mux[] = {
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(bsc_data8),
SH_PFC_PIN_GROUP(bsc_data16),
SH_PFC_PIN_GROUP(bsc_data32),
BUS_DATA_PIN_GROUP(bsc_data, 8),
BUS_DATA_PIN_GROUP(bsc_data, 16),
BUS_DATA_PIN_GROUP(bsc_data, 32),
SH_PFC_PIN_GROUP(bsc_cs0),
SH_PFC_PIN_GROUP(bsc_cs2),
SH_PFC_PIN_GROUP(bsc_cs4),
@ -2760,9 +2574,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(bsc_cs5a_1),
SH_PFC_PIN_GROUP(bsc_cs5b),
SH_PFC_PIN_GROUP(bsc_cs6a),
SH_PFC_PIN_GROUP(bsc_rd_we8),
SH_PFC_PIN_GROUP(bsc_rd_we16),
SH_PFC_PIN_GROUP(bsc_rd_we32),
SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we8, bsc_rd_we, 0, 2),
SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we16, bsc_rd_we, 0, 3),
SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we32, bsc_rd_we, 0, 5),
SH_PFC_PIN_GROUP(bsc_bs),
SH_PFC_PIN_GROUP(bsc_rdwr),
SH_PFC_PIN_GROUP(ceu0_data_0_7),
@ -2847,11 +2661,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(intc_irq30_1),
SH_PFC_PIN_GROUP(intc_irq31_0),
SH_PFC_PIN_GROUP(intc_irq31_1),
SH_PFC_PIN_GROUP(lcd0_data8),
SH_PFC_PIN_GROUP(lcd0_data9),
SH_PFC_PIN_GROUP(lcd0_data12),
SH_PFC_PIN_GROUP(lcd0_data16),
SH_PFC_PIN_GROUP(lcd0_data18),
SH_PFC_PIN_GROUP_SUBSET(lcd0_data8, lcd0_data24_0, 0, 8),
SH_PFC_PIN_GROUP_SUBSET(lcd0_data9, lcd0_data24_0, 0, 9),
SH_PFC_PIN_GROUP_SUBSET(lcd0_data12, lcd0_data24_0, 0, 12),
SH_PFC_PIN_GROUP_SUBSET(lcd0_data16, lcd0_data24_0, 0, 16),
SH_PFC_PIN_GROUP_SUBSET(lcd0_data18, lcd0_data24_0, 0, 18),
SH_PFC_PIN_GROUP(lcd0_data24_0),
SH_PFC_PIN_GROUP(lcd0_data24_1),
SH_PFC_PIN_GROUP(lcd0_display),
@ -2859,23 +2673,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(lcd0_lclk_1),
SH_PFC_PIN_GROUP(lcd0_sync),
SH_PFC_PIN_GROUP(lcd0_sys),
SH_PFC_PIN_GROUP(lcd1_data8),
SH_PFC_PIN_GROUP(lcd1_data9),
SH_PFC_PIN_GROUP(lcd1_data12),
SH_PFC_PIN_GROUP(lcd1_data16),
SH_PFC_PIN_GROUP(lcd1_data18),
SH_PFC_PIN_GROUP(lcd1_data24),
BUS_DATA_PIN_GROUP(lcd1_data, 8),
BUS_DATA_PIN_GROUP(lcd1_data, 9),
BUS_DATA_PIN_GROUP(lcd1_data, 12),
BUS_DATA_PIN_GROUP(lcd1_data, 16),
BUS_DATA_PIN_GROUP(lcd1_data, 18),
BUS_DATA_PIN_GROUP(lcd1_data, 24),
SH_PFC_PIN_GROUP(lcd1_display),
SH_PFC_PIN_GROUP(lcd1_lclk),
SH_PFC_PIN_GROUP(lcd1_sync),
SH_PFC_PIN_GROUP(lcd1_sys),
SH_PFC_PIN_GROUP(mmc0_data1_0),
SH_PFC_PIN_GROUP(mmc0_data4_0),
SH_PFC_PIN_GROUP(mmc0_data8_0),
BUS_DATA_PIN_GROUP(mmc0_data, 1, _0),
BUS_DATA_PIN_GROUP(mmc0_data, 4, _0),
BUS_DATA_PIN_GROUP(mmc0_data, 8, _0),
SH_PFC_PIN_GROUP(mmc0_ctrl_0),
SH_PFC_PIN_GROUP(mmc0_data1_1),
SH_PFC_PIN_GROUP(mmc0_data4_1),
SH_PFC_PIN_GROUP(mmc0_data8_1),
BUS_DATA_PIN_GROUP(mmc0_data, 1, _1),
BUS_DATA_PIN_GROUP(mmc0_data, 4, _1),
BUS_DATA_PIN_GROUP(mmc0_data, 8, _1),
SH_PFC_PIN_GROUP(mmc0_ctrl_1),
SH_PFC_PIN_GROUP(scifa0_data),
SH_PFC_PIN_GROUP(scifa0_clk),
@ -2912,18 +2726,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scifb_data_1),
SH_PFC_PIN_GROUP(scifb_clk_1),
SH_PFC_PIN_GROUP(scifb_ctrl_1),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd_0),
SH_PFC_PIN_GROUP(sdhi2_wp_0),
@ -3681,7 +3495,7 @@ static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
{ 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
};
static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
static int r8a7740_pin_to_portcr(unsigned int pin)
{
unsigned int i;
@ -3690,10 +3504,10 @@ static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
&r8a7740_portcr_offsets[i];
if (pin <= group->end_pin)
return pfc->windows->virt + group->offset + pin;
return group->offset + pin;
}
return NULL;
return -1;
}
static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {

240
drivers/pinctrl/renesas/pfc-r8a77470.c
View File

@ -1595,30 +1595,14 @@ static const unsigned int i2c4_e_mux[] = {
SCL4_E_MARK, SDA4_E_MARK,
};
/* - MMC -------------------------------------------------------------------- */
static const unsigned int mmc_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(0, 15),
};
static const unsigned int mmc_data1_mux[] = {
MMC0_D0_SDHI1_D0_MARK,
};
static const unsigned int mmc_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
};
static const unsigned int mmc_data4_mux[] = {
MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
};
static const unsigned int mmc_data8_pins[] = {
static const unsigned int mmc_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
};
static const unsigned int mmc_data8_mux[] = {
static const unsigned int mmc_data_mux[] = {
MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
MMC0_D4_MARK, MMC0_D5_MARK,
@ -1639,19 +1623,12 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
static const unsigned int qspi0_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
RCAR_GP_PIN(1, 20),
};
static const unsigned int qspi0_data4_mux[] = {
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
@ -1662,19 +1639,12 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
static const unsigned int qspi1_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
RCAR_GP_PIN(4, 8),
};
static const unsigned int qspi1_data4_mux[] = {
static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
@ -1917,19 +1887,12 @@ static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(0, 7),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DAT0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
@ -1954,29 +1917,6 @@ static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(0, 15),
};
static const unsigned int sdhi1_data1_mux[] = {
MMC0_D0_SDHI1_D0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
};
static const unsigned int sdhi1_data4_mux[] = {
MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
};
static const unsigned int sdhi1_ctrl_mux[] = {
MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
};
static const unsigned int sdhi1_cd_pins[] = {
/* CD */
RCAR_GP_PIN(0, 19),
@ -1992,19 +1932,12 @@ static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(4, 16),
};
static const unsigned int sdhi2_data1_mux[] = {
SD2_DAT0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
};
static const unsigned int sdhi2_data4_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
@ -2047,43 +1980,39 @@ static const unsigned int usb1_mux[] = {
USB1_OVC_MARK,
};
/* - VIN0 ------------------------------------------------------------------- */
static const union vin_data vin0_data_pins = {
.data24 = {
/* B */
RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
/* G */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
/* R */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
},
static const unsigned int vin0_data_pins[] = {
/* B */
RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
/* G */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
/* R */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
};
static const union vin_data vin0_data_mux = {
.data24 = {
/* B */
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
/* G */
VI0_G0_MARK, VI0_G1_MARK,
VI0_G2_MARK, VI0_G3_MARK,
VI0_G4_MARK, VI0_G5_MARK,
VI0_G6_MARK, VI0_G7_MARK,
/* R */
VI0_R0_MARK, VI0_R1_MARK,
VI0_R2_MARK, VI0_R3_MARK,
VI0_R4_MARK, VI0_R5_MARK,
VI0_R6_MARK, VI0_R7_MARK,
},
static const unsigned int vin0_data_mux[] = {
/* B */
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
/* G */
VI0_G0_MARK, VI0_G1_MARK,
VI0_G2_MARK, VI0_G3_MARK,
VI0_G4_MARK, VI0_G5_MARK,
VI0_G6_MARK, VI0_G7_MARK,
/* R */
VI0_R0_MARK, VI0_R1_MARK,
VI0_R2_MARK, VI0_R3_MARK,
VI0_R4_MARK, VI0_R5_MARK,
VI0_R6_MARK, VI0_R7_MARK,
};
static const unsigned int vin0_data18_pins[] = {
/* B */
@ -2140,25 +2069,21 @@ static const unsigned int vin0_clk_mux[] = {
VI0_CLK_MARK,
};
/* - VIN1 ------------------------------------------------------------------- */
static const union vin_data vin1_data_pins = {
.data12 = {
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
},
static const unsigned int vin1_data_pins[] = {
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
};
static const union vin_data vin1_data_mux = {
.data12 = {
VI1_DATA0_MARK, VI1_DATA1_MARK,
VI1_DATA2_MARK, VI1_DATA3_MARK,
VI1_DATA4_MARK, VI1_DATA5_MARK,
VI1_DATA6_MARK, VI1_DATA7_MARK,
VI1_DATA8_MARK, VI1_DATA9_MARK,
VI1_DATA10_MARK, VI1_DATA11_MARK,
},
static const unsigned int vin1_data_mux[] = {
VI1_DATA0_MARK, VI1_DATA1_MARK,
VI1_DATA2_MARK, VI1_DATA3_MARK,
VI1_DATA4_MARK, VI1_DATA5_MARK,
VI1_DATA6_MARK, VI1_DATA7_MARK,
VI1_DATA8_MARK, VI1_DATA9_MARK,
VI1_DATA10_MARK, VI1_DATA11_MARK,
};
static const unsigned int vin1_sync_pins[] = {
RCAR_GP_PIN(3, 11), /* HSYNC */
@ -2243,16 +2168,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c4_c),
SH_PFC_PIN_GROUP(i2c4_d),
SH_PFC_PIN_GROUP(i2c4_e),
SH_PFC_PIN_GROUP(mmc_data1),
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
BUS_DATA_PIN_GROUP(qspi1_data, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_data_b),
SH_PFC_PIN_GROUP(scif0_data_c),
@ -2286,37 +2211,37 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif5_data_f),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP_SUBSET(sdhi1_data1, mmc_data, 0, 1),
SH_PFC_PIN_GROUP_SUBSET(sdhi1_data4, mmc_data, 0, 4),
SH_PFC_PIN_GROUP_ALIAS(sdhi1_ctrl, mmc_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd),
SH_PFC_PIN_GROUP(sdhi2_wp),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
VIN_DATA_PIN_GROUP(vin0_data, 24),
VIN_DATA_PIN_GROUP(vin0_data, 20),
BUS_DATA_PIN_GROUP(vin0_data, 24),
BUS_DATA_PIN_GROUP(vin0_data, 20),
SH_PFC_PIN_GROUP(vin0_data18),
VIN_DATA_PIN_GROUP(vin0_data, 16),
VIN_DATA_PIN_GROUP(vin0_data, 12),
VIN_DATA_PIN_GROUP(vin0_data, 10),
VIN_DATA_PIN_GROUP(vin0_data, 8),
BUS_DATA_PIN_GROUP(vin0_data, 16),
BUS_DATA_PIN_GROUP(vin0_data, 12),
BUS_DATA_PIN_GROUP(vin0_data, 10),
BUS_DATA_PIN_GROUP(vin0_data, 8),
SH_PFC_PIN_GROUP(vin0_sync),
SH_PFC_PIN_GROUP(vin0_field),
SH_PFC_PIN_GROUP(vin0_clkenb),
SH_PFC_PIN_GROUP(vin0_clk),
VIN_DATA_PIN_GROUP(vin1_data, 12),
VIN_DATA_PIN_GROUP(vin1_data, 10),
VIN_DATA_PIN_GROUP(vin1_data, 8),
BUS_DATA_PIN_GROUP(vin1_data, 12),
BUS_DATA_PIN_GROUP(vin1_data, 10),
BUS_DATA_PIN_GROUP(vin1_data, 8),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
@ -3420,8 +3345,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
u32 *pocctrl)
static int r8a77470_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
@ -3683,7 +3607,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a77470_pfc_ops = {
.pin_to_pocctrl = r8a77470_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
@ -3692,7 +3616,7 @@ static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
#ifdef CONFIG_PINCTRL_PFC_R8A77470
const struct sh_pfc_soc_info r8a77470_pinmux_info = {
.name = "r8a77470_pfc",
.ops = &r8a77470_pinmux_ops,
.ops = &r8a77470_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

69
drivers/pinctrl/renesas/pfc-r8a7778.c
View File

@ -1427,25 +1427,17 @@ I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C);
/* - MMC macro -------------------------------------------------------------- */
#define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
#define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
#define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
#define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
/* - MMC -------------------------------------------------------------------- */
MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD);
MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7));
MMC_PFC_DAT1(mmc_data1, MMC_D0);
MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1,
MMC_D2, MMC_D3);
MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
MMC_PFC_PINS(mmc_data, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31));
MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1,
MMC_PFC_DAT8(mmc_data, MMC_D0, MMC_D1,
MMC_D2, MMC_D3,
MMC_D4, MMC_D5,
MMC_D6, MMC_D7);
@ -1530,7 +1522,6 @@ SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B);
/* - SDHI macro ------------------------------------------------------------- */
#define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
#define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
#define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
#define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
#define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd)
@ -1541,11 +1532,9 @@ SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17));
SDHI_PFC_CDPN(sdhi0_cd, SD0_CD);
SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12));
SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD);
SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13));
SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0);
SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
SDHI_PFC_PINS(sdhi0_data, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16));
SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1,
SDHI_PFC_DAT4(sdhi0_data, SD0_DAT0, SD0_DAT1,
SD0_DAT2, SD0_DAT3);
SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18));
SDHI_PFC_WPPN(sdhi0_wp, SD0_WP);
@ -1559,17 +1548,13 @@ SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A);
SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16));
SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B);
SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7));
SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A);
SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18));
SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B);
SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
SDHI_PFC_PINS(sdhi1_data_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A,
SDHI_PFC_DAT4(sdhi1_data_a, SD1_DAT0_A, SD1_DAT1_A,
SD1_DAT2_A, SD1_DAT3_A);
SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
SDHI_PFC_PINS(sdhi1_data_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B,
SDHI_PFC_DAT4(sdhi1_data_b, SD1_DAT0_B, SD1_DAT1_B,
SD1_DAT2_B, SD1_DAT3_B);
SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31));
SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A);
@ -1585,17 +1570,13 @@ SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18));
SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A);
SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6));
SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B);
SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19));
SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A);
SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7));
SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B);
SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
SDHI_PFC_PINS(sdhi2_data_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22));
SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A,
SDHI_PFC_DAT4(sdhi2_data_a, SD2_DAT0_A, SD2_DAT1_A,
SD2_DAT2_A, SD2_DAT3_A);
SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
SDHI_PFC_PINS(sdhi2_data_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26));
SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B,
SDHI_PFC_DAT4(sdhi2_data_b, SD2_DAT0_B, SD2_DAT1_B,
SD2_DAT2_B, SD2_DAT3_B);
SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24));
SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A);
@ -1744,9 +1725,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c3_b),
SH_PFC_PIN_GROUP(i2c3_c),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(mmc_data1),
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_data_b),
@ -1781,27 +1762,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif5_data_b),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_cd_a),
SH_PFC_PIN_GROUP(sdhi1_cd_b),
SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
SH_PFC_PIN_GROUP(sdhi1_data1_a),
SH_PFC_PIN_GROUP(sdhi1_data1_b),
SH_PFC_PIN_GROUP(sdhi1_data4_a),
SH_PFC_PIN_GROUP(sdhi1_data4_b),
BUS_DATA_PIN_GROUP(sdhi1_data, 1, _a),
BUS_DATA_PIN_GROUP(sdhi1_data, 1, _b),
BUS_DATA_PIN_GROUP(sdhi1_data, 4, _a),
BUS_DATA_PIN_GROUP(sdhi1_data, 4, _b),
SH_PFC_PIN_GROUP(sdhi1_wp_a),
SH_PFC_PIN_GROUP(sdhi1_wp_b),
SH_PFC_PIN_GROUP(sdhi2_cd_a),
SH_PFC_PIN_GROUP(sdhi2_cd_b),
SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
SH_PFC_PIN_GROUP(sdhi2_data1_a),
SH_PFC_PIN_GROUP(sdhi2_data1_b),
SH_PFC_PIN_GROUP(sdhi2_data4_a),
SH_PFC_PIN_GROUP(sdhi2_data4_b),
BUS_DATA_PIN_GROUP(sdhi2_data, 1, _a),
BUS_DATA_PIN_GROUP(sdhi2_data, 1, _b),
BUS_DATA_PIN_GROUP(sdhi2_data, 4, _a),
BUS_DATA_PIN_GROUP(sdhi2_data, 4, _b),
SH_PFC_PIN_GROUP(sdhi2_wp_a),
SH_PFC_PIN_GROUP(sdhi2_wp_b),
SH_PFC_PIN_GROUP(ssi012_ctrl),

110
drivers/pinctrl/renesas/pfc-r8a7779.c
View File

@ -1928,28 +1928,13 @@ static const unsigned int lbsc_ex_cs5_mux[] = {
EX_CS5_MARK,
};
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc0_data1_pins[] = {
/* D[0] */
RCAR_GP_PIN(0, 19),
};
static const unsigned int mmc0_data1_mux[] = {
MMC0_D0_MARK,
};
static const unsigned int mmc0_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
RCAR_GP_PIN(0, 2),
};
static const unsigned int mmc0_data4_mux[] = {
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
};
static const unsigned int mmc0_data8_pins[] = {
static const unsigned int mmc0_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
};
static const unsigned int mmc0_data8_mux[] = {
static const unsigned int mmc0_data_mux[] = {
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
};
@ -1960,28 +1945,13 @@ static const unsigned int mmc0_ctrl_pins[] = {
static const unsigned int mmc0_ctrl_mux[] = {
MMC0_CMD_MARK, MMC0_CLK_MARK,
};
static const unsigned int mmc1_data1_pins[] = {
/* D[0] */
RCAR_GP_PIN(2, 8),
};
static const unsigned int mmc1_data1_mux[] = {
MMC1_D0_MARK,
};
static const unsigned int mmc1_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
RCAR_GP_PIN(2, 11),
};
static const unsigned int mmc1_data4_mux[] = {
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
};
static const unsigned int mmc1_data8_pins[] = {
static const unsigned int mmc1_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
};
static const unsigned int mmc1_data8_mux[] = {
static const unsigned int mmc1_data_mux[] = {
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
};
@ -2386,19 +2356,12 @@ static const unsigned int scif_clk_d_mux[] = {
SCIF_CLK_D_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 21),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DAT0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
RCAR_GP_PIN(3, 24),
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
@ -2423,19 +2386,12 @@ static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(0, 19),
};
static const unsigned int sdhi1_data1_mux[] = {
SD1_DAT0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
RCAR_GP_PIN(0, 2),
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
@ -2460,19 +2416,12 @@ static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 1),
};
static const unsigned int sdhi2_data1_mux[] = {
SD2_DAT0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4),
};
static const unsigned int sdhi2_data4_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
@ -2497,19 +2446,12 @@ static const unsigned int sdhi2_wp_mux[] = {
SD2_WP_MARK,
};
/* - SDHI3 ------------------------------------------------------------------ */
static const unsigned int sdhi3_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(1, 18),
};
static const unsigned int sdhi3_data1_mux[] = {
SD3_DAT0_MARK,
};
static const unsigned int sdhi3_data4_pins[] = {
static const unsigned int sdhi3_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
RCAR_GP_PIN(1, 21),
};
static const unsigned int sdhi3_data4_mux[] = {
static const unsigned int sdhi3_data_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
};
static const unsigned int sdhi3_ctrl_pins[] = {
@ -2749,13 +2691,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(lbsc_ex_cs3),
SH_PFC_PIN_GROUP(lbsc_ex_cs4),
SH_PFC_PIN_GROUP(lbsc_ex_cs5),
SH_PFC_PIN_GROUP(mmc0_data1),
SH_PFC_PIN_GROUP(mmc0_data4),
SH_PFC_PIN_GROUP(mmc0_data8),
BUS_DATA_PIN_GROUP(mmc0_data, 1),
BUS_DATA_PIN_GROUP(mmc0_data, 4),
BUS_DATA_PIN_GROUP(mmc0_data, 8),
SH_PFC_PIN_GROUP(mmc0_ctrl),
SH_PFC_PIN_GROUP(mmc1_data1),
SH_PFC_PIN_GROUP(mmc1_data4),
SH_PFC_PIN_GROUP(mmc1_data8),
BUS_DATA_PIN_GROUP(mmc1_data, 1),
BUS_DATA_PIN_GROUP(mmc1_data, 4),
BUS_DATA_PIN_GROUP(mmc1_data, 8),
SH_PFC_PIN_GROUP(mmc1_ctrl),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
@ -2812,23 +2754,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(scif_clk_c),
SH_PFC_PIN_GROUP(scif_clk_d),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd),
SH_PFC_PIN_GROUP(sdhi2_wp),
SH_PFC_PIN_GROUP(sdhi3_data1),
SH_PFC_PIN_GROUP(sdhi3_data4),
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),

493
drivers/pinctrl/renesas/pfc-r8a7790.c
View File

@ -2405,29 +2405,14 @@ static const unsigned int mlb_3pin_mux[] = {
#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
/* - MMCIF0 ----------------------------------------------------------------- */
static const unsigned int mmc0_data1_pins[] = {
/* D[0] */
RCAR_GP_PIN(3, 18),
};
static const unsigned int mmc0_data1_mux[] = {
MMC0_D0_MARK,
};
static const unsigned int mmc0_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
};
static const unsigned int mmc0_data4_mux[] = {
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
};
static const unsigned int mmc0_data8_pins[] = {
static const unsigned int mmc0_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
};
static const unsigned int mmc0_data8_mux[] = {
static const unsigned int mmc0_data_mux[] = {
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
};
@ -2439,29 +2424,14 @@ static const unsigned int mmc0_ctrl_mux[] = {
MMC0_CLK_MARK, MMC0_CMD_MARK,
};
/* - MMCIF1 ----------------------------------------------------------------- */
static const unsigned int mmc1_data1_pins[] = {
/* D[0] */
RCAR_GP_PIN(3, 26),
};
static const unsigned int mmc1_data1_mux[] = {
MMC1_D0_MARK,
};
static const unsigned int mmc1_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
};
static const unsigned int mmc1_data4_mux[] = {
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
};
static const unsigned int mmc1_data8_pins[] = {
static const unsigned int mmc1_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
};
static const unsigned int mmc1_data8_mux[] = {
static const unsigned int mmc1_data_mux[] = {
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
};
@ -2808,19 +2778,12 @@ static const unsigned int qspi_ctrl_pins[] = {
static const unsigned int qspi_ctrl_mux[] = {
SPCLK_MARK, SSL_MARK,
};
static const unsigned int qspi_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
};
static const unsigned int qspi_data2_mux[] = {
MOSI_IO0_MARK, MISO_IO1_MARK,
};
static const unsigned int qspi_data4_pins[] = {
static const unsigned int qspi_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(1, 8),
};
static const unsigned int qspi_data4_mux[] = {
static const unsigned int qspi_data_mux[] = {
MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
@ -3317,18 +3280,11 @@ static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 2),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DAT0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
@ -3353,18 +3309,11 @@ static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 10),
};
static const unsigned int sdhi1_data1_mux[] = {
SD1_DAT0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
@ -3389,18 +3338,11 @@ static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 18),
};
static const unsigned int sdhi2_data1_mux[] = {
SD2_DAT0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
};
static const unsigned int sdhi2_data4_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
@ -3425,18 +3367,11 @@ static const unsigned int sdhi2_wp_mux[] = {
SD2_WP_MARK,
};
/* - SDHI3 ------------------------------------------------------------------ */
static const unsigned int sdhi3_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 26),
};
static const unsigned int sdhi3_data1_mux[] = {
SD3_DAT0_MARK,
};
static const unsigned int sdhi3_data4_pins[] = {
static const unsigned int sdhi3_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
};
static const unsigned int sdhi3_data4_mux[] = {
static const unsigned int sdhi3_data_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
};
static const unsigned int sdhi3_ctrl_pins[] = {
@ -3674,18 +3609,11 @@ static const unsigned int tpu0_to3_mux[] = {
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC/VBUS */
RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
/* OVC/VBUS, PWEN */
RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 18),
};
static const unsigned int usb0_mux[] = {
USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
};
static const unsigned int usb0_ovc_vbus_pins[] = {
/* OVC/VBUS */
RCAR_GP_PIN(5, 19),
};
static const unsigned int usb0_ovc_vbus_mux[] = {
USB0_OVC_VBUS_MARK,
USB0_OVC_VBUS_MARK, USB0_PWEN_MARK,
};
/* - USB1 ------------------------------------------------------------------- */
static const unsigned int usb1_pins[] = {
@ -3695,13 +3623,6 @@ static const unsigned int usb1_pins[] = {
static const unsigned int usb1_mux[] = {
USB1_PWEN_MARK, USB1_OVC_MARK,
};
static const unsigned int usb1_pwen_pins[] = {
/* PWEN */
RCAR_GP_PIN(5, 20),
};
static const unsigned int usb1_pwen_mux[] = {
USB1_PWEN_MARK,
};
/* - USB2 ------------------------------------------------------------------- */
static const unsigned int usb2_pins[] = {
/* PWEN, OVC */
@ -3711,43 +3632,39 @@ static const unsigned int usb2_mux[] = {
USB2_PWEN_MARK, USB2_OVC_MARK,
};
/* - VIN0 ------------------------------------------------------------------- */
static const union vin_data vin0_data_pins = {
.data24 = {
/* B */
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
/* G */
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
/* R */
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
},
static const unsigned int vin0_data_pins[] = {
/* B */
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
/* G */
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
/* R */
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
};
static const union vin_data vin0_data_mux = {
.data24 = {
/* B */
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
/* G */
VI0_G0_MARK, VI0_G1_MARK,
VI0_G2_MARK, VI0_G3_MARK,
VI0_G4_MARK, VI0_G5_MARK,
VI0_G6_MARK, VI0_G7_MARK,
/* R */
VI0_R0_MARK, VI0_R1_MARK,
VI0_R2_MARK, VI0_R3_MARK,
VI0_R4_MARK, VI0_R5_MARK,
VI0_R6_MARK, VI0_R7_MARK,
},
static const unsigned int vin0_data_mux[] = {
/* B */
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
/* G */
VI0_G0_MARK, VI0_G1_MARK,
VI0_G2_MARK, VI0_G3_MARK,
VI0_G4_MARK, VI0_G5_MARK,
VI0_G6_MARK, VI0_G7_MARK,
/* R */
VI0_R0_MARK, VI0_R1_MARK,
VI0_R2_MARK, VI0_R3_MARK,
VI0_R4_MARK, VI0_R5_MARK,
VI0_R6_MARK, VI0_R7_MARK,
};
static const unsigned int vin0_data18_pins[] = {
/* B */
@ -3804,43 +3721,39 @@ static const unsigned int vin0_clk_mux[] = {
VI0_CLK_MARK,
};
/* - VIN1 ------------------------------------------------------------------- */
static const union vin_data vin1_data_pins = {
.data24 = {
/* B */
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
/* G */
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
/* R */
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
},
static const unsigned int vin1_data_pins[] = {
/* B */
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
/* G */
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
/* R */
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
};
static const union vin_data vin1_data_mux = {
.data24 = {
/* B */
VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
/* G */
VI1_G0_MARK, VI1_G1_MARK,
VI1_G2_MARK, VI1_G3_MARK,
VI1_G4_MARK, VI1_G5_MARK,
VI1_G6_MARK, VI1_G7_MARK,
/* R */
VI1_R0_MARK, VI1_R1_MARK,
VI1_R2_MARK, VI1_R3_MARK,
VI1_R4_MARK, VI1_R5_MARK,
VI1_R6_MARK, VI1_R7_MARK,
},
static const unsigned int vin1_data_mux[] = {
/* B */
VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
/* G */
VI1_G0_MARK, VI1_G1_MARK,
VI1_G2_MARK, VI1_G3_MARK,
VI1_G4_MARK, VI1_G5_MARK,
VI1_G6_MARK, VI1_G7_MARK,
/* R */
VI1_R0_MARK, VI1_R1_MARK,
VI1_R2_MARK, VI1_R3_MARK,
VI1_R4_MARK, VI1_R5_MARK,
VI1_R6_MARK, VI1_R7_MARK,
};
static const unsigned int vin1_data18_pins[] = {
/* B */
@ -3870,43 +3783,39 @@ static const unsigned int vin1_data18_mux[] = {
VI1_R4_MARK, VI1_R5_MARK,
VI1_R6_MARK, VI1_R7_MARK,
};
static const union vin_data vin1_data_b_pins = {
.data24 = {
/* B */
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
/* G */
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
/* R */
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
},
static const unsigned int vin1_data_b_pins[] = {
/* B */
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
/* G */
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
/* R */
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
};
static const union vin_data vin1_data_b_mux = {
.data24 = {
/* B */
VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
/* G */
VI1_G0_B_MARK, VI1_G1_B_MARK,
VI1_G2_B_MARK, VI1_G3_B_MARK,
VI1_G4_B_MARK, VI1_G5_B_MARK,
VI1_G6_B_MARK, VI1_G7_B_MARK,
/* R */
VI1_R0_B_MARK, VI1_R1_B_MARK,
VI1_R2_B_MARK, VI1_R3_B_MARK,
VI1_R4_B_MARK, VI1_R5_B_MARK,
VI1_R6_B_MARK, VI1_R7_B_MARK,
},
static const unsigned int vin1_data_b_mux[] = {
/* B */
VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
/* G */
VI1_G0_B_MARK, VI1_G1_B_MARK,
VI1_G2_B_MARK, VI1_G3_B_MARK,
VI1_G4_B_MARK, VI1_G5_B_MARK,
VI1_G6_B_MARK, VI1_G7_B_MARK,
/* R */
VI1_R0_B_MARK, VI1_R1_B_MARK,
VI1_R2_B_MARK, VI1_R3_B_MARK,
VI1_R4_B_MARK, VI1_R5_B_MARK,
VI1_R6_B_MARK, VI1_R7_B_MARK,
};
static const unsigned int vin1_data18_b_pins[] = {
/* B */
@ -3989,43 +3898,39 @@ static const unsigned int vin1_clk_b_mux[] = {
VI1_CLK_B_MARK,
};
/* - VIN2 ----------------------------------------------------------------- */
static const union vin_data vin2_data_pins = {
.data24 = {
/* B */
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
/* G */
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
/* R */
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
},
static const unsigned int vin2_data_pins[] = {
/* B */
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
/* G */
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
/* R */
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
};
static const union vin_data vin2_data_mux = {
.data24 = {
/* B */
VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
/* G */
VI2_G0_MARK, VI2_G1_MARK,
VI2_G2_MARK, VI2_G3_MARK,
VI2_G4_MARK, VI2_G5_MARK,
VI2_G6_MARK, VI2_G7_MARK,
/* R */
VI2_R0_MARK, VI2_R1_MARK,
VI2_R2_MARK, VI2_R3_MARK,
VI2_R4_MARK, VI2_R5_MARK,
VI2_R6_MARK, VI2_R7_MARK,
},
static const unsigned int vin2_data_mux[] = {
/* B */
VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
/* G */
VI2_G0_MARK, VI2_G1_MARK,
VI2_G2_MARK, VI2_G3_MARK,
VI2_G4_MARK, VI2_G5_MARK,
VI2_G6_MARK, VI2_G7_MARK,
/* R */
VI2_R0_MARK, VI2_R1_MARK,
VI2_R2_MARK, VI2_R3_MARK,
VI2_R4_MARK, VI2_R5_MARK,
VI2_R6_MARK, VI2_R7_MARK,
};
static const unsigned int vin2_data18_pins[] = {
/* B */
@ -4055,18 +3960,6 @@ static const unsigned int vin2_data18_mux[] = {
VI2_R4_MARK, VI2_R5_MARK,
VI2_R6_MARK, VI2_R7_MARK,
};
static const unsigned int vin2_g8_pins[] = {
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin2_g8_mux[] = {
VI2_G0_MARK, VI2_G1_MARK,
VI2_G2_MARK, VI2_G3_MARK,
VI2_G4_MARK, VI2_G5_MARK,
VI2_G6_MARK, VI2_G7_MARK,
};
static const unsigned int vin2_sync_pins[] = {
RCAR_GP_PIN(1, 16), /* HSYNC */
RCAR_GP_PIN(1, 21), /* VSYNC */
@ -4218,13 +4111,13 @@ static const struct {
SH_PFC_PIN_GROUP(intc_irq1),
SH_PFC_PIN_GROUP(intc_irq2),
SH_PFC_PIN_GROUP(intc_irq3),
SH_PFC_PIN_GROUP(mmc0_data1),
SH_PFC_PIN_GROUP(mmc0_data4),
SH_PFC_PIN_GROUP(mmc0_data8),
BUS_DATA_PIN_GROUP(mmc0_data, 1),
BUS_DATA_PIN_GROUP(mmc0_data, 4),
BUS_DATA_PIN_GROUP(mmc0_data, 8),
SH_PFC_PIN_GROUP(mmc0_ctrl),
SH_PFC_PIN_GROUP(mmc1_data1),
SH_PFC_PIN_GROUP(mmc1_data4),
SH_PFC_PIN_GROUP(mmc1_data8),
BUS_DATA_PIN_GROUP(mmc1_data, 1),
BUS_DATA_PIN_GROUP(mmc1_data, 4),
BUS_DATA_PIN_GROUP(mmc1_data, 8),
SH_PFC_PIN_GROUP(mmc1_ctrl),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
@ -4274,8 +4167,8 @@ static const struct {
SH_PFC_PIN_GROUP(pwm5),
SH_PFC_PIN_GROUP(pwm6),
SH_PFC_PIN_GROUP(qspi_ctrl),
SH_PFC_PIN_GROUP(qspi_data2),
SH_PFC_PIN_GROUP(qspi_data4),
BUS_DATA_PIN_GROUP(qspi_data, 2),
BUS_DATA_PIN_GROUP(qspi_data, 4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@ -4345,23 +4238,23 @@ static const struct {
SH_PFC_PIN_GROUP(scifb2_data_c),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd),
SH_PFC_PIN_GROUP(sdhi2_wp),
SH_PFC_PIN_GROUP(sdhi3_data1),
SH_PFC_PIN_GROUP(sdhi3_data4),
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),
@ -4396,38 +4289,38 @@ static const struct {
SH_PFC_PIN_GROUP(tpu0_to2),
SH_PFC_PIN_GROUP(tpu0_to3),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb0_ovc_vbus),
SH_PFC_PIN_GROUP_SUBSET(usb0_ovc_vbus, usb0, 0, 1),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb1_pwen),
SH_PFC_PIN_GROUP_SUBSET(usb1_pwen, usb1, 0, 1),
SH_PFC_PIN_GROUP(usb2),
VIN_DATA_PIN_GROUP(vin0_data, 24),
VIN_DATA_PIN_GROUP(vin0_data, 20),
BUS_DATA_PIN_GROUP(vin0_data, 24),
BUS_DATA_PIN_GROUP(vin0_data, 20),
SH_PFC_PIN_GROUP(vin0_data18),
VIN_DATA_PIN_GROUP(vin0_data, 16),
VIN_DATA_PIN_GROUP(vin0_data, 12),
VIN_DATA_PIN_GROUP(vin0_data, 10),
VIN_DATA_PIN_GROUP(vin0_data, 8),
VIN_DATA_PIN_GROUP(vin0_data, 4),
BUS_DATA_PIN_GROUP(vin0_data, 16),
BUS_DATA_PIN_GROUP(vin0_data, 12),
BUS_DATA_PIN_GROUP(vin0_data, 10),
BUS_DATA_PIN_GROUP(vin0_data, 8),
BUS_DATA_PIN_GROUP(vin0_data, 4),
SH_PFC_PIN_GROUP(vin0_sync),
SH_PFC_PIN_GROUP(vin0_field),
SH_PFC_PIN_GROUP(vin0_clkenb),
SH_PFC_PIN_GROUP(vin0_clk),
VIN_DATA_PIN_GROUP(vin1_data, 24),
VIN_DATA_PIN_GROUP(vin1_data, 20),
BUS_DATA_PIN_GROUP(vin1_data, 24),
BUS_DATA_PIN_GROUP(vin1_data, 20),
SH_PFC_PIN_GROUP(vin1_data18),
VIN_DATA_PIN_GROUP(vin1_data, 16),
VIN_DATA_PIN_GROUP(vin1_data, 12),
VIN_DATA_PIN_GROUP(vin1_data, 10),
VIN_DATA_PIN_GROUP(vin1_data, 8),
VIN_DATA_PIN_GROUP(vin1_data, 4),
VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
BUS_DATA_PIN_GROUP(vin1_data, 16),
BUS_DATA_PIN_GROUP(vin1_data, 12),
BUS_DATA_PIN_GROUP(vin1_data, 10),
BUS_DATA_PIN_GROUP(vin1_data, 8),
BUS_DATA_PIN_GROUP(vin1_data, 4),
BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
SH_PFC_PIN_GROUP(vin1_data18_b),
VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
VIN_DATA_PIN_GROUP(vin1_data, 4, _b),
BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
BUS_DATA_PIN_GROUP(vin1_data, 4, _b),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_sync_b),
SH_PFC_PIN_GROUP(vin1_field),
@ -4436,12 +4329,12 @@ static const struct {
SH_PFC_PIN_GROUP(vin1_clkenb_b),
SH_PFC_PIN_GROUP(vin1_clk),
SH_PFC_PIN_GROUP(vin1_clk_b),
VIN_DATA_PIN_GROUP(vin2_data, 24),
BUS_DATA_PIN_GROUP(vin2_data, 24),
SH_PFC_PIN_GROUP(vin2_data18),
VIN_DATA_PIN_GROUP(vin2_data, 16),
VIN_DATA_PIN_GROUP(vin2_data, 8),
VIN_DATA_PIN_GROUP(vin2_data, 4),
SH_PFC_PIN_GROUP(vin2_g8),
BUS_DATA_PIN_GROUP(vin2_data, 16),
BUS_DATA_PIN_GROUP(vin2_data, 8),
BUS_DATA_PIN_GROUP(vin2_data, 4),
SH_PFC_PIN_GROUP_SUBSET(vin2_g8, vin2_data, 8, 8),
SH_PFC_PIN_GROUP(vin2_sync),
SH_PFC_PIN_GROUP(vin2_field),
SH_PFC_PIN_GROUP(vin2_clkenb),
@ -5980,7 +5873,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
return -EINVAL;
@ -6282,7 +6175,7 @@ static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
return 0;
}
static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a7790_pfc_ops = {
.init = r8a7790_pinmux_soc_init,
.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
@ -6292,7 +6185,7 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
#ifdef CONFIG_PINCTRL_PFC_R8A7742
const struct sh_pfc_soc_info r8a7742_pinmux_info = {
.name = "r8a77420_pfc",
.ops = &r8a7790_pinmux_ops,
.ops = &r8a7790_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@ -6315,7 +6208,7 @@ const struct sh_pfc_soc_info r8a7742_pinmux_info = {
#ifdef CONFIG_PINCTRL_PFC_R8A7790
const struct sh_pfc_soc_info r8a7790_pinmux_info = {
.name = "r8a77900_pfc",
.ops = &r8a7790_pinmux_ops,
.ops = &r8a7790_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

287
drivers/pinctrl/renesas/pfc-r8a7791.c
View File

@ -2298,13 +2298,6 @@ static const unsigned int hscif1_data_d_pins[] = {
static const unsigned int hscif1_data_d_mux[] = {
HRX1_D_MARK, HTX1_D_MARK,
};
static const unsigned int hscif1_data_e_pins[] = {
/* RX, TX */
RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
};
static const unsigned int hscif1_data_e_mux[] = {
HRX1_C_MARK, HTX1_C_MARK,
};
static const unsigned int hscif1_clk_e_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 6),
@ -2599,40 +2592,25 @@ static const unsigned int mlb_3pin_mux[] = {
#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc_data1_pins[] = {
/* D[0] */
RCAR_GP_PIN(6, 18),
};
static const unsigned int mmc_data1_mux[] = {
MMC_D0_MARK,
};
static const unsigned int mmc_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
};
static const unsigned int mmc_data4_mux[] = {
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
};
static const unsigned int mmc_data8_pins[] = {
static const unsigned int mmc_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
};
static const unsigned int mmc_data8_mux[] = {
static const unsigned int mmc_data_mux[] = {
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
};
static const unsigned int mmc_data8_b_pins[] = {
static const unsigned int mmc_data_b_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
};
static const unsigned int mmc_data8_b_mux[] = {
static const unsigned int mmc_data_b_mux[] = {
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
};
@ -3220,19 +3198,12 @@ static const unsigned int qspi_ctrl_pins[] = {
static const unsigned int qspi_ctrl_mux[] = {
SPCLK_MARK, SSL_MARK,
};
static const unsigned int qspi_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
};
static const unsigned int qspi_data2_mux[] = {
MOSI_IO0_MARK, MISO_IO1_MARK,
};
static const unsigned int qspi_data4_pins[] = {
static const unsigned int qspi_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(1, 8),
};
static const unsigned int qspi_data4_mux[] = {
static const unsigned int qspi_data_mux[] = {
MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
};
@ -3243,19 +3214,12 @@ static const unsigned int qspi_ctrl_b_pins[] = {
static const unsigned int qspi_ctrl_b_mux[] = {
SPCLK_B_MARK, SSL_B_MARK,
};
static const unsigned int qspi_data2_b_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
};
static const unsigned int qspi_data2_b_mux[] = {
MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
};
static const unsigned int qspi_data4_b_pins[] = {
static const unsigned int qspi_data_b_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
RCAR_GP_PIN(6, 4),
};
static const unsigned int qspi_data4_b_mux[] = {
static const unsigned int qspi_data_b_mux[] = {
MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
@ -3816,19 +3780,12 @@ static const unsigned int scif_clk_b_mux[] = {
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 2),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DATA0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
@ -3853,19 +3810,12 @@ static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 10),
};
static const unsigned int sdhi1_data1_mux[] = {
SD1_DATA0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
@ -3890,19 +3840,12 @@ static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 18),
};
static const unsigned int sdhi2_data1_mux[] = {
SD2_DATA0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
};
static const unsigned int sdhi2_data4_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
@ -4225,43 +4168,39 @@ static const unsigned int usb1_mux[] = {
USB1_OVC_MARK,
};
/* - VIN0 ------------------------------------------------------------------- */
static const union vin_data vin0_data_pins = {
.data24 = {
/* B */
RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
/* G */
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
/* R */
RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
},
static const unsigned int vin0_data_pins[] = {
/* B */
RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
/* G */
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
/* R */
RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
};
static const union vin_data vin0_data_mux = {
.data24 = {
/* B */
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
/* G */
VI0_G0_MARK, VI0_G1_MARK,
VI0_G2_MARK, VI0_G3_MARK,
VI0_G4_MARK, VI0_G5_MARK,
VI0_G6_MARK, VI0_G7_MARK,
/* R */
VI0_R0_MARK, VI0_R1_MARK,
VI0_R2_MARK, VI0_R3_MARK,
VI0_R4_MARK, VI0_R5_MARK,
VI0_R6_MARK, VI0_R7_MARK,
},
static const unsigned int vin0_data_mux[] = {
/* B */
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
/* G */
VI0_G0_MARK, VI0_G1_MARK,
VI0_G2_MARK, VI0_G3_MARK,
VI0_G4_MARK, VI0_G5_MARK,
VI0_G6_MARK, VI0_G7_MARK,
/* R */
VI0_R0_MARK, VI0_R1_MARK,
VI0_R2_MARK, VI0_R3_MARK,
VI0_R4_MARK, VI0_R5_MARK,
VI0_R6_MARK, VI0_R7_MARK,
};
static const unsigned int vin0_data18_pins[] = {
/* B */
@ -4356,43 +4295,39 @@ static const unsigned int vin1_clk_pins[] = {
static const unsigned int vin1_clk_mux[] = {
VI1_CLK_MARK,
};
static const union vin_data vin1_data_b_pins = {
.data24 = {
/* B */
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
/* G */
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
/* R */
RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
},
static const unsigned int vin1_data_b_pins[] = {
/* B */
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
/* G */
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
/* R */
RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
};
static const union vin_data vin1_data_b_mux = {
.data24 = {
/* B */
VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
/* G */
VI1_G0_B_MARK, VI1_G1_B_MARK,
VI1_G2_B_MARK, VI1_G3_B_MARK,
VI1_G4_B_MARK, VI1_G5_B_MARK,
VI1_G6_B_MARK, VI1_G7_B_MARK,
/* R */
VI1_R0_B_MARK, VI1_R1_B_MARK,
VI1_R2_B_MARK, VI1_R3_B_MARK,
VI1_R4_B_MARK, VI1_R5_B_MARK,
VI1_R6_B_MARK, VI1_R7_B_MARK,
},
static const unsigned int vin1_data_b_mux[] = {
/* B */
VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
/* G */
VI1_G0_B_MARK, VI1_G1_B_MARK,
VI1_G2_B_MARK, VI1_G3_B_MARK,
VI1_G4_B_MARK, VI1_G5_B_MARK,
VI1_G6_B_MARK, VI1_G7_B_MARK,
/* R */
VI1_R0_B_MARK, VI1_R1_B_MARK,
VI1_R2_B_MARK, VI1_R3_B_MARK,
VI1_R4_B_MARK, VI1_R5_B_MARK,
VI1_R6_B_MARK, VI1_R7_B_MARK,
};
static const unsigned int vin1_data18_b_pins[] = {
/* B */
@ -4551,7 +4486,7 @@ static const struct {
SH_PFC_PIN_GROUP(hscif1_clk_c),
SH_PFC_PIN_GROUP(hscif1_ctrl_c),
SH_PFC_PIN_GROUP(hscif1_data_d),
SH_PFC_PIN_GROUP(hscif1_data_e),
SH_PFC_PIN_GROUP_ALIAS(hscif1_data_e, hscif1_data_c),
SH_PFC_PIN_GROUP(hscif1_clk_e),
SH_PFC_PIN_GROUP(hscif1_ctrl_e),
SH_PFC_PIN_GROUP(hscif2_data),
@ -4591,10 +4526,10 @@ static const struct {
SH_PFC_PIN_GROUP(intc_irq1),
SH_PFC_PIN_GROUP(intc_irq2),
SH_PFC_PIN_GROUP(intc_irq3),
SH_PFC_PIN_GROUP(mmc_data1),
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
SH_PFC_PIN_GROUP(mmc_data8_b),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
BUS_DATA_PIN_GROUP(mmc_data, 8, _b),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
@ -4678,11 +4613,11 @@ static const struct {
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm6),
SH_PFC_PIN_GROUP(qspi_ctrl),
SH_PFC_PIN_GROUP(qspi_data2),
SH_PFC_PIN_GROUP(qspi_data4),
BUS_DATA_PIN_GROUP(qspi_data, 2),
BUS_DATA_PIN_GROUP(qspi_data, 4),
SH_PFC_PIN_GROUP(qspi_ctrl_b),
SH_PFC_PIN_GROUP(qspi_data2_b),
SH_PFC_PIN_GROUP(qspi_data4_b),
BUS_DATA_PIN_GROUP(qspi_data, 2, _b),
BUS_DATA_PIN_GROUP(qspi_data, 4, _b),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_data_b),
SH_PFC_PIN_GROUP(scif0_data_c),
@ -4760,18 +4695,18 @@ static const struct {
SH_PFC_PIN_GROUP(scifb2_data_d),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd),
SH_PFC_PIN_GROUP(sdhi2_wp),
@ -4809,13 +4744,13 @@ static const struct {
SH_PFC_PIN_GROUP(tpu_to3),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
VIN_DATA_PIN_GROUP(vin0_data, 24),
VIN_DATA_PIN_GROUP(vin0_data, 20),
BUS_DATA_PIN_GROUP(vin0_data, 24),
BUS_DATA_PIN_GROUP(vin0_data, 20),
SH_PFC_PIN_GROUP(vin0_data18),
VIN_DATA_PIN_GROUP(vin0_data, 16),
VIN_DATA_PIN_GROUP(vin0_data, 12),
VIN_DATA_PIN_GROUP(vin0_data, 10),
VIN_DATA_PIN_GROUP(vin0_data, 8),
BUS_DATA_PIN_GROUP(vin0_data, 16),
BUS_DATA_PIN_GROUP(vin0_data, 12),
BUS_DATA_PIN_GROUP(vin0_data, 10),
BUS_DATA_PIN_GROUP(vin0_data, 8),
SH_PFC_PIN_GROUP(vin0_sync),
SH_PFC_PIN_GROUP(vin0_field),
SH_PFC_PIN_GROUP(vin0_clkenb),
@ -4825,13 +4760,13 @@ static const struct {
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
SH_PFC_PIN_GROUP(vin1_clk),
VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
SH_PFC_PIN_GROUP(vin1_data18_b),
VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
SH_PFC_PIN_GROUP(vin1_sync_b),
SH_PFC_PIN_GROUP(vin1_field_b),
SH_PFC_PIN_GROUP(vin1_clkenb_b),
@ -6667,7 +6602,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
return -EINVAL;
@ -6989,7 +6924,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a7791_pfc_ops = {
.pin_to_pocctrl = r8a7791_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
@ -6998,7 +6933,7 @@ static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
#ifdef CONFIG_PINCTRL_PFC_R8A7743
const struct sh_pfc_soc_info r8a7743_pinmux_info = {
.name = "r8a77430_pfc",
.ops = &r8a7791_pinmux_ops,
.ops = &r8a7791_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@ -7021,7 +6956,7 @@ const struct sh_pfc_soc_info r8a7743_pinmux_info = {
#ifdef CONFIG_PINCTRL_PFC_R8A7744
const struct sh_pfc_soc_info r8a7744_pinmux_info = {
.name = "r8a77440_pfc",
.ops = &r8a7791_pinmux_ops,
.ops = &r8a7791_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@ -7044,7 +6979,7 @@ const struct sh_pfc_soc_info r8a7744_pinmux_info = {
#ifdef CONFIG_PINCTRL_PFC_R8A7791
const struct sh_pfc_soc_info r8a7791_pinmux_info = {
.name = "r8a77910_pfc",
.ops = &r8a7791_pinmux_ops,
.ops = &r8a7791_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@ -7069,7 +7004,7 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = {
#ifdef CONFIG_PINCTRL_PFC_R8A7793
const struct sh_pfc_soc_info r8a7793_pinmux_info = {
.name = "r8a77930_pfc",
.ops = &r8a7791_pinmux_ops,
.ops = &r8a7791_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

440
drivers/pinctrl/renesas/pfc-r8a7792.c
View File

@ -1116,19 +1116,12 @@ static const unsigned int qspi_ctrl_pins[] = {
static const unsigned int qspi_ctrl_mux[] = {
SPCLK_MARK, SSL_MARK,
};
static const unsigned int qspi_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
static const unsigned int qspi_data2_mux[] = {
MOSI_IO0_MARK, MISO_IO1_MARK,
};
static const unsigned int qspi_data4_pins[] = {
static const unsigned int qspi_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
RCAR_GP_PIN(3, 24),
};
static const unsigned int qspi_data4_mux[] = {
static const unsigned int qspi_data_mux[] = {
MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
@ -1206,19 +1199,12 @@ static const unsigned int scif3_clk_mux[] = {
SCK3_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* DAT0 */
RCAR_GP_PIN(11, 7),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DAT0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* DAT[0-3] */
RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
@ -1243,43 +1229,39 @@ static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - VIN0 ------------------------------------------------------------------- */
static const union vin_data vin0_data_pins = {
.data24 = {
/* B */
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
/* G */
RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
/* R */
RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
},
static const unsigned int vin0_data_pins[] = {
/* B */
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
/* G */
RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
/* R */
RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
};
static const union vin_data vin0_data_mux = {
.data24 = {
/* B */
VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
/* G */
VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
/* R */
VI0_D16_R0_MARK, VI0_D17_R1_MARK,
VI0_D18_R2_MARK, VI0_D19_R3_MARK,
VI0_D20_R4_MARK, VI0_D21_R5_MARK,
VI0_D22_R6_MARK, VI0_D23_R7_MARK,
},
static const unsigned int vin0_data_mux[] = {
/* B */
VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
/* G */
VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
/* R */
VI0_D16_R0_MARK, VI0_D17_R1_MARK,
VI0_D18_R2_MARK, VI0_D19_R3_MARK,
VI0_D20_R4_MARK, VI0_D21_R5_MARK,
VI0_D22_R6_MARK, VI0_D23_R7_MARK,
};
static const unsigned int vin0_data18_pins[] = {
/* B */
@ -1335,43 +1317,39 @@ static const unsigned int vin0_clk_mux[] = {
VI0_CLK_MARK,
};
/* - VIN1 ------------------------------------------------------------------- */
static const union vin_data vin1_data_pins = {
.data24 = {
/* B */
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
/* G */
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
/* R */
RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
},
static const unsigned int vin1_data_pins[] = {
/* B */
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
/* G */
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
/* R */
RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
};
static const union vin_data vin1_data_mux = {
.data24 = {
/* B */
VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
/* G */
VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
/* R */
VI1_D16_R0_MARK, VI1_D17_R1_MARK,
VI1_D18_R2_MARK, VI1_D19_R3_MARK,
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
},
static const unsigned int vin1_data_mux[] = {
/* B */
VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
/* G */
VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
/* R */
VI1_D16_R0_MARK, VI1_D17_R1_MARK,
VI1_D18_R2_MARK, VI1_D19_R3_MARK,
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
};
static const unsigned int vin1_data18_pins[] = {
/* B */
@ -1401,43 +1379,39 @@ static const unsigned int vin1_data18_mux[] = {
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
};
static const union vin_data vin1_data_b_pins = {
.data24 = {
/* B */
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
/* G */
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
/* R */
RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
},
static const unsigned int vin1_data_b_pins[] = {
/* B */
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
/* G */
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
/* R */
RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
};
static const union vin_data vin1_data_b_mux = {
.data24 = {
/* B */
VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
/* G */
VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
/* R */
VI1_D16_R0_MARK, VI1_D17_R1_MARK,
VI1_D18_R2_MARK, VI1_D19_R3_MARK,
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
},
static const unsigned int vin1_data_b_mux[] = {
/* B */
VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
/* G */
VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
/* R */
VI1_D16_R0_MARK, VI1_D17_R1_MARK,
VI1_D18_R2_MARK, VI1_D19_R3_MARK,
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
};
static const unsigned int vin1_data18_b_pins[] = {
/* B */
@ -1493,29 +1467,25 @@ static const unsigned int vin1_clk_mux[] = {
VI1_CLK_MARK,
};
/* - VIN2 ------------------------------------------------------------------- */
static const union vin_data16 vin2_data_pins = {
.data16 = {
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
},
static const unsigned int vin2_data_pins[] = {
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
};
static const union vin_data16 vin2_data_mux = {
.data16 = {
VI2_D0_C0_MARK, VI2_D1_C1_MARK,
VI2_D2_C2_MARK, VI2_D3_C3_MARK,
VI2_D4_C4_MARK, VI2_D5_C5_MARK,
VI2_D6_C6_MARK, VI2_D7_C7_MARK,
VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
},
static const unsigned int vin2_data_mux[] = {
VI2_D0_C0_MARK, VI2_D1_C1_MARK,
VI2_D2_C2_MARK, VI2_D3_C3_MARK,
VI2_D4_C4_MARK, VI2_D5_C5_MARK,
VI2_D6_C6_MARK, VI2_D7_C7_MARK,
VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
};
static const unsigned int vin2_sync_pins[] = {
/* HSYNC#, VSYNC# */
@ -1543,29 +1513,25 @@ static const unsigned int vin2_clk_mux[] = {
VI2_CLK_MARK,
};
/* - VIN3 ------------------------------------------------------------------- */
static const union vin_data16 vin3_data_pins = {
.data16 = {
RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
},
static const unsigned int vin3_data_pins[] = {
RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
};
static const union vin_data16 vin3_data_mux = {
.data16 = {
VI3_D0_C0_MARK, VI3_D1_C1_MARK,
VI3_D2_C2_MARK, VI3_D3_C3_MARK,
VI3_D4_C4_MARK, VI3_D5_C5_MARK,
VI3_D6_C6_MARK, VI3_D7_C7_MARK,
VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
},
static const unsigned int vin3_data_mux[] = {
VI3_D0_C0_MARK, VI3_D1_C1_MARK,
VI3_D2_C2_MARK, VI3_D3_C3_MARK,
VI3_D4_C4_MARK, VI3_D5_C5_MARK,
VI3_D6_C6_MARK, VI3_D7_C7_MARK,
VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
};
static const unsigned int vin3_sync_pins[] = {
/* HSYNC#, VSYNC# */
@ -1593,25 +1559,21 @@ static const unsigned int vin3_clk_mux[] = {
VI3_CLK_MARK,
};
/* - VIN4 ------------------------------------------------------------------- */
static const union vin_data12 vin4_data_pins = {
.data12 = {
RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
},
static const unsigned int vin4_data_pins[] = {
RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
};
static const union vin_data12 vin4_data_mux = {
.data12 = {
VI4_D0_C0_MARK, VI4_D1_C1_MARK,
VI4_D2_C2_MARK, VI4_D3_C3_MARK,
VI4_D4_C4_MARK, VI4_D5_C5_MARK,
VI4_D6_C6_MARK, VI4_D7_C7_MARK,
VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
},
static const unsigned int vin4_data_mux[] = {
VI4_D0_C0_MARK, VI4_D1_C1_MARK,
VI4_D2_C2_MARK, VI4_D3_C3_MARK,
VI4_D4_C4_MARK, VI4_D5_C5_MARK,
VI4_D6_C6_MARK, VI4_D7_C7_MARK,
VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
@ -1639,25 +1601,21 @@ static const unsigned int vin4_clk_mux[] = {
VI4_CLK_MARK,
};
/* - VIN5 ------------------------------------------------------------------- */
static const union vin_data12 vin5_data_pins = {
.data12 = {
RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
},
static const unsigned int vin5_data_pins[] = {
RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
};
static const union vin_data12 vin5_data_mux = {
.data12 = {
VI5_D0_C0_MARK, VI5_D1_C1_MARK,
VI5_D2_C2_MARK, VI5_D3_C3_MARK,
VI5_D4_C4_MARK, VI5_D5_C5_MARK,
VI5_D6_C6_MARK, VI5_D7_C7_MARK,
VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
},
static const unsigned int vin5_data_mux[] = {
VI5_D0_C0_MARK, VI5_D1_C1_MARK,
VI5_D2_C2_MARK, VI5_D3_C3_MARK,
VI5_D4_C4_MARK, VI5_D5_C5_MARK,
VI5_D6_C6_MARK, VI5_D7_C7_MARK,
VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
};
static const unsigned int vin5_sync_pins[] = {
/* HSYNC#, VSYNC# */
@ -1728,8 +1686,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(msiof1_rx),
SH_PFC_PIN_GROUP(msiof1_tx),
SH_PFC_PIN_GROUP(qspi_ctrl),
SH_PFC_PIN_GROUP(qspi_data2),
SH_PFC_PIN_GROUP(qspi_data4),
BUS_DATA_PIN_GROUP(qspi_data, 2),
BUS_DATA_PIN_GROUP(qspi_data, 4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@ -1740,63 +1698,63 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif2_clk),
SH_PFC_PIN_GROUP(scif3_data),
SH_PFC_PIN_GROUP(scif3_clk),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
VIN_DATA_PIN_GROUP(vin0_data, 24),
VIN_DATA_PIN_GROUP(vin0_data, 20),
BUS_DATA_PIN_GROUP(vin0_data, 24),
BUS_DATA_PIN_GROUP(vin0_data, 20),
SH_PFC_PIN_GROUP(vin0_data18),
VIN_DATA_PIN_GROUP(vin0_data, 16),
VIN_DATA_PIN_GROUP(vin0_data, 12),
VIN_DATA_PIN_GROUP(vin0_data, 10),
VIN_DATA_PIN_GROUP(vin0_data, 8),
BUS_DATA_PIN_GROUP(vin0_data, 16),
BUS_DATA_PIN_GROUP(vin0_data, 12),
BUS_DATA_PIN_GROUP(vin0_data, 10),
BUS_DATA_PIN_GROUP(vin0_data, 8),
SH_PFC_PIN_GROUP(vin0_sync),
SH_PFC_PIN_GROUP(vin0_field),
SH_PFC_PIN_GROUP(vin0_clkenb),
SH_PFC_PIN_GROUP(vin0_clk),
VIN_DATA_PIN_GROUP(vin1_data, 24),
VIN_DATA_PIN_GROUP(vin1_data, 20),
BUS_DATA_PIN_GROUP(vin1_data, 24),
BUS_DATA_PIN_GROUP(vin1_data, 20),
SH_PFC_PIN_GROUP(vin1_data18),
VIN_DATA_PIN_GROUP(vin1_data, 16),
VIN_DATA_PIN_GROUP(vin1_data, 12),
VIN_DATA_PIN_GROUP(vin1_data, 10),
VIN_DATA_PIN_GROUP(vin1_data, 8),
VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
BUS_DATA_PIN_GROUP(vin1_data, 16),
BUS_DATA_PIN_GROUP(vin1_data, 12),
BUS_DATA_PIN_GROUP(vin1_data, 10),
BUS_DATA_PIN_GROUP(vin1_data, 8),
BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
SH_PFC_PIN_GROUP(vin1_data18_b),
VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
SH_PFC_PIN_GROUP(vin1_clk),
VIN_DATA_PIN_GROUP(vin2_data, 16),
VIN_DATA_PIN_GROUP(vin2_data, 12),
VIN_DATA_PIN_GROUP(vin2_data, 10),
VIN_DATA_PIN_GROUP(vin2_data, 8),
BUS_DATA_PIN_GROUP(vin2_data, 16),
BUS_DATA_PIN_GROUP(vin2_data, 12),
BUS_DATA_PIN_GROUP(vin2_data, 10),
BUS_DATA_PIN_GROUP(vin2_data, 8),
SH_PFC_PIN_GROUP(vin2_sync),
SH_PFC_PIN_GROUP(vin2_field),
SH_PFC_PIN_GROUP(vin2_clkenb),
SH_PFC_PIN_GROUP(vin2_clk),
VIN_DATA_PIN_GROUP(vin3_data, 16),
VIN_DATA_PIN_GROUP(vin3_data, 12),
VIN_DATA_PIN_GROUP(vin3_data, 10),
VIN_DATA_PIN_GROUP(vin3_data, 8),
BUS_DATA_PIN_GROUP(vin3_data, 16),
BUS_DATA_PIN_GROUP(vin3_data, 12),
BUS_DATA_PIN_GROUP(vin3_data, 10),
BUS_DATA_PIN_GROUP(vin3_data, 8),
SH_PFC_PIN_GROUP(vin3_sync),
SH_PFC_PIN_GROUP(vin3_field),
SH_PFC_PIN_GROUP(vin3_clkenb),
SH_PFC_PIN_GROUP(vin3_clk),
VIN_DATA_PIN_GROUP(vin4_data, 12),
VIN_DATA_PIN_GROUP(vin4_data, 10),
VIN_DATA_PIN_GROUP(vin4_data, 8),
BUS_DATA_PIN_GROUP(vin4_data, 12),
BUS_DATA_PIN_GROUP(vin4_data, 10),
BUS_DATA_PIN_GROUP(vin4_data, 8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
VIN_DATA_PIN_GROUP(vin5_data, 12),
VIN_DATA_PIN_GROUP(vin5_data, 10),
VIN_DATA_PIN_GROUP(vin5_data, 8),
BUS_DATA_PIN_GROUP(vin5_data, 12),
BUS_DATA_PIN_GROUP(vin5_data, 10),
BUS_DATA_PIN_GROUP(vin5_data, 8),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
@ -3281,14 +3239,14 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a7792_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a7792_pfc_ops = {
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a7792_pinmux_info = {
.name = "r8a77920_pfc",
.ops = &r8a7792_pinmux_ops,
.ops = &r8a7792_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

214
drivers/pinctrl/renesas/pfc-r8a7794.c
View File

@ -2388,29 +2388,14 @@ static const unsigned int intc_irq9_mux[] = {
IRQ9_MARK,
};
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc_data1_pins[] = {
/* D[0] */
RCAR_GP_PIN(6, 18),
};
static const unsigned int mmc_data1_mux[] = {
MMC_D0_MARK,
};
static const unsigned int mmc_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
};
static const unsigned int mmc_data4_mux[] = {
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
};
static const unsigned int mmc_data8_pins[] = {
static const unsigned int mmc_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
};
static const unsigned int mmc_data8_mux[] = {
static const unsigned int mmc_data_mux[] = {
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
};
@ -2745,19 +2730,12 @@ static const unsigned int qspi_ctrl_pins[] = {
static const unsigned int qspi_ctrl_mux[] = {
SPCLK_MARK, SSL_MARK,
};
static const unsigned int qspi_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
};
static const unsigned int qspi_data2_mux[] = {
MOSI_IO0_MARK, MISO_IO1_MARK,
};
static const unsigned int qspi_data4_pins[] = {
static const unsigned int qspi_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(1, 8),
};
static const unsigned int qspi_data4_mux[] = {
static const unsigned int qspi_data_mux[] = {
MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
@ -3232,19 +3210,12 @@ static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 2),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DATA0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
@ -3269,19 +3240,12 @@ static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 10),
};
static const unsigned int sdhi1_data1_mux[] = {
SD1_DATA0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
@ -3306,19 +3270,12 @@ static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 18),
};
static const unsigned int sdhi2_data1_mux[] = {
SD2_DATA0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
};
static const unsigned int sdhi2_data4_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
@ -3673,43 +3630,39 @@ static const unsigned int usb1_mux[] = {
USB1_OVC_MARK,
};
/* - VIN0 ------------------------------------------------------------------- */
static const union vin_data vin0_data_pins = {
.data24 = {
/* B */
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
/* G */
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
/* R */
RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
},
static const unsigned int vin0_data_pins[] = {
/* B */
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
/* G */
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
/* R */
RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
};
static const union vin_data vin0_data_mux = {
.data24 = {
/* B */
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
/* G */
VI0_G0_MARK, VI0_G1_MARK,
VI0_G2_MARK, VI0_G3_MARK,
VI0_G4_MARK, VI0_G5_MARK,
VI0_G6_MARK, VI0_G7_MARK,
/* R */
VI0_R0_MARK, VI0_R1_MARK,
VI0_R2_MARK, VI0_R3_MARK,
VI0_R4_MARK, VI0_R5_MARK,
VI0_R6_MARK, VI0_R7_MARK,
},
static const unsigned int vin0_data_mux[] = {
/* B */
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
/* G */
VI0_G0_MARK, VI0_G1_MARK,
VI0_G2_MARK, VI0_G3_MARK,
VI0_G4_MARK, VI0_G5_MARK,
VI0_G6_MARK, VI0_G7_MARK,
/* R */
VI0_R0_MARK, VI0_R1_MARK,
VI0_R2_MARK, VI0_R3_MARK,
VI0_R4_MARK, VI0_R5_MARK,
VI0_R6_MARK, VI0_R7_MARK,
};
static const unsigned int vin0_data18_pins[] = {
/* B */
@ -3766,25 +3719,21 @@ static const unsigned int vin0_clk_mux[] = {
VI0_CLK_MARK,
};
/* - VIN1 ------------------------------------------------------------------- */
static const union vin_data12 vin1_data_pins = {
.data12 = {
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
},
static const unsigned int vin1_data_pins[] = {
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
};
static const union vin_data12 vin1_data_mux = {
.data12 = {
VI1_DATA0_MARK, VI1_DATA1_MARK,
VI1_DATA2_MARK, VI1_DATA3_MARK,
VI1_DATA4_MARK, VI1_DATA5_MARK,
VI1_DATA6_MARK, VI1_DATA7_MARK,
VI1_DATA8_MARK, VI1_DATA9_MARK,
VI1_DATA10_MARK, VI1_DATA11_MARK,
},
static const unsigned int vin1_data_mux[] = {
VI1_DATA0_MARK, VI1_DATA1_MARK,
VI1_DATA2_MARK, VI1_DATA3_MARK,
VI1_DATA4_MARK, VI1_DATA5_MARK,
VI1_DATA6_MARK, VI1_DATA7_MARK,
VI1_DATA8_MARK, VI1_DATA9_MARK,
VI1_DATA10_MARK, VI1_DATA11_MARK,
};
static const unsigned int vin1_sync_pins[] = {
RCAR_GP_PIN(5, 22), /* HSYNC */
@ -3923,9 +3872,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(intc_irq7),
SH_PFC_PIN_GROUP(intc_irq8),
SH_PFC_PIN_GROUP(intc_irq9),
SH_PFC_PIN_GROUP(mmc_data1),
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
@ -3975,8 +3924,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(pwm6),
SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi_ctrl),
SH_PFC_PIN_GROUP(qspi_data2),
SH_PFC_PIN_GROUP(qspi_data4),
BUS_DATA_PIN_GROUP(qspi_data, 2),
BUS_DATA_PIN_GROUP(qspi_data, 4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_data_b),
SH_PFC_PIN_GROUP(scif0_data_c),
@ -4042,18 +3991,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scifb2_ctrl),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd),
SH_PFC_PIN_GROUP(sdhi2_wp),
@ -4105,20 +4054,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(tpu_to3_c),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
VIN_DATA_PIN_GROUP(vin0_data, 24),
VIN_DATA_PIN_GROUP(vin0_data, 20),
BUS_DATA_PIN_GROUP(vin0_data, 24),
BUS_DATA_PIN_GROUP(vin0_data, 20),
SH_PFC_PIN_GROUP(vin0_data18),
VIN_DATA_PIN_GROUP(vin0_data, 16),
VIN_DATA_PIN_GROUP(vin0_data, 12),
VIN_DATA_PIN_GROUP(vin0_data, 10),
VIN_DATA_PIN_GROUP(vin0_data, 8),
BUS_DATA_PIN_GROUP(vin0_data, 16),
BUS_DATA_PIN_GROUP(vin0_data, 12),
BUS_DATA_PIN_GROUP(vin0_data, 10),
BUS_DATA_PIN_GROUP(vin0_data, 8),
SH_PFC_PIN_GROUP(vin0_sync),
SH_PFC_PIN_GROUP(vin0_field),
SH_PFC_PIN_GROUP(vin0_clkenb),
SH_PFC_PIN_GROUP(vin0_clk),
VIN_DATA_PIN_GROUP(vin1_data, 12),
VIN_DATA_PIN_GROUP(vin1_data, 10),
VIN_DATA_PIN_GROUP(vin1_data, 8),
BUS_DATA_PIN_GROUP(vin1_data, 12),
BUS_DATA_PIN_GROUP(vin1_data, 10),
BUS_DATA_PIN_GROUP(vin1_data, 8),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
@ -5621,8 +5570,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
return -EINVAL;
*pocctrl = 0xe606006c;
switch (pin & 0x1f) {
@ -5932,7 +5884,7 @@ static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
return 0;
}
static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a7794_pfc_ops = {
.init = r8a7794_pinmux_soc_init,
.pin_to_pocctrl = r8a7794_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
@ -5942,7 +5894,7 @@ static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
#ifdef CONFIG_PINCTRL_PFC_R8A7745
const struct sh_pfc_soc_info r8a7745_pinmux_info = {
.name = "r8a77450_pfc",
.ops = &r8a7794_pinmux_ops,
.ops = &r8a7794_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@ -5965,7 +5917,7 @@ const struct sh_pfc_soc_info r8a7745_pinmux_info = {
#ifdef CONFIG_PINCTRL_PFC_R8A7794
const struct sh_pfc_soc_info r8a7794_pinmux_info = {
.name = "r8a77940_pfc",
.ops = &r8a7794_pinmux_ops,
.ops = &r8a7794_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

119
drivers/pinctrl/renesas/pfc-r8a77950.c
View File

@ -3140,18 +3140,11 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
static const unsigned int qspi0_data_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
};
static const unsigned int qspi0_data4_mux[] = {
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
@ -3163,18 +3156,11 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
static const unsigned int qspi1_data_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
};
static const unsigned int qspi1_data4_mux[] = {
static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
@ -3395,19 +3381,12 @@ static const unsigned int scif_clk_b_mux[] = {
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 2),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DAT0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK,
SD0_DAT2_MARK, SD0_DAT3_MARK,
};
@ -3433,19 +3412,12 @@ static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 8),
};
static const unsigned int sdhi1_data1_mux[] = {
SD1_DAT0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SD1_DAT0_MARK, SD1_DAT1_MARK,
SD1_DAT2_MARK, SD1_DAT3_MARK,
};
@ -3471,30 +3443,14 @@ static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(4, 2),
};
static const unsigned int sdhi2_data1_mux[] = {
SD2_DAT0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
};
static const unsigned int sdhi2_data4_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK,
SD2_DAT2_MARK, SD2_DAT3_MARK,
};
static const unsigned int sdhi2_data8_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi2_data8_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK,
SD2_DAT2_MARK, SD2_DAT3_MARK,
SD2_DAT4_MARK, SD2_DAT5_MARK,
@ -3543,30 +3499,14 @@ static const unsigned int sdhi2_ds_mux[] = {
SD2_DS_MARK,
};
/* - SDHI3 ------------------------------------------------------------------ */
static const unsigned int sdhi3_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(4, 9),
};
static const unsigned int sdhi3_data1_mux[] = {
SD3_DAT0_MARK,
};
static const unsigned int sdhi3_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
};
static const unsigned int sdhi3_data4_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
};
static const unsigned int sdhi3_data8_pins[] = {
static const unsigned int sdhi3_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
};
static const unsigned int sdhi3_data8_mux[] = {
static const unsigned int sdhi3_data_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
SD3_DAT4_MARK, SD3_DAT5_MARK,
@ -4103,11 +4043,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
BUS_DATA_PIN_GROUP(qspi1_data, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(sata0_devslp_a),
SH_PFC_PIN_GROUP(sata0_devslp_b),
SH_PFC_PIN_GROUP(scif0_data),
@ -4137,28 +4077,28 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif5_clk),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
SH_PFC_PIN_GROUP(sdhi2_data8),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
BUS_DATA_PIN_GROUP(sdhi2_data, 8),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd_a),
SH_PFC_PIN_GROUP(sdhi2_wp_a),
SH_PFC_PIN_GROUP(sdhi2_cd_b),
SH_PFC_PIN_GROUP(sdhi2_wp_b),
SH_PFC_PIN_GROUP(sdhi2_ds),
SH_PFC_PIN_GROUP(sdhi3_data1),
SH_PFC_PIN_GROUP(sdhi3_data4),
SH_PFC_PIN_GROUP(sdhi3_data8),
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),
@ -5574,8 +5514,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ },
};
static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
u32 *pocctrl)
static int r8a77950_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
@ -5832,7 +5771,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a77950_pfc_ops = {
.pin_to_pocctrl = r8a77950_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
@ -5840,7 +5779,7 @@ static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
const struct sh_pfc_soc_info r8a77950_pinmux_info = {
.name = "r8a77950_pfc",
.ops = &r8a77950_pinmux_ops,
.ops = &r8a77950_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

317
drivers/pinctrl/renesas/pfc-r8a77951.c
View File

@ -3268,20 +3268,13 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
static const unsigned int qspi0_data_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
/* QSPI0_IO2, QSPI0_IO3 */
PIN_QSPI0_IO2, PIN_QSPI0_IO3,
};
static const unsigned int qspi0_data4_mux[] = {
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
@ -3293,20 +3286,13 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
static const unsigned int qspi1_data_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
/* QSPI1_IO2, QSPI1_IO3 */
PIN_QSPI1_IO2, PIN_QSPI1_IO3,
};
static const unsigned int qspi1_data4_mux[] = {
static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
@ -3541,19 +3527,12 @@ static const unsigned int scif_clk_b_mux[] = {
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 2),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DAT0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK,
SD0_DAT2_MARK, SD0_DAT3_MARK,
};
@ -3579,19 +3558,12 @@ static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 8),
};
static const unsigned int sdhi1_data1_mux[] = {
SD1_DAT0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SD1_DAT0_MARK, SD1_DAT1_MARK,
SD1_DAT2_MARK, SD1_DAT3_MARK,
};
@ -3617,30 +3589,14 @@ static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(4, 2),
};
static const unsigned int sdhi2_data1_mux[] = {
SD2_DAT0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
};
static const unsigned int sdhi2_data4_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK,
SD2_DAT2_MARK, SD2_DAT3_MARK,
};
static const unsigned int sdhi2_data8_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi2_data8_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK,
SD2_DAT2_MARK, SD2_DAT3_MARK,
SD2_DAT4_MARK, SD2_DAT5_MARK,
@ -3689,30 +3645,14 @@ static const unsigned int sdhi2_ds_mux[] = {
SD2_DS_MARK,
};
/* - SDHI3 ------------------------------------------------------------------ */
static const unsigned int sdhi3_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(4, 9),
};
static const unsigned int sdhi3_data1_mux[] = {
SD3_DAT0_MARK,
};
static const unsigned int sdhi3_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
};
static const unsigned int sdhi3_data4_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
};
static const unsigned int sdhi3_data8_pins[] = {
static const unsigned int sdhi3_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
};
static const unsigned int sdhi3_data8_mux[] = {
static const unsigned int sdhi3_data_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
SD3_DAT4_MARK, SD3_DAT5_MARK,
@ -4071,81 +4011,61 @@ static const unsigned int vin4_data18_b_mux[] = {
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_a_pins = {
.data24 = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
},
static const unsigned int vin4_data_a_pins[] = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const union vin_data vin4_data_a_mux = {
.data24 = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const union vin_data vin4_data_b_pins = {
.data24 = {
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
},
};
static const union vin_data vin4_data_b_mux = {
.data24 = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const unsigned int vin4_g8_pins[] = {
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin4_g8_mux[] = {
static const unsigned int vin4_data_a_mux[] = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data_b_pins[] = {
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data_b_mux[] = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
@ -4177,37 +4097,21 @@ static const unsigned int vin4_clk_mux[] = {
};
/* - VIN5 ------------------------------------------------------------------- */
static const union vin_data16 vin5_data_pins = {
.data16 = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
},
};
static const union vin_data16 vin5_data_mux = {
.data16 = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
VI5_DATA14_MARK, VI5_DATA15_MARK,
},
};
static const unsigned int vin5_high8_pins[] = {
static const unsigned int vin5_data_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin5_high8_mux[] = {
static const unsigned int vin5_data_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
@ -4449,11 +4353,11 @@ static const struct {
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
BUS_DATA_PIN_GROUP(qspi1_data, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(sata0_devslp_a),
SH_PFC_PIN_GROUP(sata0_devslp_b),
SH_PFC_PIN_GROUP(scif0_data),
@ -4485,28 +4389,28 @@ static const struct {
SH_PFC_PIN_GROUP(scif5_clk_b),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
SH_PFC_PIN_GROUP(sdhi2_data8),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
BUS_DATA_PIN_GROUP(sdhi2_data, 8),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd_a),
SH_PFC_PIN_GROUP(sdhi2_wp_a),
SH_PFC_PIN_GROUP(sdhi2_cd_b),
SH_PFC_PIN_GROUP(sdhi2_wp_b),
SH_PFC_PIN_GROUP(sdhi2_ds),
SH_PFC_PIN_GROUP(sdhi3_data1),
SH_PFC_PIN_GROUP(sdhi3_data4),
SH_PFC_PIN_GROUP(sdhi3_data8),
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),
@ -4549,30 +4453,30 @@ static const struct {
SH_PFC_PIN_GROUP(usb2),
SH_PFC_PIN_GROUP(usb2_ch3),
SH_PFC_PIN_GROUP(usb30),
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(vin4_g8),
BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
VIN_DATA_PIN_GROUP(vin5_data, 8),
VIN_DATA_PIN_GROUP(vin5_data, 10),
VIN_DATA_PIN_GROUP(vin5_data, 12),
VIN_DATA_PIN_GROUP(vin5_data, 16),
SH_PFC_PIN_GROUP(vin5_high8),
BUS_DATA_PIN_GROUP(vin5_data, 8),
BUS_DATA_PIN_GROUP(vin5_data, 10),
BUS_DATA_PIN_GROUP(vin5_data, 12),
BUS_DATA_PIN_GROUP(vin5_data, 16),
SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
@ -6058,8 +5962,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ },
};
static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc,
unsigned int pin, u32 *pocctrl)
static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
@ -6316,7 +6219,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
.pin_to_pocctrl = r8a77951_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
@ -6325,7 +6228,7 @@ static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
.name = "r8a774e1_pfc",
.ops = &r8a77951_pinmux_ops,
.ops = &r8a77951_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@ -6350,7 +6253,7 @@ const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
#ifdef CONFIG_PINCTRL_PFC_R8A77951
const struct sh_pfc_soc_info r8a77951_pinmux_info = {
.name = "r8a77951_pfc",
.ops = &r8a77951_pinmux_ops,
.ops = &r8a77951_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

319
drivers/pinctrl/renesas/pfc-r8a7796.c
View File

@ -3274,20 +3274,13 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
static const unsigned int qspi0_data_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
/* QSPI0_IO2, QSPI0_IO3 */
PIN_QSPI0_IO2, PIN_QSPI0_IO3,
};
static const unsigned int qspi0_data4_mux[] = {
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
@ -3299,20 +3292,13 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
static const unsigned int qspi1_data_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
/* QSPI1_IO2, QSPI1_IO3 */
PIN_QSPI1_IO2, PIN_QSPI1_IO3,
};
static const unsigned int qspi1_data4_mux[] = {
static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
@ -3532,19 +3518,12 @@ static const unsigned int scif_clk_b_mux[] = {
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 2),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DAT0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK,
SD0_DAT2_MARK, SD0_DAT3_MARK,
};
@ -3570,19 +3549,12 @@ static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 8),
};
static const unsigned int sdhi1_data1_mux[] = {
SD1_DAT0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SD1_DAT0_MARK, SD1_DAT1_MARK,
SD1_DAT2_MARK, SD1_DAT3_MARK,
};
@ -3608,30 +3580,14 @@ static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(4, 2),
};
static const unsigned int sdhi2_data1_mux[] = {
SD2_DAT0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
};
static const unsigned int sdhi2_data4_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK,
SD2_DAT2_MARK, SD2_DAT3_MARK,
};
static const unsigned int sdhi2_data8_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi2_data8_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK,
SD2_DAT2_MARK, SD2_DAT3_MARK,
SD2_DAT4_MARK, SD2_DAT5_MARK,
@ -3680,30 +3636,14 @@ static const unsigned int sdhi2_ds_mux[] = {
SD2_DS_MARK,
};
/* - SDHI3 ------------------------------------------------------------------ */
static const unsigned int sdhi3_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(4, 9),
};
static const unsigned int sdhi3_data1_mux[] = {
SD3_DAT0_MARK,
};
static const unsigned int sdhi3_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
};
static const unsigned int sdhi3_data4_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
};
static const unsigned int sdhi3_data8_pins[] = {
static const unsigned int sdhi3_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
};
static const unsigned int sdhi3_data8_mux[] = {
static const unsigned int sdhi3_data_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
SD3_DAT4_MARK, SD3_DAT5_MARK,
@ -4046,81 +3986,61 @@ static const unsigned int vin4_data18_b_mux[] = {
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_a_pins = {
.data24 = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
},
static const unsigned int vin4_data_a_pins[] = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const union vin_data vin4_data_a_mux = {
.data24 = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const union vin_data vin4_data_b_pins = {
.data24 = {
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
},
};
static const union vin_data vin4_data_b_mux = {
.data24 = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const unsigned int vin4_g8_pins[] = {
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin4_g8_mux[] = {
static const unsigned int vin4_data_a_mux[] = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data_b_pins[] = {
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data_b_mux[] = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
@ -4152,37 +4072,21 @@ static const unsigned int vin4_clk_mux[] = {
};
/* - VIN5 ------------------------------------------------------------------- */
static const union vin_data16 vin5_data_pins = {
.data16 = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
},
};
static const union vin_data16 vin5_data_mux = {
.data16 = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
VI5_DATA14_MARK, VI5_DATA15_MARK,
},
};
static const unsigned int vin5_high8_pins[] = {
static const unsigned int vin5_data_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin5_high8_mux[] = {
static const unsigned int vin5_data_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
@ -4424,11 +4328,11 @@ static const struct {
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
BUS_DATA_PIN_GROUP(qspi1_data, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@ -4458,28 +4362,28 @@ static const struct {
SH_PFC_PIN_GROUP(scif5_clk_b),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
SH_PFC_PIN_GROUP(sdhi2_data8),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
BUS_DATA_PIN_GROUP(sdhi2_data, 8),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd_a),
SH_PFC_PIN_GROUP(sdhi2_wp_a),
SH_PFC_PIN_GROUP(sdhi2_cd_b),
SH_PFC_PIN_GROUP(sdhi2_wp_b),
SH_PFC_PIN_GROUP(sdhi2_ds),
SH_PFC_PIN_GROUP(sdhi3_data1),
SH_PFC_PIN_GROUP(sdhi3_data4),
SH_PFC_PIN_GROUP(sdhi3_data8),
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),
@ -4520,30 +4424,30 @@ static const struct {
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(vin4_g8),
BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
VIN_DATA_PIN_GROUP(vin5_data, 8),
VIN_DATA_PIN_GROUP(vin5_data, 10),
VIN_DATA_PIN_GROUP(vin5_data, 12),
VIN_DATA_PIN_GROUP(vin5_data, 16),
SH_PFC_PIN_GROUP(vin5_high8),
BUS_DATA_PIN_GROUP(vin5_data, 8),
BUS_DATA_PIN_GROUP(vin5_data, 10),
BUS_DATA_PIN_GROUP(vin5_data, 12),
BUS_DATA_PIN_GROUP(vin5_data, 16),
SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
@ -6009,8 +5913,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ },
};
static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc,
unsigned int pin, u32 *pocctrl)
static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
@ -6267,7 +6170,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
.pin_to_pocctrl = r8a7796_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
@ -6276,7 +6179,7 @@ static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
#ifdef CONFIG_PINCTRL_PFC_R8A774A1
const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
.name = "r8a774a1_pfc",
.ops = &r8a7796_pinmux_ops,
.ops = &r8a7796_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@ -6301,7 +6204,7 @@ const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
#ifdef CONFIG_PINCTRL_PFC_R8A77960
const struct sh_pfc_soc_info r8a77960_pinmux_info = {
.name = "r8a77960_pfc",
.ops = &r8a7796_pinmux_ops,
.ops = &r8a7796_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@ -6328,7 +6231,7 @@ const struct sh_pfc_soc_info r8a77960_pinmux_info = {
#ifdef CONFIG_PINCTRL_PFC_R8A77961
const struct sh_pfc_soc_info r8a77961_pinmux_info = {
.name = "r8a77961_pfc",
.ops = &r8a7796_pinmux_ops,
.ops = &r8a7796_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

333
drivers/pinctrl/renesas/pfc-r8a77965.c
View File

@ -3424,20 +3424,13 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
static const unsigned int qspi0_data_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
/* QSPI0_IO2, QSPI0_IO3 */
PIN_QSPI0_IO2, PIN_QSPI0_IO3,
};
static const unsigned int qspi0_data4_mux[] = {
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
@ -3449,20 +3442,13 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
static const unsigned int qspi1_data_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
/* QSPI1_IO2, QSPI1_IO3 */
PIN_QSPI1_IO2, PIN_QSPI1_IO3,
};
static const unsigned int qspi1_data4_mux[] = {
static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
@ -3698,22 +3684,13 @@ static const unsigned int scif_clk_b_mux[] = {
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 2),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DAT0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK,
SD0_DAT2_MARK, SD0_DAT3_MARK,
};
@ -3746,22 +3723,13 @@ static const unsigned int sdhi0_wp_mux[] = {
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 8),
};
static const unsigned int sdhi1_data1_mux[] = {
SD1_DAT0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SD1_DAT0_MARK, SD1_DAT1_MARK,
SD1_DAT2_MARK, SD1_DAT3_MARK,
};
@ -3794,27 +3762,7 @@ static const unsigned int sdhi1_wp_mux[] = {
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(4, 2),
};
static const unsigned int sdhi2_data1_mux[] = {
SD2_DAT0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
};
static const unsigned int sdhi2_data4_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK,
SD2_DAT2_MARK, SD2_DAT3_MARK,
};
static const unsigned int sdhi2_data8_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
@ -3822,7 +3770,7 @@ static const unsigned int sdhi2_data8_pins[] = {
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi2_data8_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK,
SD2_DAT2_MARK, SD2_DAT3_MARK,
SD2_DAT4_MARK, SD2_DAT5_MARK,
@ -3884,27 +3832,7 @@ static const unsigned int sdhi2_ds_mux[] = {
};
/* - SDHI3 ------------------------------------------------------------------ */
static const unsigned int sdhi3_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(4, 9),
};
static const unsigned int sdhi3_data1_mux[] = {
SD3_DAT0_MARK,
};
static const unsigned int sdhi3_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
};
static const unsigned int sdhi3_data4_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
};
static const unsigned int sdhi3_data8_pins[] = {
static const unsigned int sdhi3_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
@ -3912,7 +3840,7 @@ static const unsigned int sdhi3_data8_pins[] = {
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
};
static const unsigned int sdhi3_data8_mux[] = {
static const unsigned int sdhi3_data_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
SD3_DAT4_MARK, SD3_DAT5_MARK,
@ -4254,38 +4182,34 @@ static const unsigned int vin4_data18_a_mux[] = {
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_a_pins = {
.data24 = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
},
static const unsigned int vin4_data_a_pins[] = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const union vin_data vin4_data_a_mux = {
.data24 = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
static const unsigned int vin4_data_a_mux[] = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data18_b_pins[] = {
@ -4312,52 +4236,34 @@ static const unsigned int vin4_data18_b_mux[] = {
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_b_pins = {
.data24 = {
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
},
static const unsigned int vin4_data_b_pins[] = {
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const union vin_data vin4_data_b_mux = {
.data24 = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const unsigned int vin4_g8_pins[] = {
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin4_g8_mux[] = {
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
static const unsigned int vin4_data_b_mux[] = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_sync_pins[] = {
@ -4394,40 +4300,22 @@ static const unsigned int vin4_clk_mux[] = {
};
/* - VIN5 ------------------------------------------------------------------- */
static const union vin_data16 vin5_data_pins = {
.data16 = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
},
};
static const union vin_data16 vin5_data_mux = {
.data16 = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
VI5_DATA14_MARK, VI5_DATA15_MARK,
},
};
static const unsigned int vin5_high8_pins[] = {
static const unsigned int vin5_data_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin5_high8_mux[] = {
static const unsigned int vin5_data_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
@ -4674,11 +4562,11 @@ static const struct {
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
BUS_DATA_PIN_GROUP(qspi1_data, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(sata0_devslp_a),
SH_PFC_PIN_GROUP(sata0_devslp_b),
SH_PFC_PIN_GROUP(scif0_data),
@ -4710,28 +4598,28 @@ static const struct {
SH_PFC_PIN_GROUP(scif5_clk_b),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
SH_PFC_PIN_GROUP(sdhi2_data8),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
BUS_DATA_PIN_GROUP(sdhi2_data, 8),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd_a),
SH_PFC_PIN_GROUP(sdhi2_wp_a),
SH_PFC_PIN_GROUP(sdhi2_cd_b),
SH_PFC_PIN_GROUP(sdhi2_wp_b),
SH_PFC_PIN_GROUP(sdhi2_ds),
SH_PFC_PIN_GROUP(sdhi3_data1),
SH_PFC_PIN_GROUP(sdhi3_data4),
SH_PFC_PIN_GROUP(sdhi3_data8),
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),
@ -4772,30 +4660,30 @@ static const struct {
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(vin4_g8),
BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
VIN_DATA_PIN_GROUP(vin5_data, 8),
VIN_DATA_PIN_GROUP(vin5_data, 10),
VIN_DATA_PIN_GROUP(vin5_data, 12),
VIN_DATA_PIN_GROUP(vin5_data, 16),
SH_PFC_PIN_GROUP(vin5_high8),
BUS_DATA_PIN_GROUP(vin5_data, 8),
BUS_DATA_PIN_GROUP(vin5_data, 10),
BUS_DATA_PIN_GROUP(vin5_data, 12),
BUS_DATA_PIN_GROUP(vin5_data, 16),
SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
@ -6266,8 +6154,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ },
};
static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc,
unsigned int pin, u32 *pocctrl)
static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
@ -6524,7 +6411,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a77965_pfc_ops = {
.pin_to_pocctrl = r8a77965_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
@ -6533,7 +6420,7 @@ static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
#ifdef CONFIG_PINCTRL_PFC_R8A774B1
const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
.name = "r8a774b1_pfc",
.ops = &r8a77965_pinmux_ops,
.ops = &r8a77965_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@ -6558,7 +6445,7 @@ const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
#ifdef CONFIG_PINCTRL_PFC_R8A77965
const struct sh_pfc_soc_info r8a77965_pinmux_info = {
.name = "r8a77965_pfc",
.ops = &r8a77965_pinmux_ops,
.ops = &r8a77965_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

163
drivers/pinctrl/renesas/pfc-r8a77970.c
View File

@ -1102,30 +1102,14 @@ static const unsigned int intc_ex_irq5_mux[] = {
};
/* - MMC -------------------------------------------------------------------- */
static const unsigned int mmc_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 6),
};
static const unsigned int mmc_data1_mux[] = {
MMC_D0_MARK,
};
static const unsigned int mmc_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
};
static const unsigned int mmc_data4_mux[] = {
MMC_D0_MARK, MMC_D1_MARK,
MMC_D2_MARK, MMC_D3_MARK,
};
static const unsigned int mmc_data8_pins[] = {
static const unsigned int mmc_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
};
static const unsigned int mmc_data8_mux[] = {
static const unsigned int mmc_data_mux[] = {
MMC_D0_MARK, MMC_D1_MARK,
MMC_D2_MARK, MMC_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK,
@ -1393,22 +1377,6 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
};
static const unsigned int qspi0_data4_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK
};
/* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = {
@ -1418,36 +1386,14 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
};
static const unsigned int qspi1_data4_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK
};
/* - RPC -------------------------------------------------------------------- */
static const unsigned int rpc_clk1_pins[] = {
static const unsigned int rpc_clk_pins[] = {
/* Octal-SPI flash: C/SCLK */
RCAR_GP_PIN(5, 0),
};
static const unsigned int rpc_clk1_mux[] = {
QSPI0_SPCLK_MARK,
};
static const unsigned int rpc_clk2_pins[] = {
/* HyperFlash: CK, CK# */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
};
static const unsigned int rpc_clk2_mux[] = {
static const unsigned int rpc_clk_mux[] = {
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
};
static const unsigned int rpc_ctrl_pins[] = {
@ -1639,25 +1585,21 @@ static const unsigned int tmu_tclk2_b_mux[] = {
};
/* - VIN0 ------------------------------------------------------------------- */
static const union vin_data12 vin0_data_pins = {
.data12 = {
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
},
static const unsigned int vin0_data_pins[] = {
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
};
static const union vin_data12 vin0_data_mux = {
.data12 = {
VI0_DATA0_MARK, VI0_DATA1_MARK,
VI0_DATA2_MARK, VI0_DATA3_MARK,
VI0_DATA4_MARK, VI0_DATA5_MARK,
VI0_DATA6_MARK, VI0_DATA7_MARK,
VI0_DATA8_MARK, VI0_DATA9_MARK,
VI0_DATA10_MARK, VI0_DATA11_MARK,
},
static const unsigned int vin0_data_mux[] = {
VI0_DATA0_MARK, VI0_DATA1_MARK,
VI0_DATA2_MARK, VI0_DATA3_MARK,
VI0_DATA4_MARK, VI0_DATA5_MARK,
VI0_DATA6_MARK, VI0_DATA7_MARK,
VI0_DATA8_MARK, VI0_DATA9_MARK,
VI0_DATA10_MARK, VI0_DATA11_MARK,
};
static const unsigned int vin0_sync_pins[] = {
/* HSYNC#, VSYNC# */
@ -1689,25 +1631,21 @@ static const unsigned int vin0_clk_mux[] = {
};
/* - VIN1 ------------------------------------------------------------------- */
static const union vin_data12 vin1_data_pins = {
.data12 = {
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
},
static const unsigned int vin1_data_pins[] = {
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
};
static const union vin_data12 vin1_data_mux = {
.data12 = {
VI1_DATA0_MARK, VI1_DATA1_MARK,
VI1_DATA2_MARK, VI1_DATA3_MARK,
VI1_DATA4_MARK, VI1_DATA5_MARK,
VI1_DATA6_MARK, VI1_DATA7_MARK,
VI1_DATA8_MARK, VI1_DATA9_MARK,
VI1_DATA10_MARK, VI1_DATA11_MARK,
},
static const unsigned int vin1_data_mux[] = {
VI1_DATA0_MARK, VI1_DATA1_MARK,
VI1_DATA2_MARK, VI1_DATA3_MARK,
VI1_DATA4_MARK, VI1_DATA5_MARK,
VI1_DATA6_MARK, VI1_DATA7_MARK,
VI1_DATA8_MARK, VI1_DATA9_MARK,
VI1_DATA10_MARK, VI1_DATA11_MARK,
};
static const unsigned int vin1_sync_pins[] = {
/* HSYNC#, VSYNC# */
@ -1783,9 +1721,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(intc_ex_irq3),
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
SH_PFC_PIN_GROUP(mmc_data1),
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
@ -1822,13 +1760,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(pwm4_a),
SH_PFC_PIN_GROUP(pwm4_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(rpc_clk1),
SH_PFC_PIN_GROUP(rpc_clk2),
SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
BUS_DATA_PIN_GROUP(rpc_clk, 1),
BUS_DATA_PIN_GROUP(rpc_clk, 2),
SH_PFC_PIN_GROUP(rpc_ctrl),
SH_PFC_PIN_GROUP(rpc_data),
SH_PFC_PIN_GROUP(rpc_reset),
@ -1853,16 +1791,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
VIN_DATA_PIN_GROUP(vin0_data, 8),
VIN_DATA_PIN_GROUP(vin0_data, 10),
VIN_DATA_PIN_GROUP(vin0_data, 12),
BUS_DATA_PIN_GROUP(vin0_data, 8),
BUS_DATA_PIN_GROUP(vin0_data, 10),
BUS_DATA_PIN_GROUP(vin0_data, 12),
SH_PFC_PIN_GROUP(vin0_sync),
SH_PFC_PIN_GROUP(vin0_field),
SH_PFC_PIN_GROUP(vin0_clkenb),
SH_PFC_PIN_GROUP(vin0_clk),
VIN_DATA_PIN_GROUP(vin1_data, 8),
VIN_DATA_PIN_GROUP(vin1_data, 10),
VIN_DATA_PIN_GROUP(vin1_data, 12),
BUS_DATA_PIN_GROUP(vin1_data, 8),
BUS_DATA_PIN_GROUP(vin1_data, 10),
BUS_DATA_PIN_GROUP(vin1_data, 12),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
@ -2496,8 +2434,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ },
};
static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
u32 *pocctrl)
static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
@ -2656,7 +2593,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations pinmux_ops = {
static const struct sh_pfc_soc_operations r8a77970_pfc_ops = {
.pin_to_pocctrl = r8a77970_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
@ -2664,7 +2601,7 @@ static const struct sh_pfc_soc_operations pinmux_ops = {
const struct sh_pfc_soc_info r8a77970_pinmux_info = {
.name = "r8a77970_pfc",
.ops = &pinmux_ops,
.ops = &r8a77970_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

193
drivers/pinctrl/renesas/pfc-r8a77980.c
View File

@ -1365,30 +1365,14 @@ static const unsigned int intc_ex_irq5_mux[] = {
};
/* - MMC -------------------------------------------------------------------- */
static const unsigned int mmc_data1_pins[] = {
/* MMC_D0 */
RCAR_GP_PIN(3, 8),
};
static const unsigned int mmc_data1_mux[] = {
MMC_D0_MARK,
};
static const unsigned int mmc_data4_pins[] = {
/* MMC_D[0:3] */
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int mmc_data4_mux[] = {
MMC_D0_MARK, MMC_D1_MARK,
MMC_D2_MARK, MMC_D3_MARK,
};
static const unsigned int mmc_data8_pins[] = {
static const unsigned int mmc_data_pins[] = {
/* MMC_D[0:7] */
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
};
static const unsigned int mmc_data8_mux[] = {
static const unsigned int mmc_data_mux[] = {
MMC_D0_MARK, MMC_D1_MARK,
MMC_D2_MARK, MMC_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK,
@ -1687,22 +1671,6 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
};
static const unsigned int qspi0_data4_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK
};
/* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = {
@ -1712,36 +1680,14 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
};
static const unsigned int qspi1_data4_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK
};
/* - RPC -------------------------------------------------------------------- */
static const unsigned int rpc_clk1_pins[] = {
static const unsigned int rpc_clk_pins[] = {
/* Octal-SPI flash: C/SCLK */
RCAR_GP_PIN(5, 0),
};
static const unsigned int rpc_clk1_mux[] = {
QSPI0_SPCLK_MARK,
};
static const unsigned int rpc_clk2_pins[] = {
/* HyperFlash: CK, CK# */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
};
static const unsigned int rpc_clk2_mux[] = {
static const unsigned int rpc_clk_mux[] = {
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
};
static const unsigned int rpc_ctrl_pins[] = {
@ -1963,37 +1909,33 @@ static const unsigned int tpu_to3_mux[] = {
};
/* - VIN0 ------------------------------------------------------------------- */
static const union vin_data vin0_data_pins = {
.data24 = {
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
},
static const unsigned int vin0_data_pins[] = {
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
};
static const union vin_data vin0_data_mux = {
.data24 = {
VI0_DATA0_MARK, VI0_DATA1_MARK,
VI0_DATA2_MARK, VI0_DATA3_MARK,
VI0_DATA4_MARK, VI0_DATA5_MARK,
VI0_DATA6_MARK, VI0_DATA7_MARK,
VI0_DATA8_MARK, VI0_DATA9_MARK,
VI0_DATA10_MARK, VI0_DATA11_MARK,
VI0_DATA12_MARK, VI0_DATA13_MARK,
VI0_DATA14_MARK, VI0_DATA15_MARK,
VI0_DATA16_MARK, VI0_DATA17_MARK,
VI0_DATA18_MARK, VI0_DATA19_MARK,
VI0_DATA20_MARK, VI0_DATA21_MARK,
VI0_DATA22_MARK, VI0_DATA23_MARK,
},
static const unsigned int vin0_data_mux[] = {
VI0_DATA0_MARK, VI0_DATA1_MARK,
VI0_DATA2_MARK, VI0_DATA3_MARK,
VI0_DATA4_MARK, VI0_DATA5_MARK,
VI0_DATA6_MARK, VI0_DATA7_MARK,
VI0_DATA8_MARK, VI0_DATA9_MARK,
VI0_DATA10_MARK, VI0_DATA11_MARK,
VI0_DATA12_MARK, VI0_DATA13_MARK,
VI0_DATA14_MARK, VI0_DATA15_MARK,
VI0_DATA16_MARK, VI0_DATA17_MARK,
VI0_DATA18_MARK, VI0_DATA19_MARK,
VI0_DATA20_MARK, VI0_DATA21_MARK,
VI0_DATA22_MARK, VI0_DATA23_MARK,
};
static const unsigned int vin0_data18_pins[] = {
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
@ -2047,25 +1989,21 @@ static const unsigned int vin0_clk_mux[] = {
};
/* - VIN1 ------------------------------------------------------------------- */
static const union vin_data12 vin1_data_pins = {
.data12 = {
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
},
static const unsigned int vin1_data_pins[] = {
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
};
static const union vin_data12 vin1_data_mux = {
.data12 = {
VI1_DATA0_MARK, VI1_DATA1_MARK,
VI1_DATA2_MARK, VI1_DATA3_MARK,
VI1_DATA4_MARK, VI1_DATA5_MARK,
VI1_DATA6_MARK, VI1_DATA7_MARK,
VI1_DATA8_MARK, VI1_DATA9_MARK,
VI1_DATA10_MARK, VI1_DATA11_MARK,
},
static const unsigned int vin1_data_mux[] = {
VI1_DATA0_MARK, VI1_DATA1_MARK,
VI1_DATA2_MARK, VI1_DATA3_MARK,
VI1_DATA4_MARK, VI1_DATA5_MARK,
VI1_DATA6_MARK, VI1_DATA7_MARK,
VI1_DATA8_MARK, VI1_DATA9_MARK,
VI1_DATA10_MARK, VI1_DATA11_MARK,
};
static const unsigned int vin1_sync_pins[] = {
/* VI1_VSYNC#, VI1_HSYNC# */
@ -2156,9 +2094,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(intc_ex_irq3),
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
SH_PFC_PIN_GROUP(mmc_data1),
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(mmc_cd),
SH_PFC_PIN_GROUP(mmc_wp),
@ -2198,13 +2136,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(pwm4_a),
SH_PFC_PIN_GROUP(pwm4_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(rpc_clk1),
SH_PFC_PIN_GROUP(rpc_clk2),
SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
BUS_DATA_PIN_GROUP(rpc_clk, 1),
BUS_DATA_PIN_GROUP(rpc_clk, 2),
SH_PFC_PIN_GROUP(rpc_ctrl),
SH_PFC_PIN_GROUP(rpc_data),
SH_PFC_PIN_GROUP(rpc_reset),
@ -2233,20 +2171,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(tpu_to1),
SH_PFC_PIN_GROUP(tpu_to2),
SH_PFC_PIN_GROUP(tpu_to3),
VIN_DATA_PIN_GROUP(vin0_data, 8),
VIN_DATA_PIN_GROUP(vin0_data, 10),
VIN_DATA_PIN_GROUP(vin0_data, 12),
VIN_DATA_PIN_GROUP(vin0_data, 16),
BUS_DATA_PIN_GROUP(vin0_data, 8),
BUS_DATA_PIN_GROUP(vin0_data, 10),
BUS_DATA_PIN_GROUP(vin0_data, 12),
BUS_DATA_PIN_GROUP(vin0_data, 16),
SH_PFC_PIN_GROUP(vin0_data18),
VIN_DATA_PIN_GROUP(vin0_data, 20),
VIN_DATA_PIN_GROUP(vin0_data, 24),
BUS_DATA_PIN_GROUP(vin0_data, 20),
BUS_DATA_PIN_GROUP(vin0_data, 24),
SH_PFC_PIN_GROUP(vin0_sync),
SH_PFC_PIN_GROUP(vin0_field),
SH_PFC_PIN_GROUP(vin0_clkenb),
SH_PFC_PIN_GROUP(vin0_clk),
VIN_DATA_PIN_GROUP(vin1_data, 8),
VIN_DATA_PIN_GROUP(vin1_data, 10),
VIN_DATA_PIN_GROUP(vin1_data, 12),
BUS_DATA_PIN_GROUP(vin1_data, 8),
BUS_DATA_PIN_GROUP(vin1_data, 10),
BUS_DATA_PIN_GROUP(vin1_data, 12),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
@ -2940,8 +2878,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ },
};
static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
u32 *pocctrl)
static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
@ -3139,7 +3076,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations pinmux_ops = {
static const struct sh_pfc_soc_operations r8a77980_pfc_ops = {
.pin_to_pocctrl = r8a77980_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
@ -3147,7 +3084,7 @@ static const struct sh_pfc_soc_operations pinmux_ops = {
const struct sh_pfc_soc_info r8a77980_pinmux_info = {
.name = "r8a77980_pfc",
.ops = &pinmux_ops,
.ops = &r8a77980_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

311
drivers/pinctrl/renesas/pfc-r8a77990.c
View File

@ -2827,20 +2827,13 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
static const unsigned int qspi0_data_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
/* QSPI0_IO2, QSPI0_IO3 */
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
};
static const unsigned int qspi0_data4_mux[] = {
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
@ -2852,20 +2845,13 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
static const unsigned int qspi1_data_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
/* QSPI1_IO2, QSPI1_IO3 */
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
};
static const unsigned int qspi1_data4_mux[] = {
static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
@ -3148,22 +3134,13 @@ static const unsigned int scif_clk_b_mux[] = {
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 2),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DAT0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK,
SD0_DAT2_MARK, SD0_DAT3_MARK,
};
@ -3196,22 +3173,13 @@ static const unsigned int sdhi0_wp_mux[] = {
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 8),
};
static const unsigned int sdhi1_data1_mux[] = {
SD1_DAT0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SD1_DAT0_MARK, SD1_DAT1_MARK,
SD1_DAT2_MARK, SD1_DAT3_MARK,
};
@ -3244,27 +3212,7 @@ static const unsigned int sdhi1_wp_mux[] = {
};
/* - SDHI3 ------------------------------------------------------------------ */
static const unsigned int sdhi3_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(4, 2),
};
static const unsigned int sdhi3_data1_mux[] = {
SD3_DAT0_MARK,
};
static const unsigned int sdhi3_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
};
static const unsigned int sdhi3_data4_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
};
static const unsigned int sdhi3_data8_pins[] = {
static const unsigned int sdhi3_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
@ -3272,7 +3220,7 @@ static const unsigned int sdhi3_data8_pins[] = {
RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
};
static const unsigned int sdhi3_data8_mux[] = {
static const unsigned int sdhi3_data_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
SD3_DAT4_MARK, SD3_DAT5_MARK,
@ -3614,38 +3562,34 @@ static const unsigned int vin4_data18_a_mux[] = {
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_a_pins = {
.data24 = {
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
},
static const unsigned int vin4_data_a_pins[] = {
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
};
static const union vin_data vin4_data_a_mux = {
.data24 = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
static const unsigned int vin4_data_a_mux[] = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data18_b_pins[] = {
@ -3672,52 +3616,34 @@ static const unsigned int vin4_data18_b_mux[] = {
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_b_pins = {
.data24 = {
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
},
};
static const union vin_data vin4_data_b_mux = {
.data24 = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const unsigned int vin4_g8_pins[] = {
static const unsigned int vin4_data_b_pins[] = {
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
};
static const unsigned int vin4_g8_mux[] = {
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
static const unsigned int vin4_data_b_mux[] = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_sync_pins[] = {
@ -3754,30 +3680,26 @@ static const unsigned int vin4_clk_mux[] = {
};
/* - VIN5 ------------------------------------------------------------------- */
static const union vin_data16 vin5_data_a_pins = {
.data16 = {
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
},
static const unsigned int vin5_data_a_pins[] = {
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
};
static const union vin_data16 vin5_data_a_mux = {
.data16 = {
VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
},
static const unsigned int vin5_data_a_mux[] = {
VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
};
static const unsigned int vin5_data8_b_pins[] = {
@ -3794,20 +3716,6 @@ static const unsigned int vin5_data8_b_mux[] = {
VI5_DATA6_B_MARK, VI5_DATA7_B_MARK,
};
static const unsigned int vin5_high8_pins[] = {
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
};
static const unsigned int vin5_high8_mux[] = {
VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
};
static const unsigned int vin5_sync_a_pins[] = {
/* HSYNC_N, VSYNC_N */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
@ -3999,11 +3907,11 @@ static const struct {
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
BUS_DATA_PIN_GROUP(qspi1_data, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_clk_a),
SH_PFC_PIN_GROUP(scif0_ctrl_a),
@ -4034,19 +3942,19 @@ static const struct {
SH_PFC_PIN_GROUP(scif5_data_c),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi3_data1),
SH_PFC_PIN_GROUP(sdhi3_data4),
SH_PFC_PIN_GROUP(sdhi3_data8),
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),
@ -4081,31 +3989,31 @@ static const struct {
SH_PFC_PIN_GROUP(usb0_id),
SH_PFC_PIN_GROUP(usb30),
SH_PFC_PIN_GROUP(usb30_id),
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(vin4_g8),
BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
VIN_DATA_PIN_GROUP(vin5_data, 8, _a),
VIN_DATA_PIN_GROUP(vin5_data, 10, _a),
VIN_DATA_PIN_GROUP(vin5_data, 12, _a),
VIN_DATA_PIN_GROUP(vin5_data, 16, _a),
BUS_DATA_PIN_GROUP(vin5_data, 8, _a),
BUS_DATA_PIN_GROUP(vin5_data, 10, _a),
BUS_DATA_PIN_GROUP(vin5_data, 12, _a),
BUS_DATA_PIN_GROUP(vin5_data, 16, _a),
SH_PFC_PIN_GROUP(vin5_data8_b),
SH_PFC_PIN_GROUP(vin5_high8),
SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data_a, 8, 8),
SH_PFC_PIN_GROUP(vin5_sync_a),
SH_PFC_PIN_GROUP(vin5_field_a),
SH_PFC_PIN_GROUP(vin5_clkenb_a),
@ -5133,8 +5041,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ },
};
static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
u32 *pocctrl)
static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
@ -5357,7 +5264,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a77990_pfc_ops = {
.pin_to_pocctrl = r8a77990_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
@ -5366,7 +5273,7 @@ static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
#ifdef CONFIG_PINCTRL_PFC_R8A774C0
const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
.name = "r8a774c0_pfc",
.ops = &r8a77990_pinmux_ops,
.ops = &r8a77990_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@ -5390,7 +5297,7 @@ const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
#ifdef CONFIG_PINCTRL_PFC_R8A77990
const struct sh_pfc_soc_info r8a77990_pinmux_info = {
.name = "r8a77990_pfc",
.ops = &r8a77990_pinmux_ops,
.ops = &r8a77990_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

102
drivers/pinctrl/renesas/pfc-r8a77995.c
View File

@ -1266,30 +1266,14 @@ static const unsigned int mlb_3pin_mux[] = {
};
/* - MMC ------------------------------------------------------------------- */
static const unsigned int mmc_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(3, 2),
};
static const unsigned int mmc_data1_mux[] = {
MMC_D0_MARK,
};
static const unsigned int mmc_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
static const unsigned int mmc_data4_mux[] = {
MMC_D0_MARK, MMC_D1_MARK,
MMC_D2_MARK, MMC_D3_MARK,
};
static const unsigned int mmc_data8_pins[] = {
static const unsigned int mmc_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
};
static const unsigned int mmc_data8_mux[] = {
static const unsigned int mmc_data_mux[] = {
MMC_D0_MARK, MMC_D1_MARK,
MMC_D2_MARK, MMC_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK,
@ -1958,37 +1942,33 @@ static const unsigned int vin4_data18_mux[] = {
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_pins = {
.data24 = {
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
},
static const unsigned int vin4_data_pins[] = {
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
};
static const union vin_data vin4_data_mux = {
.data24 = {
VI4_DATA0_MARK, VI4_DATA1_MARK,
VI4_DATA2_MARK, VI4_DATA3_MARK,
VI4_DATA4_MARK, VI4_DATA5_MARK,
VI4_DATA6_MARK, VI4_DATA7_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
static const unsigned int vin4_data_mux[] = {
VI4_DATA0_MARK, VI4_DATA1_MARK,
VI4_DATA2_MARK, VI4_DATA3_MARK,
VI4_DATA4_MARK, VI4_DATA5_MARK,
VI4_DATA6_MARK, VI4_DATA7_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
@ -2058,9 +2038,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c3_a),
SH_PFC_PIN_GROUP(i2c3_b),
SH_PFC_PIN_GROUP(mlb_3pin),
SH_PFC_PIN_GROUP(mmc_data1),
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
@ -2137,13 +2117,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi4_ctrl_b),
SH_PFC_PIN_GROUP(ssi4_data_b),
SH_PFC_PIN_GROUP(usb0),
VIN_DATA_PIN_GROUP(vin4_data, 8),
VIN_DATA_PIN_GROUP(vin4_data, 10),
VIN_DATA_PIN_GROUP(vin4_data, 12),
VIN_DATA_PIN_GROUP(vin4_data, 16),
BUS_DATA_PIN_GROUP(vin4_data, 8),
BUS_DATA_PIN_GROUP(vin4_data, 10),
BUS_DATA_PIN_GROUP(vin4_data, 12),
BUS_DATA_PIN_GROUP(vin4_data, 16),
SH_PFC_PIN_GROUP(vin4_data18),
VIN_DATA_PIN_GROUP(vin4_data, 20),
VIN_DATA_PIN_GROUP(vin4_data, 24),
BUS_DATA_PIN_GROUP(vin4_data, 20),
BUS_DATA_PIN_GROUP(vin4_data, 24),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
@ -2856,7 +2836,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
@ -3092,7 +3072,7 @@ r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
const struct pinmux_bias_reg *reg;
unsigned int bit;
reg = rcar_pin_to_bias_reg(pfc, pin, &bit);
reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
if (!reg)
return reg;
@ -3158,7 +3138,7 @@ static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
sh_pfc_write(pfc, reg->puen, enable);
}
static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a77995_pfc_ops = {
.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
.get_bias = r8a77995_pinmux_get_bias,
.set_bias = r8a77995_pinmux_set_bias,
@ -3166,7 +3146,7 @@ static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
const struct sh_pfc_soc_info r8a77995_pinmux_info = {
.name = "r8a77995_pfc",
.ops = &r8a77995_pinmux_ops,
.ops = &r8a77995_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

63
drivers/pinctrl/renesas/pfc-r8a779a0.c
View File

@ -2009,30 +2009,14 @@ static const unsigned int intc_ex_irq5_mux[] = {
};
/* - MMC -------------------------------------------------------------------- */
static const unsigned int mmc_data1_pins[] = {
/* MMC_SD_D0 */
RCAR_GP_PIN(0, 19),
};
static const unsigned int mmc_data1_mux[] = {
MMC_SD_D0_MARK,
};
static const unsigned int mmc_data4_pins[] = {
/* MMC_SD_D[0:3] */
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
};
static const unsigned int mmc_data4_mux[] = {
MMC_SD_D0_MARK, MMC_SD_D1_MARK,
MMC_SD_D2_MARK, MMC_SD_D3_MARK,
};
static const unsigned int mmc_data8_pins[] = {
static const unsigned int mmc_data_pins[] = {
/* MMC_SD_D[0:3], MMC_D[4:7] */
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27),
};
static const unsigned int mmc_data8_mux[] = {
static const unsigned int mmc_data_mux[] = {
MMC_SD_D0_MARK, MMC_SD_D1_MARK,
MMC_SD_D2_MARK, MMC_SD_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK,
@ -2384,19 +2368,12 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
static const unsigned int qspi0_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
};
static const unsigned int qspi0_data4_mux[] = {
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK
};
@ -2409,19 +2386,12 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
static const unsigned int qspi1_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
};
static const unsigned int qspi1_data4_mux[] = {
static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK
};
@ -2715,9 +2685,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
SH_PFC_PIN_GROUP(mmc_data1),
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(mmc_cd),
SH_PFC_PIN_GROUP(mmc_wp),
@ -2767,11 +2737,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(pwm4),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
BUS_DATA_PIN_GROUP(qspi1_data, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
@ -4041,8 +4011,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ },
};
static int r8a779a0_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
u32 *pocctrl)
static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
@ -4429,7 +4398,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
static const struct sh_pfc_soc_operations pinmux_ops = {
static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = {
.pin_to_pocctrl = r8a779a0_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
@ -4437,7 +4406,7 @@ static const struct sh_pfc_soc_operations pinmux_ops = {
const struct sh_pfc_soc_info r8a779a0_pinmux_info = {
.name = "r8a779a0_pfc",
.ops = &pinmux_ops,
.ops = &r8a779a0_pfc_ops,
.unlock_reg = 0x1ff, /* PMMRn mask */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

2126
drivers/pinctrl/renesas/pfc-r8a779f0.c Normal file
View File

File diff suppressed because it is too large Load Diff

1
drivers/pinctrl/renesas/pfc-sh7203.c
View File

@ -6,7 +6,6 @@
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <cpu/sh7203.h>
#include "sh_pfc.h"

1
drivers/pinctrl/renesas/pfc-sh7264.c
View File

@ -6,7 +6,6 @@
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <cpu/sh7264.h>
#include "sh_pfc.h"

1
drivers/pinctrl/renesas/pfc-sh7269.c
View File

@ -7,7 +7,6 @@
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <cpu/sh7269.h>
#include "sh_pfc.h"

269
drivers/pinctrl/renesas/pfc-sh73a0.c
View File

@ -1777,35 +1777,11 @@ static const unsigned int irda_1_mux[] = {
PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
};
/* - KEYSC ------------------------------------------------------------------ */
static const unsigned int keysc_in5_pins[] = {
/* KEYIN[0:4] */
66, 67, 68, 69, 70,
};
static const unsigned int keysc_in5_mux[] = {
KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
KEYIN4_MARK,
};
static const unsigned int keysc_in6_pins[] = {
/* KEYIN[0:5] */
66, 67, 68, 69, 70, 71,
};
static const unsigned int keysc_in6_mux[] = {
KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
KEYIN4_MARK, KEYIN5_MARK,
};
static const unsigned int keysc_in7_pins[] = {
/* KEYIN[0:6] */
66, 67, 68, 69, 70, 71, 72,
};
static const unsigned int keysc_in7_mux[] = {
KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
};
static const unsigned int keysc_in8_pins[] = {
static const unsigned int keysc_in_pins[] = {
/* KEYIN[0:7] */
66, 67, 68, 69, 70, 71, 72, 73,
};
static const unsigned int keysc_in8_mux[] = {
static const unsigned int keysc_in_mux[] = {
KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
};
@ -1936,65 +1912,13 @@ static const unsigned int keysc_out11_1_mux[] = {
PORT143_KEYOUT11_MARK,
};
/* - LCD -------------------------------------------------------------------- */
static const unsigned int lcd_data8_pins[] = {
/* D[0:7] */
192, 193, 194, 195, 196, 197, 198, 199,
};
static const unsigned int lcd_data8_mux[] = {
LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
};
static const unsigned int lcd_data9_pins[] = {
/* D[0:8] */
192, 193, 194, 195, 196, 197, 198, 199,
200,
};
static const unsigned int lcd_data9_mux[] = {
LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
LCDD8_MARK,
};
static const unsigned int lcd_data12_pins[] = {
/* D[0:11] */
192, 193, 194, 195, 196, 197, 198, 199,
200, 201, 202, 203,
};
static const unsigned int lcd_data12_mux[] = {
LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
};
static const unsigned int lcd_data16_pins[] = {
/* D[0:15] */
192, 193, 194, 195, 196, 197, 198, 199,
200, 201, 202, 203, 204, 205, 206, 207,
};
static const unsigned int lcd_data16_mux[] = {
LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
};
static const unsigned int lcd_data18_pins[] = {
/* D[0:17] */
192, 193, 194, 195, 196, 197, 198, 199,
200, 201, 202, 203, 204, 205, 206, 207,
208, 209,
};
static const unsigned int lcd_data18_mux[] = {
LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
LCDD16_MARK, LCDD17_MARK,
};
static const unsigned int lcd_data24_pins[] = {
static const unsigned int lcd_data_pins[] = {
/* D[0:23] */
192, 193, 194, 195, 196, 197, 198, 199,
200, 201, 202, 203, 204, 205, 206, 207,
208, 209, 210, 211, 212, 213, 214, 215
};
static const unsigned int lcd_data24_mux[] = {
static const unsigned int lcd_data_mux[] = {
LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
@ -2031,65 +1955,13 @@ static const unsigned int lcd_sys_mux[] = {
LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
};
/* - LCD2 ------------------------------------------------------------------- */
static const unsigned int lcd2_data8_pins[] = {
/* D[0:7] */
128, 129, 142, 143, 144, 145, 138, 139,
};
static const unsigned int lcd2_data8_mux[] = {
LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
};
static const unsigned int lcd2_data9_pins[] = {
/* D[0:8] */
128, 129, 142, 143, 144, 145, 138, 139,
140,
};
static const unsigned int lcd2_data9_mux[] = {
LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
LCD2D8_MARK,
};
static const unsigned int lcd2_data12_pins[] = {
/* D[0:11] */
128, 129, 142, 143, 144, 145, 138, 139,
140, 141, 130, 131,
};
static const unsigned int lcd2_data12_mux[] = {
LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
};
static const unsigned int lcd2_data16_pins[] = {
/* D[0:15] */
128, 129, 142, 143, 144, 145, 138, 139,
140, 141, 130, 131, 132, 133, 134, 135,
};
static const unsigned int lcd2_data16_mux[] = {
LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
};
static const unsigned int lcd2_data18_pins[] = {
/* D[0:17] */
128, 129, 142, 143, 144, 145, 138, 139,
140, 141, 130, 131, 132, 133, 134, 135,
136, 137,
};
static const unsigned int lcd2_data18_mux[] = {
LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
LCD2D16_MARK, LCD2D17_MARK,
};
static const unsigned int lcd2_data24_pins[] = {
static const unsigned int lcd2_data_pins[] = {
/* D[0:23] */
128, 129, 142, 143, 144, 145, 138, 139,
140, 141, 130, 131, 132, 133, 134, 135,
136, 137, 146, 147, 234, 235, 238, 239
};
static const unsigned int lcd2_data24_mux[] = {
static const unsigned int lcd2_data_mux[] = {
LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
@ -2130,25 +2002,11 @@ static const unsigned int lcd2_sys_1_mux[] = {
LCD2RD__MARK, PORT217_LCD2RS_MARK,
};
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc0_data1_0_pins[] = {
/* D[0] */
271,
};
static const unsigned int mmc0_data1_0_mux[] = {
MMCD0_0_MARK,
};
static const unsigned int mmc0_data4_0_pins[] = {
/* D[0:3] */
271, 272, 273, 274,
};
static const unsigned int mmc0_data4_0_mux[] = {
MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
};
static const unsigned int mmc0_data8_0_pins[] = {
static const unsigned int mmc0_data_0_pins[] = {
/* D[0:7] */
271, 272, 273, 274, 275, 276, 277, 278,
};
static const unsigned int mmc0_data8_0_mux[] = {
static const unsigned int mmc0_data_0_mux[] = {
MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
};
@ -2160,25 +2018,11 @@ static const unsigned int mmc0_ctrl_0_mux[] = {
MMCCMD0_MARK, MMCCLK0_MARK,
};
static const unsigned int mmc0_data1_1_pins[] = {
/* D[0] */
305,
};
static const unsigned int mmc0_data1_1_mux[] = {
MMCD1_0_MARK,
};
static const unsigned int mmc0_data4_1_pins[] = {
/* D[0:3] */
305, 304, 303, 302,
};
static const unsigned int mmc0_data4_1_mux[] = {
MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
};
static const unsigned int mmc0_data8_1_pins[] = {
static const unsigned int mmc0_data_1_pins[] = {
/* D[0:7] */
305, 304, 303, 302, 301, 300, 299, 298,
};
static const unsigned int mmc0_data8_1_mux[] = {
static const unsigned int mmc0_data_1_mux[] = {
MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
};
@ -2851,18 +2695,11 @@ static const unsigned int scifb_ctrl_1_mux[] = {
PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
252,
};
static const unsigned int sdhi0_data1_mux[] = {
SDHID0_0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
252, 253, 254, 255,
};
static const unsigned int sdhi0_data4_mux[] = {
static const unsigned int sdhi0_data_mux[] = {
SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
@ -2887,18 +2724,11 @@ static const unsigned int sdhi0_wp_mux[] = {
SDHIWP0_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
259,
};
static const unsigned int sdhi1_data1_mux[] = {
SDHID1_0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
259, 260, 261, 262,
};
static const unsigned int sdhi1_data4_mux[] = {
static const unsigned int sdhi1_data_mux[] = {
SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
@ -2909,18 +2739,11 @@ static const unsigned int sdhi1_ctrl_mux[] = {
SDHICMD1_MARK, SDHICLK1_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
265,
};
static const unsigned int sdhi2_data1_mux[] = {
SDHID2_0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
static const unsigned int sdhi2_data_pins[] = {
/* D[0:3] */
265, 266, 267, 268,
};
static const unsigned int sdhi2_data4_mux[] = {
static const unsigned int sdhi2_data_mux[] = {
SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
@ -3138,10 +2961,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c3_2),
SH_PFC_PIN_GROUP(irda_0),
SH_PFC_PIN_GROUP(irda_1),
SH_PFC_PIN_GROUP(keysc_in5),
SH_PFC_PIN_GROUP(keysc_in6),
SH_PFC_PIN_GROUP(keysc_in7),
SH_PFC_PIN_GROUP(keysc_in8),
BUS_DATA_PIN_GROUP(keysc_in, 5),
BUS_DATA_PIN_GROUP(keysc_in, 6),
BUS_DATA_PIN_GROUP(keysc_in, 7),
BUS_DATA_PIN_GROUP(keysc_in, 8),
SH_PFC_PIN_GROUP(keysc_out04),
SH_PFC_PIN_GROUP(keysc_out5),
SH_PFC_PIN_GROUP(keysc_out6_0),
@ -3160,33 +2983,33 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(keysc_out10_1),
SH_PFC_PIN_GROUP(keysc_out11_0),
SH_PFC_PIN_GROUP(keysc_out11_1),
SH_PFC_PIN_GROUP(lcd_data8),
SH_PFC_PIN_GROUP(lcd_data9),
SH_PFC_PIN_GROUP(lcd_data12),
SH_PFC_PIN_GROUP(lcd_data16),
SH_PFC_PIN_GROUP(lcd_data18),
SH_PFC_PIN_GROUP(lcd_data24),
BUS_DATA_PIN_GROUP(lcd_data, 8),
BUS_DATA_PIN_GROUP(lcd_data, 9),
BUS_DATA_PIN_GROUP(lcd_data, 12),
BUS_DATA_PIN_GROUP(lcd_data, 16),
BUS_DATA_PIN_GROUP(lcd_data, 18),
BUS_DATA_PIN_GROUP(lcd_data, 24),
SH_PFC_PIN_GROUP(lcd_display),
SH_PFC_PIN_GROUP(lcd_lclk),
SH_PFC_PIN_GROUP(lcd_sync),
SH_PFC_PIN_GROUP(lcd_sys),
SH_PFC_PIN_GROUP(lcd2_data8),
SH_PFC_PIN_GROUP(lcd2_data9),
SH_PFC_PIN_GROUP(lcd2_data12),
SH_PFC_PIN_GROUP(lcd2_data16),
SH_PFC_PIN_GROUP(lcd2_data18),
SH_PFC_PIN_GROUP(lcd2_data24),
BUS_DATA_PIN_GROUP(lcd2_data, 8),
BUS_DATA_PIN_GROUP(lcd2_data, 9),
BUS_DATA_PIN_GROUP(lcd2_data, 12),
BUS_DATA_PIN_GROUP(lcd2_data, 16),
BUS_DATA_PIN_GROUP(lcd2_data, 18),
BUS_DATA_PIN_GROUP(lcd2_data, 24),
SH_PFC_PIN_GROUP(lcd2_sync_0),
SH_PFC_PIN_GROUP(lcd2_sync_1),
SH_PFC_PIN_GROUP(lcd2_sys_0),
SH_PFC_PIN_GROUP(lcd2_sys_1),
SH_PFC_PIN_GROUP(mmc0_data1_0),
SH_PFC_PIN_GROUP(mmc0_data4_0),
SH_PFC_PIN_GROUP(mmc0_data8_0),
BUS_DATA_PIN_GROUP(mmc0_data, 1, _0),
BUS_DATA_PIN_GROUP(mmc0_data, 4, _0),
BUS_DATA_PIN_GROUP(mmc0_data, 8, _0),
SH_PFC_PIN_GROUP(mmc0_ctrl_0),
SH_PFC_PIN_GROUP(mmc0_data1_1),
SH_PFC_PIN_GROUP(mmc0_data4_1),
SH_PFC_PIN_GROUP(mmc0_data8_1),
BUS_DATA_PIN_GROUP(mmc0_data, 1, _1),
BUS_DATA_PIN_GROUP(mmc0_data, 4, _1),
BUS_DATA_PIN_GROUP(mmc0_data, 8, _1),
SH_PFC_PIN_GROUP(mmc0_ctrl_1),
SH_PFC_PIN_GROUP(msiof0_rsck),
SH_PFC_PIN_GROUP(msiof0_tsck),
@ -3280,16 +3103,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scifb_data_1),
SH_PFC_PIN_GROUP(scifb_clk_1),
SH_PFC_PIN_GROUP(scifb_ctrl_1),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(tpu0_to0),
SH_PFC_PIN_GROUP(tpu0_to1),
@ -4314,9 +4137,9 @@ static const unsigned int sh73a0_portcr_offsets[] = {
0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
};
static void __iomem *sh73a0_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
static int sh73a0_pin_to_portcr(unsigned int pin)
{
return pfc->windows->virt + sh73a0_portcr_offsets[pin >> 5] + pin;
return sh73a0_portcr_offsets[pin >> 5] + pin;
}
/* -----------------------------------------------------------------------------

1
drivers/pinctrl/renesas/pfc-sh7720.c
View File

@ -6,7 +6,6 @@
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <cpu/sh7720.h>
#include "sh_pfc.h"

1
drivers/pinctrl/renesas/pfc-sh7722.c
View File

@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <cpu/sh7722.h>
#include "sh_pfc.h"

24
drivers/pinctrl/renesas/pinctrl.c
View File

@ -639,7 +639,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
return -ENOTSUPP;
bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl);
if (WARN(bit < 0, "invalid pin %#x", _pin))
return bit;
@ -711,7 +711,7 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
return -ENOTSUPP;
bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl);
if (WARN(bit < 0, "invalid pin %#x", _pin))
return bit;
@ -835,16 +835,16 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
}
const struct pinmux_bias_reg *
rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin,
unsigned int *bit)
{
unsigned int i, j;
for (i = 0; pfc->info->bias_regs[i].puen || pfc->info->bias_regs[i].pud; i++) {
for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
if (pfc->info->bias_regs[i].pins[j] == pin) {
for (i = 0; info->bias_regs[i].puen || info->bias_regs[i].pud; i++) {
for (j = 0; j < ARRAY_SIZE(info->bias_regs[i].pins); j++) {
if (info->bias_regs[i].pins[j] == pin) {
*bit = j;
return &pfc->info->bias_regs[i];
return &info->bias_regs[i];
}
}
}
@ -859,7 +859,7 @@ unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
const struct pinmux_bias_reg *reg;
unsigned int bit;
reg = rcar_pin_to_bias_reg(pfc, pin, &bit);
reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
if (!reg)
return PIN_CONFIG_BIAS_DISABLE;
@ -885,7 +885,7 @@ void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
u32 enable, updown;
unsigned int bit;
reg = rcar_pin_to_bias_reg(pfc, pin, &bit);
reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
if (!reg)
return;
@ -919,7 +919,8 @@ void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
{
void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin);
void __iomem *reg = pfc->windows->virt +
pfc->info->ops->pin_to_portcr(pin);
u32 value = ioread8(reg) & PORTnCR_PULMD_MASK;
switch (value) {
@ -936,7 +937,8 @@ unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias)
{
void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin);
void __iomem *reg = pfc->windows->virt +
pfc->info->ops->pin_to_portcr(pin);
u32 value = ioread8(reg) & ~PORTnCR_PULMD_MASK;
switch (bias) {

176
drivers/pinctrl/renesas/sh_pfc.h
View File

@ -49,15 +49,34 @@ struct sh_pfc_pin {
u16 enum_id;
};
#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
{ \
.name = #alias, \
.pins = n##_pins, \
.mux = n##_mux, \
.nr_pins = ARRAY_SIZE(n##_pins) + \
BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
}
#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
#define SH_PFC_PIN_GROUP_ALIAS(alias, _name) { \
.name = #alias, \
.pins = _name##_pins, \
.mux = _name##_mux, \
.nr_pins = ARRAY_SIZE(_name##_pins) + \
BUILD_BUG_ON_ZERO(sizeof(_name##_pins) != sizeof(_name##_mux)), \
}
#define SH_PFC_PIN_GROUP(name) SH_PFC_PIN_GROUP_ALIAS(name, name)
/*
* Define a pin group referring to a subset of an array of pins.
*/
#define SH_PFC_PIN_GROUP_SUBSET(_name, data, first, n) { \
.name = #_name, \
.pins = data##_pins + first, \
.mux = data##_mux + first, \
.nr_pins = n + \
BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_pins)) + \
BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_mux)), \
}
/*
* Define a pin group for the data pins of a resizable bus.
* An optional 'suffix' argument is accepted, to be used when the same group
* can appear on a different set of pins.
*/
#define BUS_DATA_PIN_GROUP(base, n, ...) \
SH_PFC_PIN_GROUP_SUBSET(base##n##__VA_ARGS__, base##__VA_ARGS__, 0, n)
struct sh_pfc_pin_group {
const char *name;
@ -66,49 +85,11 @@ struct sh_pfc_pin_group {
unsigned int nr_pins;
};
/*
* Using union vin_data{,12,16} saves memory occupied by the VIN data pins.
* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
* in this case. It accepts an optional 'version' argument used when the
* same group can appear on a different set of pins.
*/
#define VIN_DATA_PIN_GROUP(n, s, ...) \
{ \
.name = #n#s#__VA_ARGS__, \
.pins = n##__VA_ARGS__##_pins.data##s, \
.mux = n##__VA_ARGS__##_mux.data##s, \
.nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
}
union vin_data12 {
unsigned int data12[12];
unsigned int data10[10];
unsigned int data8[8];
};
union vin_data16 {
unsigned int data16[16];
unsigned int data12[12];
unsigned int data10[10];
unsigned int data8[8];
};
union vin_data {
unsigned int data24[24];
unsigned int data20[20];
unsigned int data16[16];
unsigned int data12[12];
unsigned int data10[10];
unsigned int data8[8];
unsigned int data4[4];
};
#define SH_PFC_FUNCTION(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.nr_groups = ARRAY_SIZE(n##_groups), \
}
#define SH_PFC_FUNCTION(n) { \
.name = #n, \
.groups = n##_groups, \
.nr_groups = ARRAY_SIZE(n##_groups), \
}
struct sh_pfc_function {
const char *name;
@ -231,8 +212,9 @@ struct pinmux_irq {
* Describe the mapping from GPIOs to a single IRQ
* - ids...: List of GPIOs that are mapped to the same IRQ
*/
#define PINMUX_IRQ(ids...) \
{ .gpios = (const short []) { ids, -1 } }
#define PINMUX_IRQ(ids...) { \
.gpios = (const short []) { ids, -1 } \
}
struct pinmux_range {
u16 begin;
@ -272,8 +254,8 @@ struct sh_pfc_soc_operations {
unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias);
int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
void __iomem * (*pin_to_portcr)(struct sh_pfc *pfc, unsigned int pin);
int (*pin_to_pocctrl)(unsigned int pin, u32 *pocctrl);
int (*pin_to_portcr)(unsigned int pin);
};
struct sh_pfc_soc_info {
@ -342,6 +324,7 @@ extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
extern const struct sh_pfc_soc_info r8a779f0_pinmux_info;
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
extern const struct sh_pfc_soc_info sh7269_pinmux_info;
@ -535,9 +518,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
#define PORT_GP_CFG_19(bank, fn, sfx, cfg) \
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg)
#define PORT_GP_19(bank, fn, sfx) PORT_GP_CFG_19(bank, fn, sfx, 0)
#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
PORT_GP_CFG_19(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
@ -624,13 +611,12 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
#define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str)
/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
{ \
.pin = (bank * 32) + _pin, \
.name = __stringify(_name), \
.enum_id = _name##_DATA, \
.configs = cfg, \
}
#define _GP_GPIO(bank, _pin, _name, sfx, cfg) { \
.pin = (bank * 32) + _pin, \
.name = __stringify(_name), \
.enum_id = _name##_DATA, \
.configs = cfg, \
}
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
@ -688,13 +674,12 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
}
/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
#define SH_PFC_PIN_CFG(_pin, cfgs) \
{ \
.pin = _pin, \
.name = __stringify(PORT##_pin), \
.enum_id = PORT##_pin##_DATA, \
.configs = cfgs, \
}
#define SH_PFC_PIN_CFG(_pin, cfgs) { \
.pin = _pin, \
.name = __stringify(PORT##_pin), \
.enum_id = PORT##_pin##_DATA, \
.configs = cfgs, \
}
/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
* PORT_name_OUT, PORT_name_IN marks
@ -743,35 +728,32 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
#define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL)
/* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */
#define _NOGP_PINMUX(_pin, _name, cfg) \
{ \
.pin = PIN_##_pin, \
.name = "PIN_" _name, \
.configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \
}
#define _NOGP_PINMUX(_pin, _name, cfg) { \
.pin = PIN_##_pin, \
.name = "PIN_" _name, \
.configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \
}
#define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX)
/*
* PORTnCR helper macro for SH-Mobile/R-Mobile
*/
#define PORTCR(nr, reg) \
{ \
PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
GROUP(2, 2, 1, 3), \
GROUP( \
/* PULMD[1:0], handled by .set_bias() */ \
0, 0, 0, 0, \
/* IE and OE */ \
0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
/* SEC, not supported */ \
0, 0, \
/* PTMD[2:0] */ \
PORT##nr##_FN0, PORT##nr##_FN1, \
PORT##nr##_FN2, PORT##nr##_FN3, \
PORT##nr##_FN4, PORT##nr##_FN5, \
PORT##nr##_FN6, PORT##nr##_FN7 \
)) \
}
#define PORTCR(nr, reg) { \
PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, GROUP(2, 2, 1, 3), \
GROUP( \
/* PULMD[1:0], handled by .set_bias() */ \
0, 0, 0, 0, \
/* IE and OE */ \
0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
/* SEC, not supported */ \
0, 0, \
/* PTMD[2:0] */ \
PORT##nr##_FN0, PORT##nr##_FN1, \
PORT##nr##_FN2, PORT##nr##_FN3, \
PORT##nr##_FN4, PORT##nr##_FN5, \
PORT##nr##_FN6, PORT##nr##_FN7 \
)) \
}
/*
* GPIO number helper macro for R-Car
@ -782,7 +764,7 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
* Bias helpers
*/
const struct pinmux_bias_reg *
rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin,
unsigned int *bit);
unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,