drm/amdgpu/virt: add high level interfaces for virt
Add high level interfaces that is not relate to specific asic. So asic files just need to implement the interfaces to support virtualization. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -149,3 +149,70 @@ void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
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DRM_ERROR("wait for kiq fence error: %ld.\n", r);
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dma_fence_put(f);
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}
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/**
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* amdgpu_virt_request_full_gpu() - request full gpu access
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* @amdgpu: amdgpu device.
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* @init: is driver init time.
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* When start to init/fini driver, first need to request full gpu access.
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* Return: Zero if request success, otherwise will return error.
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*/
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int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->req_full_gpu) {
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r = virt->ops->req_full_gpu(adev, init);
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if (r)
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return r;
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adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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/**
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* amdgpu_virt_release_full_gpu() - release full gpu access
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* @amdgpu: amdgpu device.
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* @init: is driver init time.
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* When finishing driver init/fini, need to release full gpu access.
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* Return: Zero if release success, otherwise will returen error.
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*/
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int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->rel_full_gpu) {
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r = virt->ops->rel_full_gpu(adev, init);
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if (r)
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return r;
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adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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/**
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* amdgpu_virt_reset_gpu() - reset gpu
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* @amdgpu: amdgpu device.
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* Send reset command to GPU hypervisor to reset GPU that VM is using
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* Return: Zero if reset success, otherwise will return error.
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*/
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int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->reset_gpu) {
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r = virt->ops->reset_gpu(adev);
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if (r)
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return r;
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adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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@ -30,6 +30,15 @@
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#define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
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#define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
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/**
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* struct amdgpu_virt_ops - amdgpu device virt operations
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*/
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struct amdgpu_virt_ops {
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int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
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int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
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int (*reset_gpu)(struct amdgpu_device *adev);
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};
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/* GPU virtualization */
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struct amdgpu_virt {
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uint32_t caps;
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@ -37,6 +46,7 @@ struct amdgpu_virt {
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uint64_t csa_vmid0_addr;
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uint32_t reg_val_offs;
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struct mutex lock;
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const struct amdgpu_virt_ops *ops;
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};
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#define AMDGPU_CSA_SIZE (8 * 1024)
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@ -72,5 +82,8 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm);
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void amdgpu_virt_init_setting(struct amdgpu_device *adev);
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uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
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void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
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int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
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int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
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int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
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#endif
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