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drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD 

The WA applies to all production Gen9 and requires both enabling and
whitelisting of the per-context preemption control register.

v2: Extend to Cannonlake.

Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171003203453.15692-1-chris@chris-wilson.co.uk
This commit is contained in:
Jeff McGee 2017-10-03 21:34:45 +01:00 committed by Chris Wilson
parent 3af7a9c644
commit 1e998343f9
1 changed files with 6 additions and 10 deletions
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16
drivers/gpu/drm/i915/intel_engine_cs.c
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@ -1075,8 +1075,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
if (ret) if (ret)
return ret; return ret;
/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl */ /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
if (ret) if (ret)
return ret; return ret;
@ -1138,14 +1140,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
if (ret) if (ret)
return ret; return ret;
/*
* Actual WA is to disable percontext preemption granularity control
* until D0 which is the default case so this is equivalent to
* !WaDisablePerCtxtPreemptionGranularityControl:skl
*/
I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
/* WaEnableGapsTsvCreditFix:skl */ /* WaEnableGapsTsvCreditFix:skl */
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
GEN9_GAPS_TSV_CREDIT_DISABLE)); GEN9_GAPS_TSV_CREDIT_DISABLE));
@ -1278,6 +1272,8 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
/* WaEnablePreemptionGranularityControlByUMD:cnl */ /* WaEnablePreemptionGranularityControlByUMD:cnl */
I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
if (ret) if (ret)
return ret; return ret;