arm64: dts: Amlogic updates for v5.2, round 2
- add display/gfx support for G12a boards - enable USB for g12a boards -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAly8ghgACgkQWTcYmtP7 xmXqyg/9HtVrO5aNLEmGi3l/YySSH7fSp5BNnvTzlT8SpB1vBAKLXWjemVss2XVE QEE7d1UyUoXwgE4GoAyguuuj0Ov+JwYRTQb+OZKliALPlHfQQkklN8FKVMnDzEz7 u1ivVqmoXzwqW32NW3a24AyGLgQXgJi2+ctAZSGNd+pLydwANLCB+Ffc1I4fTmW0 kwLnqBgyVMxhbgRw6Blj9nh+ZlQOLwktpiMfrOwIpV0WLT3LZdRMrY1M/SnP+4+B Pq2BEzBAaHC5cNjQ3TjEj+nckXnrncJ0V6DepT+UIOC8L61rsb/tQAx8ecVVoHcW TTsQ3fewNcqIrKLRFpyNpXEAEAzlciwpV8lDczY5fLv5/j0MHiRSwBctj1pcK+CF Rsl2NygGZv0SuU0hDsDfEzVGLPjD1VYVGSJezWaaNzhjLw4sDUylBsKOcMNui4fW IUT3ahdjtvp03xjlGWAd1NI/MkYuu3RxJ2wR28vPEUGu2JEVpI8PtkR1FVqRIwBU Qd20x3bAn76zxMSWrsmDiTAa0+HMqjUbhzyeJxKPV5ON5k7RbmADrQ2rvxx+E4Uj FR3S6iulwaXDxIrvKZvTJDX3Myf2EL0bck5/XlKrD/B8tN5dCBgySA+SGHLhIiwZ XpCQmP6nLzZayeU4TX7jvAQdbhmR5GYCpO7SsIFTz7fJr6Vb8lM= =T6Im -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.2, round 2 - add display/gfx support for G12a boards - enable USB for g12a boards * tag 'amlogic-dt64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (26 commits) arm64: dts: meson-g12a-u200: Add support for Video Display arm64: dts: meson-g12a-sei510: Add support for Video Display arm64: dts: meson-g12a-x96-max: Add support for Video Display arm64: dts: meson-g12a: Add AO-CEC nodes arm64: dts: meson-g12a: Add VPU and HDMI related nodes arm64: dts: meson-g12a-x96-max: Enable USB arm64: dts: meson-g12a-u200: Enable USB arm64: dts: meson-g12a-sei510: Enable USB arm64: dts: meson-g12a-sei510: Add ADC Key and BT support arm64: dts: meson-g12a-u200: add regulators arm64: dts: meson: g12a: Add mali-g31 gpu node arm64: dts: meson: g12a: Add G12A USB nodes arm64: dts: meson: g12a: Add SAR ADC node dt-bindings: power: amlogic, meson-gx-pwrc: Add G12A compatible arm64: dts: meson-gxm: Add Mali-T820 node dt-bindings: gpu: mali-midgard: Add resets property dt-bindings: clock: meson8b: export the video decoder clocks dt-bindings: clock: meson8b: export the VPU clock dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN dt-bindings: clock: meson8b: drop the "ABP" clock definition ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
1e67323721
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@ -37,6 +37,20 @@ Optional properties:
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- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
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for details.
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- resets : Phandle of the GPU reset line.
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Vendor-specific bindings
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------------------------
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The Mali GPU is integrated very differently from one SoC to
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another. In order to accomodate those differences, you have the option
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to specify one more vendor-specific compatible, among:
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- "amlogic,meson-gxm-mali"
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Required properties:
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- resets : Should contain phandles of :
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+ GPU reset line
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+ GPU APB glue reset line
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Example for a Mali-T760:
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@ -16,7 +16,9 @@ Device Tree Bindings:
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---------------------
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Required properties:
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- compatible: should be "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
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- compatible: should be one of the following :
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- "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
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- "amlogic,meson-g12a-pwrc-vpu" for the Meson G12A SoCs
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- #power-domain-cells: should be 0
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- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
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- resets: phandles to the reset lines needed for this power demain sequence
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@ -7,6 +7,7 @@
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#include "meson-g12a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/meson-g12a-gpio.h>
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/ {
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@ -17,6 +18,19 @@
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serial0 = &uart_AO;
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};
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adc_keys {
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compatible = "adc-keys";
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io-channels = <&saradc 0>;
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io-channel-names = "buttons";
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keyup-threshold-microvolt = <1800000>;
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button-onoff {
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label = "On/Off";
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linux,code = <KEY_POWER>;
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press-threshold-microvolt = <1700000>;
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};
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};
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ao_5v: regulator-ao_5v {
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compatible = "regulator-fixed";
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regulator-name = "AO_5V";
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@ -30,6 +44,16 @@
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stdout-path = "serial0:115200n8";
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};
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cvbs-connector {
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compatible = "composite-video-connector";
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port {
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cvbs_connector_in: endpoint {
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remote-endpoint = <&cvbs_vdac_out>;
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};
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};
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};
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dc_in: regulator-dc_in {
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compatible = "regulator-fixed";
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regulator-name = "DC_IN";
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@ -47,6 +71,17 @@
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regulator-always-on;
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};
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hdmi-connector {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&hdmi_tx_tmds_out>;
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};
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};
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x40000000>;
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@ -87,7 +122,55 @@
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vin-supply = <&vddao_3v3>;
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regulator-always-on;
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};
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};
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&cec_AO {
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pinctrl-0 = <&cec_ao_a_h_pins>;
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pinctrl-names = "default";
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status = "disabled";
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hdmi-phandle = <&hdmi_tx>;
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};
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&cecb_AO {
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pinctrl-0 = <&cec_ao_b_h_pins>;
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pinctrl-names = "default";
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status = "okay";
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hdmi-phandle = <&hdmi_tx>;
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};
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&cvbs_vdac_port {
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cvbs_vdac_out: endpoint {
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remote-endpoint = <&cvbs_connector_in>;
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};
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};
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&saradc {
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status = "okay";
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vref-supply = <&vddio_ao1v8>;
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};
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&uart_A {
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status = "okay";
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pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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bluetooth {
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compatible = "brcm,bcm43438-bt";
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shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
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};
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};
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&hdmi_tx {
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status = "okay";
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pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
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pinctrl-names = "default";
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};
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&hdmi_tx_tmds_port {
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hdmi_tx_tmds_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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&uart_AO {
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@ -95,3 +178,8 @@
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pinctrl-0 = <&uart_ao_a_pins>;
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pinctrl-names = "default";
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};
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&usb {
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status = "okay";
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dr_mode = "host";
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};
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@ -6,6 +6,8 @@
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/dts-v1/;
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#include "meson-g12a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/gpio/meson-g12a-gpio.h>
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/ {
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compatible = "amlogic,u200", "amlogic,g12a";
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@ -21,6 +23,137 @@
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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cvbs-connector {
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compatible = "composite-video-connector";
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port {
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cvbs_connector_in: endpoint {
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remote-endpoint = <&cvbs_vdac_out>;
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};
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};
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};
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flash_1v8: regulator-flash_1v8 {
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compatible = "regulator-fixed";
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regulator-name = "FLASH_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vcc_3v3>;
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regulator-always-on;
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};
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hdmi-connector {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&hdmi_tx_tmds_out>;
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};
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};
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};
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main_12v: regulator-main_12v {
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compatible = "regulator-fixed";
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regulator-name = "12V";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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regulator-always-on;
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};
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vcc_1v8: regulator-vcc_1v8 {
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compatible = "regulator-fixed";
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regulator-name = "VCC_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vcc_3v3>;
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regulator-always-on;
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};
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vcc_3v3: regulator-vcc_3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VCC_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vddao_3v3>;
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regulator-always-on;
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/* FIXME: actually controlled by VDDCPU_B_EN */
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};
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vcc_5v: regulator-vcc_5v {
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compatible = "regulator-fixed";
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regulator-name = "VCC_5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&main_12v>;
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gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
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enable-active-high;
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};
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usb_pwr_en: regulator-usb_pwr_en {
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compatible = "regulator-fixed";
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regulator-name = "USB_PWR_EN";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc_5v>;
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gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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vddao_1v8: regulator-vddao_1v8 {
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compatible = "regulator-fixed";
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regulator-name = "VDDAO_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vddao_3v3>;
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regulator-always-on;
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};
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vddao_3v3: regulator-vddao_3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VDDAO_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&main_12v>;
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regulator-always-on;
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};
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};
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&cec_AO {
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pinctrl-0 = <&cec_ao_a_h_pins>;
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pinctrl-names = "default";
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status = "disabled";
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hdmi-phandle = <&hdmi_tx>;
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};
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&cecb_AO {
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pinctrl-0 = <&cec_ao_b_h_pins>;
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pinctrl-names = "default";
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status = "okay";
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hdmi-phandle = <&hdmi_tx>;
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};
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&cvbs_vdac_port {
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cvbs_vdac_out: endpoint {
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remote-endpoint = <&cvbs_connector_in>;
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};
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};
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&hdmi_tx {
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status = "okay";
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pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
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pinctrl-names = "default";
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hdmi-supply = <&vcc_5v>;
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};
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&hdmi_tx_tmds_port {
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hdmi_tx_tmds_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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&uart_AO {
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@ -29,3 +162,15 @@
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pinctrl-names = "default";
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};
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&usb {
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status = "okay";
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vbus-supply = <&usb_pwr_en>;
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};
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&usb2_phy0 {
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phy-supply = <&vcc_5v>;
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};
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&usb2_phy1 {
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phy-supply = <&vcc_5v>;
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};
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|
|
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@ -24,6 +24,27 @@
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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cvbs-connector {
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compatible = "composite-video-connector";
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port {
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cvbs_connector_in: endpoint {
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remote-endpoint = <&cvbs_vdac_out>;
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};
|
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};
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
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type = "a";
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|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&hdmi_tx_tmds_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
flash_1v8: regulator-flash_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "FLASH_1V8";
|
||||
|
|
@ -90,6 +111,39 @@
|
|||
};
|
||||
};
|
||||
|
||||
&cec_AO {
|
||||
pinctrl-0 = <&cec_ao_a_h_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&cecb_AO {
|
||||
pinctrl-0 = <&cec_ao_b_h_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&cvbs_vdac_port {
|
||||
cvbs_vdac_out: endpoint {
|
||||
remote-endpoint = <&cvbs_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
|
||||
pinctrl-names = "default";
|
||||
hdmi-supply = <&vcc_5v>;
|
||||
};
|
||||
|
||||
&hdmi_tx_tmds_port {
|
||||
hdmi_tx_tmds_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart_A {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
|
||||
|
|
@ -107,3 +161,8 @@
|
|||
pinctrl-0 = <&uart_ao_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -3,10 +3,13 @@
|
|||
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clock/g12a-clkc.h>
|
||||
#include <dt-bindings/clock/g12a-aoclkc.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
|
||||
|
||||
/ {
|
||||
compatible = "amlogic,g12a";
|
||||
|
|
@ -106,6 +109,37 @@
|
|||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
|
||||
|
||||
hdmi_tx: hdmi-tx@0 {
|
||||
compatible = "amlogic,meson-g12a-dw-hdmi";
|
||||
reg = <0x0 0x0 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
|
||||
resets = <&reset RESET_HDMITX_CAPB3>,
|
||||
<&reset RESET_HDMITX_PHY>,
|
||||
<&reset RESET_HDMITX>;
|
||||
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
|
||||
clocks = <&clkc CLKID_HDMI>,
|
||||
<&clkc CLKID_HTX_PCLK>,
|
||||
<&clkc CLKID_VPU_INTR>;
|
||||
clock-names = "isfr", "iahb", "venci";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
/* VPU VENC Input */
|
||||
hdmi_tx_venc_port: port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi_tx_in: endpoint {
|
||||
remote-endpoint = <&hdmi_tx_out>;
|
||||
};
|
||||
};
|
||||
|
||||
/* TMDS Output */
|
||||
hdmi_tx_tmds_port: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
periphs: bus@34400 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0x34400 0x0 0x400>;
|
||||
|
|
@ -135,6 +169,39 @@
|
|||
gpio-ranges = <&periphs_pinctrl 0 0 86>;
|
||||
};
|
||||
|
||||
cec_ao_a_h_pins: cec_ao_a_h {
|
||||
mux {
|
||||
groups = "cec_ao_a_h";
|
||||
function = "cec_ao_a_h";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
cec_ao_b_h_pins: cec_ao_b_h {
|
||||
mux {
|
||||
groups = "cec_ao_b_h";
|
||||
function = "cec_ao_b_h";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
hdmitx_ddc_pins: hdmitx_ddc {
|
||||
mux {
|
||||
groups = "hdmitx_sda",
|
||||
"hdmitx_sck";
|
||||
function = "hdmitx";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
hdmitx_hpd_pins: hdmitx_hpd {
|
||||
mux {
|
||||
groups = "hdmitx_hpd_in";
|
||||
function = "hdmitx";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart_a_pins: uart-a {
|
||||
mux {
|
||||
groups = "uart_a_tx",
|
||||
|
|
@ -182,6 +249,39 @@
|
|||
};
|
||||
};
|
||||
|
||||
usb2_phy0: phy@36000 {
|
||||
compatible = "amlogic,g12a-usb2-phy";
|
||||
reg = <0x0 0x36000 0x0 0x2000>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "xtal";
|
||||
resets = <&reset RESET_USB_PHY20>;
|
||||
reset-names = "phy";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
dmc: bus@38000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0x38000 0x0 0x400>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
|
||||
|
||||
canvas: video-lut@48 {
|
||||
compatible = "amlogic,canvas";
|
||||
reg = <0x0 0x48 0x0 0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
usb2_phy1: phy@3a000 {
|
||||
compatible = "amlogic,g12a-usb2-phy";
|
||||
reg = <0x0 0x3a000 0x0 0x2000>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "xtal";
|
||||
resets = <&reset RESET_USB_PHY21>;
|
||||
reset-names = "phy";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
hiu: bus@3c000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0x3c000 0x0 0x1400>;
|
||||
|
|
@ -202,6 +302,18 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb3_pcie_phy: phy@46000 {
|
||||
compatible = "amlogic,g12a-usb3-pcie-phy";
|
||||
reg = <0x0 0x46000 0x0 0x2000>;
|
||||
clocks = <&clkc CLKID_PCIE_PLL>;
|
||||
clock-names = "ref_clk";
|
||||
resets = <&reset RESET_PCIE_PHY>;
|
||||
reset-names = "phy";
|
||||
assigned-clocks = <&clkc CLKID_PCIE_PLL>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aobus: bus@ff800000 {
|
||||
|
|
@ -227,6 +339,50 @@
|
|||
clock-names = "xtal", "mpeg-clk";
|
||||
};
|
||||
|
||||
pwrc_vpu: power-controller-vpu {
|
||||
compatible = "amlogic,meson-g12a-pwrc-vpu";
|
||||
#power-domain-cells = <0>;
|
||||
amlogic,hhi-sysctrl = <&hhi>;
|
||||
resets = <&reset RESET_VIU>,
|
||||
<&reset RESET_VENC>,
|
||||
<&reset RESET_VCBUS>,
|
||||
<&reset RESET_BT656>,
|
||||
<&reset RESET_RDMA>,
|
||||
<&reset RESET_VENCI>,
|
||||
<&reset RESET_VENCP>,
|
||||
<&reset RESET_VDAC>,
|
||||
<&reset RESET_VDI6>,
|
||||
<&reset RESET_VENCL>,
|
||||
<&reset RESET_VID_LOCK>;
|
||||
clocks = <&clkc CLKID_VPU>,
|
||||
<&clkc CLKID_VAPB>;
|
||||
clock-names = "vpu", "vapb";
|
||||
/*
|
||||
* VPU clocking is provided by two identical clock paths
|
||||
* VPU_0 and VPU_1 muxed to a single clock by a glitch
|
||||
* free mux to safely change frequency while running.
|
||||
* Same for VAPB but with a final gate after the glitch free mux.
|
||||
*/
|
||||
assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
|
||||
<&clkc CLKID_VPU_0>,
|
||||
<&clkc CLKID_VPU>, /* Glitch free mux */
|
||||
<&clkc CLKID_VAPB_0_SEL>,
|
||||
<&clkc CLKID_VAPB_0>,
|
||||
<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
|
||||
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
|
||||
<0>, /* Do Nothing */
|
||||
<&clkc CLKID_VPU_0>,
|
||||
<&clkc CLKID_FCLK_DIV4>,
|
||||
<0>, /* Do Nothing */
|
||||
<&clkc CLKID_VAPB_0>;
|
||||
assigned-clock-rates = <0>, /* Do Nothing */
|
||||
<666666666>,
|
||||
<0>, /* Do Nothing */
|
||||
<0>, /* Do Nothing */
|
||||
<250000000>,
|
||||
<0>; /* Do Nothing */
|
||||
};
|
||||
|
||||
ao_pinctrl: pinctrl@14 {
|
||||
compatible = "amlogic,meson-g12a-aobus-pinctrl";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -265,12 +421,30 @@
|
|||
};
|
||||
};
|
||||
|
||||
cec_AO: cec@100 {
|
||||
compatible = "amlogic,meson-gx-ao-cec";
|
||||
reg = <0x0 0x00100 0x0 0x14>;
|
||||
interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clkc_AO CLKID_AO_CEC>;
|
||||
clock-names = "core";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sec_AO: ao-secure@140 {
|
||||
compatible = "amlogic,meson-gx-ao-secure", "syscon";
|
||||
reg = <0x0 0x140 0x0 0x140>;
|
||||
amlogic,has-chip-id;
|
||||
};
|
||||
|
||||
cecb_AO: cec@280 {
|
||||
compatible = "amlogic,meson-g12a-ao-cec";
|
||||
reg = <0x0 0x00280 0x0 0x1c>;
|
||||
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
|
||||
clock-names = "oscin";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart_AO: serial@3000 {
|
||||
compatible = "amlogic,meson-gx-uart",
|
||||
"amlogic,meson-ao-uart";
|
||||
|
|
@ -290,6 +464,46 @@
|
|||
clock-names = "xtal", "pclk", "baud";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
saradc: adc@9000 {
|
||||
compatible = "amlogic,meson-g12a-saradc",
|
||||
"amlogic,meson-saradc";
|
||||
reg = <0x0 0x9000 0x0 0x48>;
|
||||
#io-channel-cells = <1>;
|
||||
interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&xtal>,
|
||||
<&clkc_AO CLKID_AO_SAR_ADC>,
|
||||
<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
|
||||
<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
|
||||
clock-names = "clkin", "core", "adc_clk", "adc_sel";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
vpu: vpu@ff900000 {
|
||||
compatible = "amlogic,meson-g12a-vpu";
|
||||
reg = <0x0 0xff900000 0x0 0x100000>,
|
||||
<0x0 0xff63c000 0x0 0x1000>;
|
||||
reg-names = "vpu", "hhi";
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
amlogic,canvas = <&canvas>;
|
||||
power-domains = <&pwrc_vpu>;
|
||||
|
||||
/* CVBS VDAC output port */
|
||||
cvbs_vdac_port: port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
/* HDMI-TX output port */
|
||||
hdmi_tx_port: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hdmi_tx_out: endpoint {
|
||||
remote-endpoint = <&hdmi_tx_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@ffc01000 {
|
||||
|
|
@ -351,6 +565,74 @@
|
|||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usb: usb@ffe09000 {
|
||||
status = "disabled";
|
||||
compatible = "amlogic,meson-g12a-usb-ctrl";
|
||||
reg = <0x0 0xffe09000 0x0 0xa0>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
clocks = <&clkc CLKID_USB>;
|
||||
resets = <&reset RESET_USB>;
|
||||
|
||||
dr_mode = "otg";
|
||||
|
||||
phys = <&usb2_phy0>, <&usb2_phy1>,
|
||||
<&usb3_pcie_phy PHY_TYPE_USB3>;
|
||||
phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
|
||||
|
||||
dwc2: usb@ff400000 {
|
||||
compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
|
||||
reg = <0x0 0xff400000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
|
||||
clock-names = "ddr";
|
||||
phys = <&usb2_phy1>;
|
||||
dr_mode = "peripheral";
|
||||
g-rx-fifo-size = <192>;
|
||||
g-np-tx-fifo-size = <128>;
|
||||
g-tx-fifo-size = <128 128 16 16 16>;
|
||||
};
|
||||
|
||||
dwc3: usb@ff500000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0xff500000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,quirk-frame-length-adjustment;
|
||||
};
|
||||
};
|
||||
|
||||
mali: gpu@ffe40000 {
|
||||
compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
|
||||
reg = <0x0 0xffe40000 0x0 0x40000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "gpu", "mmu", "job";
|
||||
clocks = <&clkc CLKID_MALI>;
|
||||
resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
|
||||
|
||||
/*
|
||||
* Mali clocking is provided by two identical clock paths
|
||||
* MALI_0 and MALI_1 muxed to a single clock by a glitch
|
||||
* free mux to safely change frequency while running.
|
||||
*/
|
||||
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
|
||||
<&clkc CLKID_MALI_0>,
|
||||
<&clkc CLKID_MALI>; /* Glitch free mux */
|
||||
assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
|
||||
<0>, /* Do Nothing */
|
||||
<&clkc CLKID_MALI_0>;
|
||||
assigned-clock-rates = <0>, /* Do Nothing */
|
||||
<800000000>,
|
||||
<0>; /* Do Nothing */
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
|
|||
|
|
@ -91,6 +91,33 @@
|
|||
reset-names = "phy";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mali: gpu@c0000 {
|
||||
compatible = "amlogic,meson-gxm-mali", "arm,mali-t820";
|
||||
reg = <0x0 0xc0000 0x0 0x40000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "gpu", "mmu", "job";
|
||||
clocks = <&clkc CLKID_MALI>;
|
||||
resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;
|
||||
|
||||
/*
|
||||
* Mali clocking is provided by two identical clock paths
|
||||
* MALI_0 and MALI_1 muxed to a single clock by a glitch
|
||||
* free mux to safely change frequency while running.
|
||||
*/
|
||||
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
|
||||
<&clkc CLKID_MALI_0>,
|
||||
<&clkc CLKID_MALI>; /* Glitch free mux */
|
||||
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
|
||||
<0>, /* Do Nothing */
|
||||
<&clkc CLKID_MALI_0>;
|
||||
assigned-clock-rates = <0>, /* Do Nothing */
|
||||
<666666666>,
|
||||
<0>; /* Do Nothing */
|
||||
};
|
||||
};
|
||||
|
||||
&clkc_AO {
|
||||
|
|
|
|||
|
|
@ -60,6 +60,26 @@
|
|||
#define AUD_CLKID_MST5 6
|
||||
#define AUD_CLKID_MST6 7
|
||||
#define AUD_CLKID_MST7 8
|
||||
#define AUD_CLKID_SLV_SCLK0 9
|
||||
#define AUD_CLKID_SLV_SCLK1 10
|
||||
#define AUD_CLKID_SLV_SCLK2 11
|
||||
#define AUD_CLKID_SLV_SCLK3 12
|
||||
#define AUD_CLKID_SLV_SCLK4 13
|
||||
#define AUD_CLKID_SLV_SCLK5 14
|
||||
#define AUD_CLKID_SLV_SCLK6 15
|
||||
#define AUD_CLKID_SLV_SCLK7 16
|
||||
#define AUD_CLKID_SLV_SCLK8 17
|
||||
#define AUD_CLKID_SLV_SCLK9 18
|
||||
#define AUD_CLKID_SLV_LRCLK0 19
|
||||
#define AUD_CLKID_SLV_LRCLK1 20
|
||||
#define AUD_CLKID_SLV_LRCLK2 21
|
||||
#define AUD_CLKID_SLV_LRCLK3 22
|
||||
#define AUD_CLKID_SLV_LRCLK4 23
|
||||
#define AUD_CLKID_SLV_LRCLK5 24
|
||||
#define AUD_CLKID_SLV_LRCLK6 25
|
||||
#define AUD_CLKID_SLV_LRCLK7 26
|
||||
#define AUD_CLKID_SLV_LRCLK8 27
|
||||
#define AUD_CLKID_SLV_LRCLK9 28
|
||||
#define AUD_CLKID_MST_A_MCLK_SEL 59
|
||||
#define AUD_CLKID_MST_B_MCLK_SEL 60
|
||||
#define AUD_CLKID_MST_C_MCLK_SEL 61
|
||||
|
|
|
|||
|
|
@ -16,9 +16,7 @@
|
|||
* to expose, such as the internal muxes and dividers of composite clocks,
|
||||
* will remain defined here.
|
||||
*/
|
||||
#define CLKID_AO_SAR_ADC_SEL 16
|
||||
#define CLKID_AO_SAR_ADC_DIV 17
|
||||
#define CLKID_AO_CTS_OSCIN 19
|
||||
#define CLKID_AO_32K_PRE 20
|
||||
#define CLKID_AO_32K_DIV 21
|
||||
#define CLKID_AO_32K_SEL 22
|
||||
|
|
|
|||
|
|
@ -7,26 +7,6 @@
|
|||
#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
|
||||
#define __AXG_AUDIO_CLKC_BINDINGS_H
|
||||
|
||||
#define AUD_CLKID_SLV_SCLK0 9
|
||||
#define AUD_CLKID_SLV_SCLK1 10
|
||||
#define AUD_CLKID_SLV_SCLK2 11
|
||||
#define AUD_CLKID_SLV_SCLK3 12
|
||||
#define AUD_CLKID_SLV_SCLK4 13
|
||||
#define AUD_CLKID_SLV_SCLK5 14
|
||||
#define AUD_CLKID_SLV_SCLK6 15
|
||||
#define AUD_CLKID_SLV_SCLK7 16
|
||||
#define AUD_CLKID_SLV_SCLK8 17
|
||||
#define AUD_CLKID_SLV_SCLK9 18
|
||||
#define AUD_CLKID_SLV_LRCLK0 19
|
||||
#define AUD_CLKID_SLV_LRCLK1 20
|
||||
#define AUD_CLKID_SLV_LRCLK2 21
|
||||
#define AUD_CLKID_SLV_LRCLK3 22
|
||||
#define AUD_CLKID_SLV_LRCLK4 23
|
||||
#define AUD_CLKID_SLV_LRCLK5 24
|
||||
#define AUD_CLKID_SLV_LRCLK6 25
|
||||
#define AUD_CLKID_SLV_LRCLK7 26
|
||||
#define AUD_CLKID_SLV_LRCLK8 27
|
||||
#define AUD_CLKID_SLV_LRCLK9 28
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#define AUD_CLKID_DDR_ARB 29
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#define AUD_CLKID_PDM 30
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#define AUD_CLKID_TDMIN_A 31
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|||
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@ -26,7 +26,9 @@
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#define CLKID_AO_M4_FCLK 13
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#define CLKID_AO_M4_HCLK 14
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#define CLKID_AO_CLK81 15
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#define CLKID_AO_SAR_ADC_SEL 16
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#define CLKID_AO_SAR_ADC_CLK 18
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#define CLKID_AO_CTS_OSCIN 19
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#define CLKID_AO_32K 23
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#define CLKID_AO_CEC 27
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#define CLKID_AO_CTS_RTC_OSCIN 28
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|
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|||
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@ -131,5 +131,10 @@
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#define CLKID_MALI_1 174
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#define CLKID_MALI 175
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#define CLKID_MPLL_5OM 177
|
||||
#define CLKID_CPU_CLK 187
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||||
#define CLKID_PCIE_PLL 201
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||||
#define CLKID_VDEC_1 204
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||||
#define CLKID_VDEC_HEVC 207
|
||||
#define CLKID_VDEC_HEVCF 210
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||||
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||||
#endif /* __G12A_CLKC_H */
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||||
|
|
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|||
|
|
@ -103,10 +103,14 @@
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|||
#define CLKID_MPLL1 94
|
||||
#define CLKID_MPLL2 95
|
||||
#define CLKID_NAND_CLK 112
|
||||
#define CLKID_ABP 124
|
||||
#define CLKID_APB 124
|
||||
#define CLKID_PERIPH 126
|
||||
#define CLKID_AXI 128
|
||||
#define CLKID_L2_DRAM 130
|
||||
#define CLKID_VPU 190
|
||||
#define CLKID_VDEC_1 196
|
||||
#define CLKID_VDEC_HCODEC 199
|
||||
#define CLKID_VDEC_2 202
|
||||
#define CLKID_VDEC_HEVC 206
|
||||
|
||||
#endif /* __MESON8B_CLKC_H */
|
||||
|
|
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|||
|
|
@ -51,7 +51,10 @@
|
|||
#define RESET_SD_EMMC_A 44
|
||||
#define RESET_SD_EMMC_B 45
|
||||
#define RESET_SD_EMMC_C 46
|
||||
/* 47-60 */
|
||||
/* 47 */
|
||||
#define RESET_USB_PHY20 48
|
||||
#define RESET_USB_PHY21 49
|
||||
/* 50-60 */
|
||||
#define RESET_AUDIO_CODEC 61
|
||||
/* 62-63 */
|
||||
/* RESET2 */
|
||||
|
|
|
|||
Loading…
Reference in New Issue