mt6795
- enable frequency hopping controller (FHCTL) - add i2c, power domains and some clocks for video enconde/decode - Sony Xperia M5 enable touchscreen, proximity sensor, accelerometer and NFC mt8173 - align keys with DT binding mt8183 - enable GPU DVFS mt8186 - enable GPU mt8192 - enable GPU mt8195 - add mutex for Video Processor Pipeline Subsystem (VPP) - add support for Mali-G57 Valhall Natt GPU baked by panfrost - add support for display on vdosys1 - add thermal support - add display PWM mt8365 - add support for the eval kit including i2c, pmic-wrapper, mmc and ethernet -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAmQ5gfsXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH5u1Q/8DIMqPn9FZkC6bBaxK2GoCSav +u5fG4fC3LimDtR+N8M7C9eV4Dag94IxeRlmcEW9e7U0KBvPq9YqFp8Ul0a61LTg vdtGs6wLar4/P9ohVvHJ8Kj9Kf6r2/sjYK303VK8jKUlGBbQvReoY12irOhSVwJ2 qlaDZUiWhZTP+EoQxF4uUvvEerFfrYLalHpKocxfQojFWrs8OpZ0kJVa69GBcO9j jCAhQ3V6xL94ZC8NtF/gcgGmMVWXDY/J4DjekX4X9H332/pDfC1NKCFb4wzr6I2t 3ySEk7f7ysytWCBF3vaEREz1kJZawzsA58PE5oWziiB+iI+0nr9zn5RbX3dG8cd2 cbvuiv747xZZXuz9I5cuQYqeO/enI962aaDH/hJ92r0pLJEJB9S1jPAAusxho9Hy TwzZTVhDi6Ha8zRYzxBizARL/BwGVN+iH7iTKn5GQ8oDfIZ949FQuRd1OrMDxZ1A JUKSCHWC38dUd6323w03TbZMdWsX1Xwsvr1o06tEBdKas4U2+qX9Pl5vRiAlIdTy Xz9se3W4DQbU9ihk6ydvSvFNWKqpbCL764rK9vMo/kCltxixZ3sbzNFY+LG854TQ GlEXdsJZg67WjDWhCQloto8fuUhmf1/Pc20F854aibRan0HnKCC2aluLHqBylO77 TL9HItdqvrRn10hIuJk= =s32c -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmQ5uGsACgkQYKtH/8kJ UifODhAAwj4X5LId2gSHyzezoiUCDR2IYpj2g6rLvtS5vzZtCp72FjFUbKU9uErF Crwg+k0LuNV+WMyMbWCElAy9mwuNMOXSnQkFYY5gnRG/0iWGuydDBlYcnRCkxYrQ JUhYOEQ3+zxblgoaB6go3JQrXdUyGdqrhN4XhOPGkOWRn2zYbvCmtT+AoBWwgPh0 TrrS8IuKG/u2rzZYSqKlPCCFRvbDuco/FmGLHBxQAdr3r0FnEXlRyJ/S1okXAcMx un/kiTcBETjCJDMeXGu2kyxdiPhF5B+SB9xSXQbtgFKuzBKvUNaMTV7f5i9q6gym GP2jJrHqsNFIAegJ50XOd/v1xDMF8CFJ1ooWVAotbZxVHtxNEgYWaMiukWuYvNvT encnz5FG8cJvbX90vK1W9S0KSFHOVh/75fiZ7Tut4WPhvtcj6bsfqM98ELk7f9UT 4VdohyoDTmf3fOYWL0tACgnHo2vsVh4j7BEBDXbjJaeEfmwuWbaFgtu8CAlcEKsj VsTyiXtHl6NHlitHpYj6996ZyKQYSxxPpD6miDCNbeFQjTHyhyrgKmwayJ72y+8v TNxSF1aKhMgV3WZinAf5wQ6o1Dka3jjVhdbvOIzap36mjJ89EMGSVCtG79lbKDSa jWfneYferjIDmZJX/xivLqVWjF9BRYqcJlv/ZlGIE9G2PnRmQkk= =ZI7k -----END PGP SIGNATURE----- Merge tag 'v6.3-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into soc/dt mt6795 - enable frequency hopping controller (FHCTL) - add i2c, power domains and some clocks for video enconde/decode - Sony Xperia M5 enable touchscreen, proximity sensor, accelerometer and NFC mt8173 - align keys with DT binding mt8183 - enable GPU DVFS mt8186 - enable GPU mt8192 - enable GPU mt8195 - add mutex for Video Processor Pipeline Subsystem (VPP) - add support for Mali-G57 Valhall Natt GPU baked by panfrost - add support for display on vdosys1 - add thermal support - add display PWM mt8365 - add support for the eval kit including i2c, pmic-wrapper, mmc and ethernet * tag 'v6.3-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (50 commits) arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMM050 Magnetometer arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMA255 Accelerometer arm64: dts: mediatek: mt6795: Add tertiary PWM node arm64: dts: mediatek: mt8173: correct GPIO keys wakeup arm64: dts: mediatek: mt6795-xperia-m5: Add NXP PN547 NFC on I2C3 arm64: dts: mediatek: mt6795-xperia-m5: Add Sensortek STK3310 Proximity arm64: dts: mediatek: mt6795-xperia-m5: Add Synaptics RMI4 Touchscreen arm64: dts: mediatek: mt6795-xperia-m5: Enable I2C 0-3 busses arm64: dts: mediatek: mt6795: Add VDECSYS and VENCSYS clocks arm64: dts: mediatek: mt6795: Add SoC power domains arm64: dts: mediatek: mt6795: Add nodes for I2C controllers arm64: dts: mediatek: mt6795: xperia-m5: Enable Frequency Hopping arm64: dts: mediatek: mt6795: Add apmixedsys syscon node arm64: dts: mediatek: mt6795: Add Frequency Hopping Controller node arm64: dts: mediatek: cherry: Add configuration for display backlight arm64: dts: mediatek: mt8195: Add display pwm nodes arm64: dts: mediatek: mt8195: Add temperature mitigation threshold arm64: dts: mediatek: mt8195: Add thermal zones and thermal nodes arm64: dts: mediatek: add ethernet support for mt8365 SoC arm64: dts: mediatek: add mmc support for mt8365 SoC ... Link: https://lore.kernel.org/r/6920736b-ddb3-29df-d0b2-46db40cef49f@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
1e14b4f9d9
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@ -52,4 +52,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
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@ -559,7 +559,7 @@
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status = "disabled";
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};
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nandc: nfi@1100e000 {
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nandc: nand-controller@1100e000 {
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compatible = "mediatek,mt2712-nfc";
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reg = <0 0x1100e000 0 0x1000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
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@ -0,0 +1,282 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Copyright (c) 2023 BayLibre Inc.
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*/
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#include <dt-bindings/input/input.h>
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&pwrap {
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mt6357_pmic: pmic {
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compatible = "mediatek,mt6357";
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regulators {
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mt6357_vproc_reg: buck-vproc {
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regulator-name = "vproc";
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regulator-min-microvolt = <518750>;
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regulator-max-microvolt = <1312500>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <220>;
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regulator-always-on;
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};
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mt6357_vcore_reg: buck-vcore {
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regulator-name = "vcore";
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regulator-min-microvolt = <518750>;
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regulator-max-microvolt = <1312500>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <220>;
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regulator-always-on;
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};
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mt6357_vmodem_reg: buck-vmodem {
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regulator-name = "vmodem";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1193750>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <220>;
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};
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mt6357_vs1_reg: buck-vs1 {
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regulator-name = "vs1";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <2200000>;
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regulator-ramp-delay = <12500>;
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regulator-enable-ramp-delay = <220>;
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regulator-always-on;
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};
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mt6357_vpa_reg: buck-vpa {
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regulator-name = "vpa";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3650000>;
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regulator-ramp-delay = <50000>;
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regulator-enable-ramp-delay = <220>;
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};
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mt6357_vfe28_reg: ldo-vfe28 {
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compatible = "regulator-fixed";
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regulator-name = "vfe28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vxo22_reg: ldo-vxo22 {
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regulator-name = "vxo22";
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regulator-min-microvolt = <2200000>;
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regulator-max-microvolt = <2400000>;
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regulator-enable-ramp-delay = <110>;
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};
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mt6357_vrf18_reg: ldo-vrf18 {
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compatible = "regulator-fixed";
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regulator-name = "vrf18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <110>;
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};
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mt6357_vrf12_reg: ldo-vrf12 {
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compatible = "regulator-fixed";
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regulator-name = "vrf12";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-enable-ramp-delay = <110>;
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};
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mt6357_vefuse_reg: ldo-vefuse {
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regulator-name = "vefuse";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcn33_bt_reg: ldo-vcn33-bt {
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regulator-name = "vcn33-bt";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3500000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcn33_wifi_reg: ldo-vcn33-wifi {
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regulator-name = "vcn33-wifi";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3500000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcn28_reg: ldo-vcn28 {
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compatible = "regulator-fixed";
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regulator-name = "vcn28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcn18_reg: ldo-vcn18 {
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compatible = "regulator-fixed";
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regulator-name = "vcn18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcama_reg: ldo-vcama {
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regulator-name = "vcama";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcamd_reg: ldo-vcamd {
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regulator-name = "vcamd";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcamio_reg: ldo-vcamio18 {
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compatible = "regulator-fixed";
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regulator-name = "vcamio";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vldo28_reg: ldo-vldo28 {
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regulator-name = "vldo28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <3000000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vsram_others_reg: ldo-vsram-others {
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regulator-name = "vsram-others";
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regulator-min-microvolt = <518750>;
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regulator-max-microvolt = <1312500>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <110>;
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regulator-always-on;
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};
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mt6357_vsram_proc_reg: ldo-vsram-proc {
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regulator-name = "vsram-proc";
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regulator-min-microvolt = <518750>;
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regulator-max-microvolt = <1312500>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <110>;
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regulator-always-on;
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};
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mt6357_vaux18_reg: ldo-vaux18 {
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compatible = "regulator-fixed";
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regulator-name = "vaux18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vaud28_reg: ldo-vaud28 {
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compatible = "regulator-fixed";
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regulator-name = "vaud28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vio28_reg: ldo-vio28 {
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compatible = "regulator-fixed";
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regulator-name = "vio28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vio18_reg: ldo-vio18 {
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compatible = "regulator-fixed";
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regulator-name = "vio18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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regulator-always-on;
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};
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mt6357_vdram_reg: ldo-vdram {
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regulator-name = "vdram";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1200000>;
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regulator-enable-ramp-delay = <3300>;
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};
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mt6357_vmc_reg: ldo-vmc {
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regulator-name = "vmc";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <44>;
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};
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mt6357_vmch_reg: ldo-vmch {
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regulator-name = "vmch";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <44>;
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};
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mt6357_vemc_reg: ldo-vemc {
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regulator-name = "vemc";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <44>;
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regulator-always-on;
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};
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mt6357_vsim1_reg: ldo-vsim1 {
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regulator-name = "vsim1";
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regulator-min-microvolt = <1700000>;
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regulator-max-microvolt = <3100000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vsim2_reg: ldo-vsim2 {
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regulator-name = "vsim2";
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regulator-min-microvolt = <1700000>;
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regulator-max-microvolt = <3100000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vibr_reg: ldo-vibr {
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regulator-name = "vibr";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <44>;
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};
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mt6357_vusb33_reg: ldo-vusb33 {
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regulator-name = "vusb33";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3100000>;
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regulator-enable-ramp-delay = <264>;
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};
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};
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rtc {
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compatible = "mediatek,mt6357-rtc";
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};
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keys {
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compatible = "mediatek,mt6357-keys";
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key-power {
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linux,keycodes = <KEY_POWER>;
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wakeup-source;
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};
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key-home {
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linux,keycodes = <KEY_HOME>;
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wakeup-source;
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};
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};
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};
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};
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@ -5,6 +5,7 @@
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "mt6795.dtsi"
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/ {
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@ -48,7 +49,172 @@
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};
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};
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&fhctl {
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clocks = <&apmixedsys CLK_APMIXED_MAINPLL>, <&apmixedsys CLK_APMIXED_MPLL>,
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<&apmixedsys CLK_APMIXED_MSDCPLL>;
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mediatek,hopping-ssc-percent = <8>, <5>, <8>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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status = "okay";
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accelerometer@10 {
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compatible = "bosch,bma255";
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reg = <0x10>;
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pinctrl-names = "default";
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pinctrl-0 = <&accel_pins>;
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};
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magnetometer@12 {
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compatible = "bosch,bmm150";
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reg = <0x12>;
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};
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||||
};
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||||
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&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
status = "okay";
|
||||
|
||||
touchscreen@20 {
|
||||
compatible = "syna,rmi4-i2c";
|
||||
reg = <0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts-extended = <&pio 6 IRQ_TYPE_EDGE_FALLING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ts_pins>;
|
||||
syna,startup-delay-ms = <160>;
|
||||
syna,reset-delay-ms = <90>;
|
||||
|
||||
rmi4-f01@1 {
|
||||
reg = <0x1>;
|
||||
syna,nosleep-mode = <1>;
|
||||
};
|
||||
|
||||
rmi4-f12@12 {
|
||||
reg = <0x12>;
|
||||
syna,sensor-type = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
status = "okay";
|
||||
|
||||
pn547: nfc@28 {
|
||||
compatible = "nxp,pn544-i2c";
|
||||
reg = <0x28>;
|
||||
interrupts-extended = <&pio 3 IRQ_TYPE_EDGE_RISING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nfc_pins>;
|
||||
enable-gpios = <&pio 149 GPIO_ACTIVE_HIGH>;
|
||||
firmware-gpios = <&pio 94 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
proximity@48 {
|
||||
compatible = "sensortek,stk3310";
|
||||
reg = <0x48>;
|
||||
interrupts-extended = <&pio 8 IRQ_TYPE_EDGE_FALLING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&proximity_pins>;
|
||||
};
|
||||
};
|
||||
|
||||
&pio {
|
||||
nfc_pins: nfc-pins {
|
||||
pins-irq {
|
||||
pinmux = <PINMUX_GPIO3__FUNC_GPIO3>;
|
||||
bias-pull-down;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
pins-fw-ven {
|
||||
pinmux = <PINMUX_GPIO94__FUNC_GPIO94>,
|
||||
<PINMUX_GPIO149__FUNC_GPIO149>;
|
||||
};
|
||||
};
|
||||
|
||||
ts_pins: touchscreen-pins {
|
||||
pins-irq {
|
||||
pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
pins-rst {
|
||||
pinmux = <PINMUX_GPIO102__FUNC_GPIO102>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
proximity_pins: proximity-pins {
|
||||
pins-irq {
|
||||
pinmux = <PINMUX_GPIO8__FUNC_GPIO8>;
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
accel_pins: accelerometer-pins {
|
||||
pins-irq {
|
||||
pinmux = <PINMUX_GPIO12__FUNC_GPIO12>;
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0-pins {
|
||||
pins-bus {
|
||||
pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
|
||||
<PINMUX_GPIO46__FUNC_SCL0>;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1-pins {
|
||||
pins-bus {
|
||||
pinmux = <PINMUX_GPIO125__FUNC_SDA1>,
|
||||
<PINMUX_GPIO126__FUNC_SCL1>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2-pins {
|
||||
pins-bus {
|
||||
pinmux = <PINMUX_GPIO43__FUNC_SDA2>,
|
||||
<PINMUX_GPIO44__FUNC_SCL2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3_pins: i2c3-pins {
|
||||
pins-bus {
|
||||
pinmux = <PINMUX_GPIO136__FUNC_SDA3>,
|
||||
<PINMUX_GPIO137__FUNC_SCL3>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4-pins {
|
||||
pins-bus {
|
||||
pinmux = <PINMUX_GPIO100__FUNC_SDA4>,
|
||||
<PINMUX_GPIO101__FUNC_SCL4>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
pins-rx {
|
||||
pinmux = <PINMUX_GPIO113__FUNC_URXD0>;
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
|
||||
#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
|
||||
#include <dt-bindings/power/mt6795-power.h>
|
||||
#include <dt-bindings/reset/mediatek,mt6795-resets.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -264,6 +265,84 @@
|
|||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
scpsys: syscon@10006000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0 0x10006000 0 0x1000>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
/* System Power Manager */
|
||||
spm: power-controller {
|
||||
compatible = "mediatek,mt6795-power-controller";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
/* power domains of the SoC */
|
||||
power-domain@MT6795_POWER_DOMAIN_VDEC {
|
||||
reg = <MT6795_POWER_DOMAIN_VDEC>;
|
||||
clocks = <&topckgen CLK_TOP_MM_SEL>;
|
||||
clock-names = "mm";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
power-domain@MT6795_POWER_DOMAIN_VENC {
|
||||
reg = <MT6795_POWER_DOMAIN_VENC>;
|
||||
clocks = <&topckgen CLK_TOP_MM_SEL>,
|
||||
<&topckgen CLK_TOP_VENC_SEL>;
|
||||
clock-names = "mm", "venc";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
power-domain@MT6795_POWER_DOMAIN_ISP {
|
||||
reg = <MT6795_POWER_DOMAIN_ISP>;
|
||||
clocks = <&topckgen CLK_TOP_MM_SEL>;
|
||||
clock-names = "mm";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
power-domain@MT6795_POWER_DOMAIN_MM {
|
||||
reg = <MT6795_POWER_DOMAIN_MM>;
|
||||
clocks = <&topckgen CLK_TOP_MM_SEL>;
|
||||
clock-names = "mm";
|
||||
#power-domain-cells = <0>;
|
||||
mediatek,infracfg = <&infracfg>;
|
||||
};
|
||||
|
||||
power-domain@MT6795_POWER_DOMAIN_MJC {
|
||||
reg = <MT6795_POWER_DOMAIN_MJC>;
|
||||
clocks = <&topckgen CLK_TOP_MM_SEL>,
|
||||
<&topckgen CLK_TOP_MJC_SEL>;
|
||||
clock-names = "mm", "mjc";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
power-domain@MT6795_POWER_DOMAIN_AUDIO {
|
||||
reg = <MT6795_POWER_DOMAIN_AUDIO>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC {
|
||||
reg = <MT6795_POWER_DOMAIN_MFG_ASYNC>;
|
||||
clocks = <&clk26m>;
|
||||
clock-names = "mfg";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
power-domain@MT6795_POWER_DOMAIN_MFG_2D {
|
||||
reg = <MT6795_POWER_DOMAIN_MFG_2D>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
power-domain@MT6795_POWER_DOMAIN_MFG {
|
||||
reg = <MT6795_POWER_DOMAIN_MFG>;
|
||||
#power-domain-cells = <0>;
|
||||
mediatek,infracfg = <&infracfg>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pio: pinctrl@10005000 {
|
||||
compatible = "mediatek,mt6795-pinctrl";
|
||||
reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
|
||||
|
|
@ -310,6 +389,18 @@
|
|||
clock-names = "clk13m";
|
||||
};
|
||||
|
||||
apmixedsys: syscon@10209000 {
|
||||
compatible = "mediatek,mt6795-apmixedsys", "syscon";
|
||||
reg = <0 0x10209000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
fhctl: clock-controller@10209f00 {
|
||||
compatible = "mediatek,mt6795-fhctl";
|
||||
reg = <0 0x10209f00 0 0x100>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@10221000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -433,6 +524,85 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@11006000 {
|
||||
compatible = "mediatek,mt6795-pwm";
|
||||
reg = <0 0x11006000 0 0x1000>;
|
||||
#pwm-cells = <2>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_PWM_SEL>,
|
||||
<&pericfg CLK_PERI_PWM>,
|
||||
<&pericfg CLK_PERI_PWM1>,
|
||||
<&pericfg CLK_PERI_PWM2>,
|
||||
<&pericfg CLK_PERI_PWM3>,
|
||||
<&pericfg CLK_PERI_PWM4>,
|
||||
<&pericfg CLK_PERI_PWM5>,
|
||||
<&pericfg CLK_PERI_PWM6>,
|
||||
<&pericfg CLK_PERI_PWM7>;
|
||||
clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
|
||||
"pwm4", "pwm5", "pwm6", "pwm7";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11007000 {
|
||||
compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
|
||||
reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11008000 {
|
||||
compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
|
||||
reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@11009000 {
|
||||
compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
|
||||
reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@11010000 {
|
||||
compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
|
||||
reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@11011000 {
|
||||
compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
|
||||
reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@11230000 {
|
||||
compatible = "mediatek,mt6795-mmc";
|
||||
reg = <0 0x11230000 0 0x1000>;
|
||||
|
|
@ -473,5 +643,17 @@
|
|||
clock-names = "source", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vdecsys: clock-controller@16000000 {
|
||||
compatible = "mediatek,mt6795-vdecsys";
|
||||
reg = <0 0x16000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
vencsys: clock-controller@18000000 {
|
||||
compatible = "mediatek,mt6795-vencsys";
|
||||
reg = <0 0x18000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -539,7 +539,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
nandc: nfi@1100d000 {
|
||||
nandc: nand-controller@1100d000 {
|
||||
compatible = "mediatek,mt7622-nfc";
|
||||
reg = <0 0x1100D000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
|
|
|||
|
|
@ -124,7 +124,7 @@
|
|||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
mmsys: mmsys@14000000 {
|
||||
mmsys: syscon@14000000 {
|
||||
compatible = "mediatek,mt8167-mmsys", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@
|
|||
gpios = <&pio 69 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <SW_LID>;
|
||||
linux,input-type = <EV_SW>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
switch-power {
|
||||
|
|
@ -66,7 +66,7 @@
|
|||
gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_POWER>;
|
||||
debounce-interval = <30>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
switch-tablet-mode {
|
||||
|
|
@ -74,7 +74,7 @@
|
|||
gpios = <&pio 121 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <SW_TABLET_MODE>;
|
||||
linux,input-type = <EV_SW>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
switch-volume-down {
|
||||
|
|
|
|||
|
|
@ -52,7 +52,6 @@
|
|||
|
||||
&gpu {
|
||||
mali-supply = <&mt6358_vgpu_reg>;
|
||||
sram-supply = <&mt6358_vsram_gpu_reg>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
|
|
@ -138,6 +137,22 @@
|
|||
non-removable;
|
||||
};
|
||||
|
||||
&mt6358_vgpu_reg {
|
||||
regulator-min-microvolt = <625000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
|
||||
regulator-coupled-max-spread = <100000>;
|
||||
};
|
||||
|
||||
&mt6358_vsram_gpu_reg {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
|
||||
regulator-coupled-with = <&mt6358_vgpu_reg>;
|
||||
regulator-coupled-max-spread = <100000>;
|
||||
};
|
||||
|
||||
&pio {
|
||||
i2c_pins_0: i2c0{
|
||||
pins_i2c{
|
||||
|
|
|
|||
|
|
@ -294,7 +294,6 @@
|
|||
|
||||
&gpu {
|
||||
mali-supply = <&mt6358_vgpu_reg>;
|
||||
sram-supply = <&mt6358_vsram_gpu_reg>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
|
|
@ -401,6 +400,14 @@
|
|||
Avdd-supply = <&mt6358_vaud28_reg>;
|
||||
};
|
||||
|
||||
&mt6358_vgpu_reg {
|
||||
regulator-min-microvolt = <625000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
|
||||
regulator-coupled-max-spread = <100000>;
|
||||
};
|
||||
|
||||
&mt6358_vsim1_reg {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
|
|
@ -411,6 +418,14 @@
|
|||
regulator-max-microvolt = <2700000>;
|
||||
};
|
||||
|
||||
&mt6358_vsram_gpu_reg {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
|
||||
regulator-coupled-with = <&mt6358_vgpu_reg>;
|
||||
regulator-coupled-max-spread = <100000>;
|
||||
};
|
||||
|
||||
&pio {
|
||||
aud_pins_default: audiopins {
|
||||
pins_bus {
|
||||
|
|
|
|||
|
|
@ -71,7 +71,6 @@
|
|||
|
||||
&gpu {
|
||||
mali-supply = <&mt6358_vgpu_reg>;
|
||||
sram-supply = <&mt6358_vsram_gpu_reg>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
|
|
@ -176,6 +175,22 @@
|
|||
non-removable;
|
||||
};
|
||||
|
||||
&mt6358_vgpu_reg {
|
||||
regulator-min-microvolt = <625000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
|
||||
regulator-coupled-max-spread = <100000>;
|
||||
};
|
||||
|
||||
&mt6358_vsram_gpu_reg {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
|
||||
regulator-coupled-with = <&mt6358_vgpu_reg>;
|
||||
regulator-coupled-max-spread = <100000>;
|
||||
};
|
||||
|
||||
&pio {
|
||||
i2c_pins_0: i2c0 {
|
||||
pins_i2c{
|
||||
|
|
|
|||
|
|
@ -563,82 +563,82 @@
|
|||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
opp-microvolt = <625000>, <850000>;
|
||||
opp-microvolt = <625000>;
|
||||
};
|
||||
|
||||
opp-320000000 {
|
||||
opp-hz = /bits/ 64 <320000000>;
|
||||
opp-microvolt = <631250>, <850000>;
|
||||
opp-microvolt = <631250>;
|
||||
};
|
||||
|
||||
opp-340000000 {
|
||||
opp-hz = /bits/ 64 <340000000>;
|
||||
opp-microvolt = <637500>, <850000>;
|
||||
opp-microvolt = <637500>;
|
||||
};
|
||||
|
||||
opp-360000000 {
|
||||
opp-hz = /bits/ 64 <360000000>;
|
||||
opp-microvolt = <643750>, <850000>;
|
||||
opp-microvolt = <643750>;
|
||||
};
|
||||
|
||||
opp-380000000 {
|
||||
opp-hz = /bits/ 64 <380000000>;
|
||||
opp-microvolt = <650000>, <850000>;
|
||||
opp-microvolt = <650000>;
|
||||
};
|
||||
|
||||
opp-400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <656250>, <850000>;
|
||||
opp-microvolt = <656250>;
|
||||
};
|
||||
|
||||
opp-420000000 {
|
||||
opp-hz = /bits/ 64 <420000000>;
|
||||
opp-microvolt = <662500>, <850000>;
|
||||
opp-microvolt = <662500>;
|
||||
};
|
||||
|
||||
opp-460000000 {
|
||||
opp-hz = /bits/ 64 <460000000>;
|
||||
opp-microvolt = <675000>, <850000>;
|
||||
opp-microvolt = <675000>;
|
||||
};
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <687500>, <850000>;
|
||||
opp-microvolt = <687500>;
|
||||
};
|
||||
|
||||
opp-540000000 {
|
||||
opp-hz = /bits/ 64 <540000000>;
|
||||
opp-microvolt = <700000>, <850000>;
|
||||
opp-microvolt = <700000>;
|
||||
};
|
||||
|
||||
opp-580000000 {
|
||||
opp-hz = /bits/ 64 <580000000>;
|
||||
opp-microvolt = <712500>, <850000>;
|
||||
opp-microvolt = <712500>;
|
||||
};
|
||||
|
||||
opp-620000000 {
|
||||
opp-hz = /bits/ 64 <620000000>;
|
||||
opp-microvolt = <725000>, <850000>;
|
||||
opp-microvolt = <725000>;
|
||||
};
|
||||
|
||||
opp-653000000 {
|
||||
opp-hz = /bits/ 64 <653000000>;
|
||||
opp-microvolt = <743750>, <850000>;
|
||||
opp-microvolt = <743750>;
|
||||
};
|
||||
|
||||
opp-698000000 {
|
||||
opp-hz = /bits/ 64 <698000000>;
|
||||
opp-microvolt = <768750>, <868750>;
|
||||
opp-microvolt = <768750>;
|
||||
};
|
||||
|
||||
opp-743000000 {
|
||||
opp-hz = /bits/ 64 <743000000>;
|
||||
opp-microvolt = <793750>, <893750>;
|
||||
opp-microvolt = <793750>;
|
||||
};
|
||||
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <825000>, <925000>;
|
||||
opp-microvolt = <825000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1752,7 +1752,7 @@
|
|||
};
|
||||
|
||||
gpu: gpu@13040000 {
|
||||
compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
|
||||
compatible = "mediatek,mt8183b-mali", "arm,mali-bifrost";
|
||||
reg = <0 0x13040000 0 0x4000>;
|
||||
interrupts =
|
||||
<GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
|
||||
|
|
|
|||
|
|
@ -1075,6 +1075,23 @@
|
|||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gpu: gpu@13040000 {
|
||||
compatible = "mediatek,mt8186-mali",
|
||||
"arm,mali-bifrost";
|
||||
reg = <0 0x13040000 0 0x4000>;
|
||||
|
||||
clocks = <&mfgsys CLK_MFG_BG3D>;
|
||||
interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
|
||||
<&spm MT8186_POWER_DOMAIN_MFG3>;
|
||||
power-domain-names = "core0", "core1";
|
||||
#cooling-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmsys: syscon@14000000 {
|
||||
compatible = "mediatek,mt8186-mmsys", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
|
|
|
|||
|
|
@ -275,6 +275,11 @@
|
|||
remote-endpoint = <&anx7625_in>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&mt6315_7_vbuck1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -380,6 +385,14 @@
|
|||
pinctrl-0 = <&i2c7_pins>;
|
||||
};
|
||||
|
||||
&mfg0 {
|
||||
domain-supply = <&mt6315_7_vbuck1>;
|
||||
};
|
||||
|
||||
&mfg1 {
|
||||
domain-supply = <&mt6359_vsram_others_ldo_reg>;
|
||||
};
|
||||
|
||||
&mipi_tx0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -439,6 +452,13 @@
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
&mt6359_vsram_others_ldo_reg {
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-coupled-with = <&mt6315_7_vbuck1>;
|
||||
regulator-coupled-max-spread = <10000>;
|
||||
};
|
||||
|
||||
&mt6359_vufs_ldo_reg {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
|
@ -1400,9 +1420,11 @@
|
|||
regulator-compatible = "vbuck1";
|
||||
regulator-name = "Vgpu";
|
||||
regulator-min-microvolt = <606250>;
|
||||
regulator-max-microvolt = <1193750>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-enable-ramp-delay = <256>;
|
||||
regulator-allowed-modes = <0 1 2>;
|
||||
regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
|
||||
regulator-coupled-max-spread = <10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -312,6 +312,91 @@
|
|||
clock-frequency = <13000000>;
|
||||
};
|
||||
|
||||
gpu_opp_table: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-358000000 {
|
||||
opp-hz = /bits/ 64 <358000000>;
|
||||
opp-microvolt = <606250>;
|
||||
};
|
||||
|
||||
opp-399000000 {
|
||||
opp-hz = /bits/ 64 <399000000>;
|
||||
opp-microvolt = <618750>;
|
||||
};
|
||||
|
||||
opp-440000000 {
|
||||
opp-hz = /bits/ 64 <440000000>;
|
||||
opp-microvolt = <631250>;
|
||||
};
|
||||
|
||||
opp-482000000 {
|
||||
opp-hz = /bits/ 64 <482000000>;
|
||||
opp-microvolt = <643750>;
|
||||
};
|
||||
|
||||
opp-523000000 {
|
||||
opp-hz = /bits/ 64 <523000000>;
|
||||
opp-microvolt = <656250>;
|
||||
};
|
||||
|
||||
opp-564000000 {
|
||||
opp-hz = /bits/ 64 <564000000>;
|
||||
opp-microvolt = <668750>;
|
||||
};
|
||||
|
||||
opp-605000000 {
|
||||
opp-hz = /bits/ 64 <605000000>;
|
||||
opp-microvolt = <681250>;
|
||||
};
|
||||
|
||||
opp-647000000 {
|
||||
opp-hz = /bits/ 64 <647000000>;
|
||||
opp-microvolt = <693750>;
|
||||
};
|
||||
|
||||
opp-688000000 {
|
||||
opp-hz = /bits/ 64 <688000000>;
|
||||
opp-microvolt = <706250>;
|
||||
};
|
||||
|
||||
opp-724000000 {
|
||||
opp-hz = /bits/ 64 <724000000>;
|
||||
opp-microvolt = <725000>;
|
||||
};
|
||||
|
||||
opp-748000000 {
|
||||
opp-hz = /bits/ 64 <748000000>;
|
||||
opp-microvolt = <737500>;
|
||||
};
|
||||
|
||||
opp-772000000 {
|
||||
opp-hz = /bits/ 64 <772000000>;
|
||||
opp-microvolt = <750000>;
|
||||
};
|
||||
|
||||
opp-795000000 {
|
||||
opp-hz = /bits/ 64 <795000000>;
|
||||
opp-microvolt = <762500>;
|
||||
};
|
||||
|
||||
opp-819000000 {
|
||||
opp-hz = /bits/ 64 <819000000>;
|
||||
opp-microvolt = <775000>;
|
||||
};
|
||||
|
||||
opp-843000000 {
|
||||
opp-hz = /bits/ 64 <843000000>;
|
||||
opp-microvolt = <787500>;
|
||||
};
|
||||
|
||||
opp-866000000 {
|
||||
opp-hz = /bits/ 64 <866000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -412,15 +497,16 @@
|
|||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
power-domain@MT8192_POWER_DOMAIN_MFG0 {
|
||||
mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 {
|
||||
reg = <MT8192_POWER_DOMAIN_MFG0>;
|
||||
clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
|
||||
clock-names = "mfg";
|
||||
clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
|
||||
<&topckgen CLK_TOP_MFG_REF_SEL>;
|
||||
clock-names = "mfg", "alt";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
power-domain@MT8192_POWER_DOMAIN_MFG1 {
|
||||
mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 {
|
||||
reg = <MT8192_POWER_DOMAIN_MFG1>;
|
||||
mediatek,infracfg = <&infracfg>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1266,6 +1352,28 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu: gpu@13000000 {
|
||||
compatible = "mediatek,mt8192-mali", "arm,mali-valhall-jm";
|
||||
reg = <0 0x13000000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
|
||||
clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
|
||||
|
||||
power-domains = <&spm MT8192_POWER_DOMAIN_MFG2>,
|
||||
<&spm MT8192_POWER_DOMAIN_MFG3>,
|
||||
<&spm MT8192_POWER_DOMAIN_MFG4>,
|
||||
<&spm MT8192_POWER_DOMAIN_MFG5>,
|
||||
<&spm MT8192_POWER_DOMAIN_MFG6>;
|
||||
power-domain-names = "core0", "core1", "core2", "core3", "core4";
|
||||
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mfgcfg: clock-controller@13fbf000 {
|
||||
compatible = "mediatek,mt8192-mfgcfg";
|
||||
reg = <0 0x13fbf000 0 0x1000>;
|
||||
|
|
|
|||
|
|
@ -22,6 +22,16 @@
|
|||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
backlight_lcd0: backlight-lcd0 {
|
||||
compatible = "pwm-backlight";
|
||||
brightness-levels = <0 1023>;
|
||||
default-brightness-level = <576>;
|
||||
enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>;
|
||||
num-interpolated-steps = <1023>;
|
||||
pwms = <&disp_pwm0 0 500000>;
|
||||
power-supply = <&ppvar_sys>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
|
@ -212,6 +222,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
&disp_pwm0 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&disp_pwm0_pin_default>;
|
||||
};
|
||||
|
||||
&dp_tx {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -238,6 +255,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
mali-supply = <&mt6315_7_vbuck1>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -648,6 +670,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
disp_pwm0_pin_default: disp-pwm0-default-pins {
|
||||
pins-disp-pwm {
|
||||
pinmux = <PINMUX_GPIO82__FUNC_GPIO82>,
|
||||
<PINMUX_GPIO97__FUNC_DISP_PWM0>;
|
||||
};
|
||||
};
|
||||
|
||||
dptx_pin: dptx-default-pins {
|
||||
pins-cmd-dat {
|
||||
pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>;
|
||||
|
|
|
|||
|
|
@ -14,6 +14,8 @@
|
|||
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
|
||||
#include <dt-bindings/power/mt8195-power.h>
|
||||
#include <dt-bindings/reset/mt8195-resets.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt8195";
|
||||
|
|
@ -24,6 +26,22 @@
|
|||
aliases {
|
||||
gce0 = &gce0;
|
||||
gce1 = &gce1;
|
||||
ethdr0 = ðdr0;
|
||||
mutex0 = &mutex;
|
||||
mutex1 = &mutex1;
|
||||
merge1 = &merge1;
|
||||
merge2 = &merge2;
|
||||
merge3 = &merge3;
|
||||
merge4 = &merge4;
|
||||
merge5 = &merge5;
|
||||
vdo1-rdma0 = &vdo1_rdma0;
|
||||
vdo1-rdma1 = &vdo1_rdma1;
|
||||
vdo1-rdma2 = &vdo1_rdma2;
|
||||
vdo1-rdma3 = &vdo1_rdma3;
|
||||
vdo1-rdma4 = &vdo1_rdma4;
|
||||
vdo1-rdma5 = &vdo1_rdma5;
|
||||
vdo1-rdma6 = &vdo1_rdma6;
|
||||
vdo1-rdma7 = &vdo1_rdma7;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -333,6 +351,76 @@
|
|||
#performance-domain-cells = <1>;
|
||||
};
|
||||
|
||||
gpu_opp_table: opp-table-gpu {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-390000000 {
|
||||
opp-hz = /bits/ 64 <390000000>;
|
||||
opp-microvolt = <625000>;
|
||||
};
|
||||
opp-410000000 {
|
||||
opp-hz = /bits/ 64 <410000000>;
|
||||
opp-microvolt = <631250>;
|
||||
};
|
||||
opp-431000000 {
|
||||
opp-hz = /bits/ 64 <431000000>;
|
||||
opp-microvolt = <631250>;
|
||||
};
|
||||
opp-473000000 {
|
||||
opp-hz = /bits/ 64 <473000000>;
|
||||
opp-microvolt = <637500>;
|
||||
};
|
||||
opp-515000000 {
|
||||
opp-hz = /bits/ 64 <515000000>;
|
||||
opp-microvolt = <637500>;
|
||||
};
|
||||
opp-556000000 {
|
||||
opp-hz = /bits/ 64 <556000000>;
|
||||
opp-microvolt = <643750>;
|
||||
};
|
||||
opp-598000000 {
|
||||
opp-hz = /bits/ 64 <598000000>;
|
||||
opp-microvolt = <650000>;
|
||||
};
|
||||
opp-640000000 {
|
||||
opp-hz = /bits/ 64 <640000000>;
|
||||
opp-microvolt = <650000>;
|
||||
};
|
||||
opp-670000000 {
|
||||
opp-hz = /bits/ 64 <670000000>;
|
||||
opp-microvolt = <662500>;
|
||||
};
|
||||
opp-700000000 {
|
||||
opp-hz = /bits/ 64 <700000000>;
|
||||
opp-microvolt = <675000>;
|
||||
};
|
||||
opp-730000000 {
|
||||
opp-hz = /bits/ 64 <730000000>;
|
||||
opp-microvolt = <687500>;
|
||||
};
|
||||
opp-760000000 {
|
||||
opp-hz = /bits/ 64 <760000000>;
|
||||
opp-microvolt = <700000>;
|
||||
};
|
||||
opp-790000000 {
|
||||
opp-hz = /bits/ 64 <790000000>;
|
||||
opp-microvolt = <712500>;
|
||||
};
|
||||
opp-820000000 {
|
||||
opp-hz = /bits/ 64 <820000000>;
|
||||
opp-microvolt = <725000>;
|
||||
};
|
||||
opp-850000000 {
|
||||
opp-hz = /bits/ 64 <850000000>;
|
||||
opp-microvolt = <737500>;
|
||||
};
|
||||
opp-880000000 {
|
||||
opp-hz = /bits/ 64 <880000000>;
|
||||
opp-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu-a55 {
|
||||
compatible = "arm,cortex-a55-pmu";
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -446,8 +534,9 @@
|
|||
|
||||
power-domain@MT8195_POWER_DOMAIN_MFG1 {
|
||||
reg = <MT8195_POWER_DOMAIN_MFG1>;
|
||||
clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
|
||||
clock-names = "mfg";
|
||||
clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
|
||||
<&topckgen CLK_TOP_MFG_CORE_TMP>;
|
||||
clock-names = "mfg", "alt";
|
||||
mediatek,infracfg = <&infracfg_ao>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1018,6 +1107,40 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
lvts_ap: thermal-sensor@1100b000 {
|
||||
compatible = "mediatek,mt8195-lvts-ap";
|
||||
reg = <0 0x1100b000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
|
||||
resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
|
||||
nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
|
||||
nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
disp_pwm0: pwm@1100e000 {
|
||||
compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
|
||||
reg = <0 0x1100e000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&topckgen CLK_TOP_DISP_PWM0>,
|
||||
<&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
|
||||
clock-names = "main", "mm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
disp_pwm1: pwm@1100f000 {
|
||||
compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
|
||||
reg = <0 0x1100f000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&topckgen CLK_TOP_DISP_PWM1>,
|
||||
<&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
|
||||
clock-names = "main", "mm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@11010000 {
|
||||
compatible = "mediatek,mt8195-spi",
|
||||
"mediatek,mt6765-spi";
|
||||
|
|
@ -1270,6 +1393,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
lvts_mcu: thermal-sensor@11278000 {
|
||||
compatible = "mediatek,mt8195-lvts-mcu";
|
||||
reg = <0 0x11278000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
|
||||
resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
|
||||
nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
|
||||
nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
xhci1: usb@11290000 {
|
||||
compatible = "mediatek,mt8195-xhci",
|
||||
"mediatek,mtk-xhci";
|
||||
|
|
@ -1789,18 +1923,47 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu: gpu@13000000 {
|
||||
compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
|
||||
"arm,mali-valhall-jm";
|
||||
reg = <0 0x13000000 0 0x4000>;
|
||||
|
||||
clocks = <&mfgcfg CLK_MFG_BG3D>;
|
||||
interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
|
||||
<&spm MT8195_POWER_DOMAIN_MFG3>,
|
||||
<&spm MT8195_POWER_DOMAIN_MFG4>,
|
||||
<&spm MT8195_POWER_DOMAIN_MFG5>,
|
||||
<&spm MT8195_POWER_DOMAIN_MFG6>;
|
||||
power-domain-names = "core0", "core1", "core2", "core3", "core4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mfgcfg: clock-controller@13fbf000 {
|
||||
compatible = "mediatek,mt8195-mfgcfg";
|
||||
reg = <0 0x13fbf000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
vppsys0: clock-controller@14000000 {
|
||||
compatible = "mediatek,mt8195-vppsys0";
|
||||
vppsys0: syscon@14000000 {
|
||||
compatible = "mediatek,mt8195-vppsys0", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mutex@1400f000 {
|
||||
compatible = "mediatek,mt8195-vpp-mutex";
|
||||
reg = <0 0x1400f000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
|
||||
clocks = <&vppsys0 CLK_VPP0_MUTEX>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
|
||||
};
|
||||
|
||||
smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
|
||||
compatible = "mediatek,mt8195-smi-sub-common";
|
||||
reg = <0 0x14010000 0 0x1000>;
|
||||
|
|
@ -1900,12 +2063,21 @@
|
|||
power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
|
||||
};
|
||||
|
||||
vppsys1: clock-controller@14f00000 {
|
||||
compatible = "mediatek,mt8195-vppsys1";
|
||||
vppsys1: syscon@14f00000 {
|
||||
compatible = "mediatek,mt8195-vppsys1", "syscon";
|
||||
reg = <0 0x14f00000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mutex@14f01000 {
|
||||
compatible = "mediatek,mt8195-vpp-mutex";
|
||||
reg = <0 0x14f01000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
|
||||
clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
|
||||
};
|
||||
|
||||
larb5: larb@14f02000 {
|
||||
compatible = "mediatek,mt8195-smi-larb";
|
||||
reg = <0 0x14f02000 0 0x1000>;
|
||||
|
|
@ -2557,7 +2729,10 @@
|
|||
vdosys1: syscon@1c100000 {
|
||||
compatible = "mediatek,mt8195-vdosys1", "syscon";
|
||||
reg = <0 0x1c100000 0 0x1000>;
|
||||
mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
smi_common_vdo: smi@1c01b000 {
|
||||
|
|
@ -2586,6 +2761,17 @@
|
|||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
|
||||
};
|
||||
|
||||
mutex1: mutex@1c101000 {
|
||||
compatible = "mediatek,mt8195-disp-mutex";
|
||||
reg = <0 0x1c101000 0 0x1000>;
|
||||
reg-names = "vdo1_mutex";
|
||||
interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
|
||||
clock-names = "vdo1_mutex";
|
||||
mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
|
||||
};
|
||||
|
||||
larb2: larb@1c102000 {
|
||||
compatible = "mediatek,mt8195-smi-larb";
|
||||
reg = <0 0x1c102000 0 0x1000>;
|
||||
|
|
@ -2610,6 +2796,151 @@
|
|||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
};
|
||||
|
||||
vdo1_rdma0: rdma@1c104000 {
|
||||
compatible = "mediatek,mt8195-vdo1-rdma";
|
||||
reg = <0 0x1c104000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
|
||||
};
|
||||
|
||||
vdo1_rdma1: rdma@1c105000 {
|
||||
compatible = "mediatek,mt8195-vdo1-rdma";
|
||||
reg = <0 0x1c105000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
|
||||
};
|
||||
|
||||
vdo1_rdma2: rdma@1c106000 {
|
||||
compatible = "mediatek,mt8195-vdo1-rdma";
|
||||
reg = <0 0x1c106000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
|
||||
};
|
||||
|
||||
vdo1_rdma3: rdma@1c107000 {
|
||||
compatible = "mediatek,mt8195-vdo1-rdma";
|
||||
reg = <0 0x1c107000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
|
||||
};
|
||||
|
||||
vdo1_rdma4: rdma@1c108000 {
|
||||
compatible = "mediatek,mt8195-vdo1-rdma";
|
||||
reg = <0 0x1c108000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
|
||||
};
|
||||
|
||||
vdo1_rdma5: rdma@1c109000 {
|
||||
compatible = "mediatek,mt8195-vdo1-rdma";
|
||||
reg = <0 0x1c109000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
|
||||
};
|
||||
|
||||
vdo1_rdma6: rdma@1c10a000 {
|
||||
compatible = "mediatek,mt8195-vdo1-rdma";
|
||||
reg = <0 0x1c10a000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
|
||||
};
|
||||
|
||||
vdo1_rdma7: rdma@1c10b000 {
|
||||
compatible = "mediatek,mt8195-vdo1-rdma";
|
||||
reg = <0 0x1c10b000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
|
||||
};
|
||||
|
||||
merge1: vpp-merge@1c10c000 {
|
||||
compatible = "mediatek,mt8195-disp-merge";
|
||||
reg = <0 0x1c10c000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
|
||||
<&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
|
||||
clock-names = "merge","merge_async";
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
|
||||
mediatek,merge-mute = <1>;
|
||||
resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
|
||||
};
|
||||
|
||||
merge2: vpp-merge@1c10d000 {
|
||||
compatible = "mediatek,mt8195-disp-merge";
|
||||
reg = <0 0x1c10d000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
|
||||
<&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
|
||||
clock-names = "merge","merge_async";
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
|
||||
mediatek,merge-mute = <1>;
|
||||
resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
|
||||
};
|
||||
|
||||
merge3: vpp-merge@1c10e000 {
|
||||
compatible = "mediatek,mt8195-disp-merge";
|
||||
reg = <0 0x1c10e000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
|
||||
<&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
|
||||
clock-names = "merge","merge_async";
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
|
||||
mediatek,merge-mute = <1>;
|
||||
resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
|
||||
};
|
||||
|
||||
merge4: vpp-merge@1c10f000 {
|
||||
compatible = "mediatek,mt8195-disp-merge";
|
||||
reg = <0 0x1c10f000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
|
||||
<&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
|
||||
clock-names = "merge","merge_async";
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
|
||||
mediatek,merge-mute = <1>;
|
||||
resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
|
||||
};
|
||||
|
||||
merge5: vpp-merge@1c110000 {
|
||||
compatible = "mediatek,mt8195-disp-merge";
|
||||
reg = <0 0x1c110000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
|
||||
<&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
|
||||
clock-names = "merge","merge_async";
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
|
||||
mediatek,merge-fifo-en = <1>;
|
||||
resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
|
||||
};
|
||||
|
||||
dp_intf1: dp-intf@1c113000 {
|
||||
compatible = "mediatek,mt8195-dp-intf";
|
||||
reg = <0 0x1c113000 0 0x1000>;
|
||||
|
|
@ -2622,6 +2953,54 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ethdr0: hdr-engine@1c114000 {
|
||||
compatible = "mediatek,mt8195-disp-ethdr";
|
||||
reg = <0 0x1c114000 0 0x1000>,
|
||||
<0 0x1c115000 0 0x1000>,
|
||||
<0 0x1c117000 0 0x1000>,
|
||||
<0 0x1c119000 0 0x1000>,
|
||||
<0 0x1c11a000 0 0x1000>,
|
||||
<0 0x1c11b000 0 0x1000>,
|
||||
<0 0x1c11c000 0 0x1000>;
|
||||
reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
|
||||
"vdo_be", "adl_ds";
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
|
||||
clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
|
||||
<&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
|
||||
<&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_BE>,
|
||||
<&vdosys1 CLK_VDO1_26M_SLOW>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
|
||||
<&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
|
||||
<&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
|
||||
<&topckgen CLK_TOP_ETHDR>;
|
||||
clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
|
||||
"vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
|
||||
"gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
|
||||
"ethdr_top";
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
|
||||
<&iommu_vpp M4U_PORT_L3_HDR_ADL>;
|
||||
interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
|
||||
resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
|
||||
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
|
||||
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
|
||||
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
|
||||
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
|
||||
reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
|
||||
"gfx_fe1_async", "vdo_be_async";
|
||||
};
|
||||
|
||||
edp_tx: edp-tx@1c500000 {
|
||||
compatible = "mediatek,mt8195-edp-tx";
|
||||
reg = <0 0x1c500000 0 0x8000>;
|
||||
|
|
@ -2644,4 +3023,246 @@
|
|||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
cpu0-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
|
||||
|
||||
trips {
|
||||
cpu0_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu0_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu0_alert>;
|
||||
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu1-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
|
||||
|
||||
trips {
|
||||
cpu1_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu1_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu1_alert>;
|
||||
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu2-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
|
||||
|
||||
trips {
|
||||
cpu2_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu2_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu2_alert>;
|
||||
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu3-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
|
||||
|
||||
trips {
|
||||
cpu3_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu3_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu3_alert>;
|
||||
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu4-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
|
||||
|
||||
trips {
|
||||
cpu4_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu4_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu4_alert>;
|
||||
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu5-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
|
||||
|
||||
trips {
|
||||
cpu5_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu5_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu5_alert>;
|
||||
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu6-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
|
||||
|
||||
trips {
|
||||
cpu6_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu6_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu6_alert>;
|
||||
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu7-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
|
||||
|
||||
trips {
|
||||
cpu7_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu7_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu7_alert>;
|
||||
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,183 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2021-2022 BayLibre, SAS.
|
||||
* Authors:
|
||||
* Fabien Parent <fparent@baylibre.com>
|
||||
* Bernhard Rosenkränzer <bero@baylibre.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
|
||||
#include "mt8365.dtsi"
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT8365 Open Platform EVK";
|
||||
compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:921600n8";
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio_keys>;
|
||||
|
||||
key-volume-up {
|
||||
gpios = <&pio 24 GPIO_ACTIVE_LOW>;
|
||||
label = "volume_up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
wakeup-source;
|
||||
debounce-interval = <15>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0xc0000000>;
|
||||
};
|
||||
|
||||
usb_otg_vbus: regulator-0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
|
||||
bl31_secmon_reserved: secmon@43000000 {
|
||||
no-map;
|
||||
reg = <0 0x43000000 0 0x30000>;
|
||||
};
|
||||
|
||||
/* 12 MiB reserved for OP-TEE (BL32)
|
||||
* +-----------------------+ 0x43e0_0000
|
||||
* | SHMEM 2MiB |
|
||||
* +-----------------------+ 0x43c0_0000
|
||||
* | | TA_RAM 8MiB |
|
||||
* + TZDRAM +--------------+ 0x4340_0000
|
||||
* | | TEE_RAM 2MiB |
|
||||
* +-----------------------+ 0x4320_0000
|
||||
*/
|
||||
optee_reserved: optee@43200000 {
|
||||
no-map;
|
||||
reg = <0 0x43200000 0 0x00c00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pio {
|
||||
gpio_keys: gpio-keys-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
|
||||
<MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
|
||||
<MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1_pins: uart1-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
|
||||
<MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
|
||||
<MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_pins: usb-pins {
|
||||
id-pins {
|
||||
pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
usb0-vbus-pins {
|
||||
pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
|
||||
output-high;
|
||||
};
|
||||
|
||||
usb1-vbus-pins {
|
||||
pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
pwm_pins: pwm-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
|
||||
<MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-0 = <&pwm_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,488 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* (C) 2018 MediaTek Inc.
|
||||
* Copyright (C) 2022 BayLibre SAS
|
||||
* Fabien Parent <fparent@baylibre.com>
|
||||
* Bernhard Rosenkränzer <bero@baylibre.com>
|
||||
*/
|
||||
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt8365";
|
||||
interrupt-parent = <&sysirq>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x2>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x3>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
|
||||
clk26m: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
clock-output-names = "clk26m";
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
gic: interrupt-controller@c000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-controller;
|
||||
reg = <0 0x0c000000 0 0x10000>, /* GICD */
|
||||
<0 0x0c080000 0 0x80000>, /* GICR */
|
||||
<0 0x0c400000 0 0x2000>, /* GICC */
|
||||
<0 0x0c410000 0 0x1000>, /* GICH */
|
||||
<0 0x0c420000 0 0x2000>; /* GICV */
|
||||
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
topckgen: syscon@10000000 {
|
||||
compatible = "mediatek,mt8365-topckgen", "syscon";
|
||||
reg = <0 0x10000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
infracfg: syscon@10001000 {
|
||||
compatible = "mediatek,mt8365-infracfg", "syscon";
|
||||
reg = <0 0x10001000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pericfg: syscon@10003000 {
|
||||
compatible = "mediatek,mt8365-pericfg", "syscon";
|
||||
reg = <0 0x10003000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
syscfg_pctl: syscfg-pctl@10005000 {
|
||||
compatible = "mediatek,mt8365-syscfg", "syscon";
|
||||
reg = <0 0x10005000 0 0x1000>;
|
||||
};
|
||||
|
||||
pio: pinctrl@1000b000 {
|
||||
compatible = "mediatek,mt8365-pinctrl";
|
||||
reg = <0 0x1000b000 0 0x1000>;
|
||||
mediatek,pctl-regmap = <&syscfg_pctl>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
apmixedsys: syscon@1000c000 {
|
||||
compatible = "mediatek,mt8365-apmixedsys", "syscon";
|
||||
reg = <0 0x1000c000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pwrap: pwrap@1000d000 {
|
||||
compatible = "mediatek,mt8365-pwrap";
|
||||
reg = <0 0x1000d000 0 0x1000>;
|
||||
reg-names = "pwrap";
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
|
||||
<&infracfg CLK_IFR_PMIC_AP>,
|
||||
<&infracfg CLK_IFR_PWRAP_SYS>,
|
||||
<&infracfg CLK_IFR_PWRAP_TMR>;
|
||||
clock-names = "spi", "wrap", "sys", "tmr";
|
||||
};
|
||||
|
||||
keypad: keypad@10010000 {
|
||||
compatible = "mediatek,mt6779-keypad";
|
||||
reg = <0 0x10010000 0 0x1000>;
|
||||
wakeup-source;
|
||||
interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
|
||||
clocks = <&clk26m>;
|
||||
clock-names = "kpd";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcucfg: syscon@10200000 {
|
||||
compatible = "mediatek,mt8365-mcucfg", "syscon";
|
||||
reg = <0 0x10200000 0 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sysirq: interrupt-controller@10200a80 {
|
||||
compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
reg = <0 0x10200a80 0 0x20>;
|
||||
};
|
||||
|
||||
infracfg_nao: infracfg@1020e000 {
|
||||
compatible = "mediatek,mt8365-infracfg", "syscon";
|
||||
reg = <0 0x1020e000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
rng: rng@1020f000 {
|
||||
compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";
|
||||
reg = <0 0x1020f000 0 0x100>;
|
||||
clocks = <&infracfg CLK_IFR_TRNG>;
|
||||
clock-names = "rng";
|
||||
};
|
||||
|
||||
apdma: dma-controller@11000280 {
|
||||
compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";
|
||||
reg = <0 0x11000280 0 0x80>,
|
||||
<0 0x11000300 0 0x80>,
|
||||
<0 0x11000380 0 0x80>,
|
||||
<0 0x11000400 0 0x80>,
|
||||
<0 0x11000580 0 0x80>,
|
||||
<0 0x11000600 0 0x80>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
|
||||
dma-requests = <6>;
|
||||
clocks = <&infracfg CLK_IFR_AP_DMA>;
|
||||
clock-names = "apdma";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@11002000 {
|
||||
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
|
||||
reg = <0 0x11002000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
|
||||
clock-names = "baud", "bus";
|
||||
dmas = <&apdma 0>, <&apdma 1>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@11003000 {
|
||||
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
|
||||
reg = <0 0x11003000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
|
||||
clock-names = "baud", "bus";
|
||||
dmas = <&apdma 2>, <&apdma 3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@11004000 {
|
||||
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
|
||||
reg = <0 0x11004000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
|
||||
clock-names = "baud", "bus";
|
||||
dmas = <&apdma 4>, <&apdma 5>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm@11006000 {
|
||||
compatible = "mediatek,mt8365-pwm";
|
||||
reg = <0 0x11006000 0 0x1000>;
|
||||
#pwm-cells = <2>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infracfg CLK_IFR_PWM_HCLK>,
|
||||
<&infracfg CLK_IFR_PWM>,
|
||||
<&infracfg CLK_IFR_PWM1>,
|
||||
<&infracfg CLK_IFR_PWM2>,
|
||||
<&infracfg CLK_IFR_PWM3>;
|
||||
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
|
||||
};
|
||||
|
||||
i2c0: i2c@11007000 {
|
||||
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
|
||||
reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <1>;
|
||||
clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11008000 {
|
||||
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
|
||||
reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <1>;
|
||||
clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@11009000 {
|
||||
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
|
||||
reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <1>;
|
||||
clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi: spi@1100a000 {
|
||||
compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
|
||||
reg = <0 0x1100a000 0 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
|
||||
<&topckgen CLK_TOP_SPI_SEL>,
|
||||
<&infracfg CLK_IFR_SPI0>;
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@1100f000 {
|
||||
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
|
||||
reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <1>;
|
||||
clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssusb: usb@11201000 {
|
||||
compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
|
||||
reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
|
||||
reg-names = "mac", "ippc";
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
|
||||
phys = <&u2port0 PHY_TYPE_USB2>,
|
||||
<&u2port1 PHY_TYPE_USB2>;
|
||||
clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
|
||||
<&infracfg CLK_IFR_SSUSB_REF>,
|
||||
<&infracfg CLK_IFR_SSUSB_SYS>,
|
||||
<&infracfg CLK_IFR_ICUSB>;
|
||||
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
usb_host: usb@11200000 {
|
||||
compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";
|
||||
reg = <0 0x11200000 0 0x1000>;
|
||||
reg-names = "mac";
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
|
||||
<&infracfg CLK_IFR_SSUSB_REF>,
|
||||
<&infracfg CLK_IFR_SSUSB_SYS>,
|
||||
<&infracfg CLK_IFR_ICUSB>,
|
||||
<&infracfg CLK_IFR_SSUSB_XHCI>;
|
||||
clock-names = "sys_ck", "ref_ck", "mcu_ck",
|
||||
"dma_ck", "xhci_ck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
mmc0: mmc@11230000 {
|
||||
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
|
||||
reg = <0 0x11230000 0 0x1000>,
|
||||
<0 0x11cd0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
|
||||
<&infracfg CLK_IFR_MSDC0_HCLK>,
|
||||
<&infracfg CLK_IFR_MSDC0_SRC>;
|
||||
clock-names = "source", "hclk", "source_cg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc1: mmc@11240000 {
|
||||
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
|
||||
reg = <0 0x11240000 0 0x1000>,
|
||||
<0 0x11c90000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
|
||||
<&infracfg CLK_IFR_MSDC1_HCLK>,
|
||||
<&infracfg CLK_IFR_MSDC1_SRC>;
|
||||
clock-names = "source", "hclk", "source_cg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc2: mmc@11250000 {
|
||||
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
|
||||
reg = <0 0x11250000 0 0x1000>,
|
||||
<0 0x11c60000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
|
||||
<&infracfg CLK_IFR_MSDC2_HCLK>,
|
||||
<&infracfg CLK_IFR_MSDC2_SRC>,
|
||||
<&infracfg CLK_IFR_MSDC2_BK>,
|
||||
<&infracfg CLK_IFR_AP_MSDC0>;
|
||||
clock-names = "source", "hclk", "source_cg",
|
||||
"bus_clk", "sys_cg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet: ethernet@112a0000 {
|
||||
compatible = "mediatek,mt8365-eth";
|
||||
reg = <0 0x112a0000 0 0x1000>;
|
||||
mediatek,pericfg = <&infracfg>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_ETH_SEL>,
|
||||
<&infracfg CLK_IFR_NIC_AXI>,
|
||||
<&infracfg CLK_IFR_NIC_SLV_AXI>;
|
||||
clock-names = "core", "reg", "trans";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
u3phy: t-phy@11cc0000 {
|
||||
compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x11cc0000 0x9000>;
|
||||
|
||||
u2port0: usb-phy@0 {
|
||||
reg = <0x0 0x400>;
|
||||
clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
|
||||
<&topckgen CLK_TOP_USB20_48M_EN>;
|
||||
clock-names = "ref", "da_ref";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
u2port1: usb-phy@1000 {
|
||||
reg = <0x1000 0x400>;
|
||||
clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
|
||||
<&topckgen CLK_TOP_USB20_48M_EN>;
|
||||
clock-names = "ref", "da_ref";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
system_clk: dummy13m {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
systimer: timer@10017000 {
|
||||
compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
|
||||
reg = <0 0x10017000 0 0x100>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&system_clk>;
|
||||
clock-names = "clk13m";
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue