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OpenCloudOS-Kernel
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Merge branch 'next-samsung-devel' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/devel

This commit is contained in:
Arnd Bergmann 2011-07-21 16:34:00 +02:00
parent 4d09a93886 e8de616e39
commit 1e09939bad
91 changed files with 2718 additions and 1341 deletions
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8
arch/arm/Kconfig
View File

@ -684,6 +684,7 @@ config ARCH_S3C2410
select GENERIC_GPIO
select ARCH_HAS_CPUFREQ
select HAVE_CLK
select CLKDEV_LOOKUP
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C if I2C
help
@ -701,6 +702,7 @@ config ARCH_S3C64XX
select CPU_V6
select ARM_VIC
select HAVE_CLK
select CLKDEV_LOOKUP
select NO_IOPORT
select ARCH_USES_GETTIMEOFFSET
select ARCH_HAS_CPUFREQ
@ -725,6 +727,7 @@ config ARCH_S5P64X0
select CPU_V6
select GENERIC_GPIO
select HAVE_CLK
select CLKDEV_LOOKUP
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK
@ -738,6 +741,7 @@ config ARCH_S5PC100
bool "Samsung S5PC100"
select GENERIC_GPIO
select HAVE_CLK
select CLKDEV_LOOKUP
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
select ARCH_USES_GETTIMEOFFSET
@ -751,8 +755,10 @@ config ARCH_S5PV210
bool "Samsung S5PV210/S5PC110"
select CPU_V7
select ARCH_SPARSEMEM_ENABLE
select ARCH_HAS_HOLES_MEMORYMODEL
select GENERIC_GPIO
select HAVE_CLK
select CLKDEV_LOOKUP
select ARM_L1_CACHE_SHIFT_6
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
@ -767,8 +773,10 @@ config ARCH_EXYNOS4
bool "Samsung EXYNOS4"
select CPU_V7
select ARCH_SPARSEMEM_ENABLE
select ARCH_HAS_HOLES_MEMORYMODEL
select GENERIC_GPIO
select HAVE_CLK
select CLKDEV_LOOKUP
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select HAVE_S3C_RTC if RTC_CLASS

6
arch/arm/common/gic.c
View File

@ -38,12 +38,6 @@ static DEFINE_SPINLOCK(irq_controller_lock);
/* Address of GIC 0 CPU interface */
void __iomem *gic_cpu_base_addr __read_mostly;
struct gic_chip_data {
unsigned int irq_offset;
void __iomem *dist_base;
void __iomem *cpu_base;
};
/*
* Supported arch specific GIC irq extension.
* Default make them NULL.

6
arch/arm/include/asm/hardware/gic.h
View File

@ -41,6 +41,12 @@ void gic_secondary_init(unsigned int);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
void gic_enable_ppi(unsigned int);
struct gic_chip_data {
unsigned int irq_offset;
void __iomem *dist_base;
void __iomem *cpu_base;
};
#endif
#endif

30
arch/arm/mach-exynos4/Kconfig
View File

@ -16,7 +16,8 @@ config CPU_EXYNOS4210
Enable EXYNOS4210 CPU support
config EXYNOS4_MCT
bool "Kernel timer support by MCT"
bool
default y
help
Use MCT (Multi Core Timer) as kernel timers
@ -25,6 +26,11 @@ config EXYNOS4_DEV_AHCI
help
Compile in platform device definitions for AHCI
config EXYNOS4_SETUP_FIMD0
bool
help
Common setup code for FIMD0.
config EXYNOS4_DEV_PD
bool
help
@ -35,6 +41,11 @@ config EXYNOS4_DEV_SYSMMU
help
Common setup code for SYSTEM MMU in EXYNOS4
config EXYNOS4_DEV_DWMCI
bool
help
Compile in platform device definitions for DWMCI
config EXYNOS4_SETUP_I2C1
bool
help
@ -103,6 +114,7 @@ menu "EXYNOS4 Machines"
config MACH_SMDKC210
bool "SMDKC210"
select CPU_EXYNOS4210
select S5P_DEV_FIMD0
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
@ -112,6 +124,7 @@ config MACH_SMDKC210
select S3C_DEV_HSMMC3
select EXYNOS4_DEV_PD
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_SDHCI
help
@ -120,6 +133,7 @@ config MACH_SMDKC210
config MACH_SMDKV310
bool "SMDKV310"
select CPU_EXYNOS4210
select S5P_DEV_FIMD0
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
@ -127,9 +141,11 @@ config MACH_SMDKV310
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select EXYNOS4_DEV_AHCI
select SAMSUNG_DEV_KEYPAD
select EXYNOS4_DEV_PD
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_KEYPAD
select EXYNOS4_SETUP_SDHCI
@ -153,13 +169,22 @@ config MACH_ARMLEX4210
config MACH_UNIVERSAL_C210
bool "Mobile UNIVERSAL_C210 Board"
select CPU_EXYNOS4210
select S5P_GPIO_INT
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_FIMC3
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S3C_DEV_I2C1
select S3C_DEV_I2C3
select S3C_DEV_I2C5
select S5P_DEV_MFC
select S5P_DEV_ONENAND
select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
help
@ -176,13 +201,16 @@ config MACH_NURI
select S3C_DEV_I2C1
select S3C_DEV_I2C3
select S3C_DEV_I2C5
select S5P_DEV_MFC
select S5P_DEV_USB_EHCI
select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_ADC
help
Machine support for Samsung Mobile NURI Board.

11
arch/arm/mach-exynos4/Makefile
View File

@ -13,19 +13,14 @@ obj- :=
# Core support for EXYNOS4 system
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
ifeq ($(CONFIG_EXYNOS4_MCT),y)
obj-y += mct.o
else
obj-y += time.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
endif
obj-$(CONFIG_EXYNOS4_MCT) += mct.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
@ -43,8 +38,10 @@ obj-y += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o

238
arch/arm/mach-exynos4/clock.c
View File

@ -27,24 +27,20 @@
static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
.id = -1,
.rate = 27000000,
};
static struct clk clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy",
.id = -1,
};
static struct clk clk_sclk_usbphy0 = {
.name = "sclk_usbphy0",
.id = -1,
.rate = 27000000,
};
static struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1",
.id = -1,
};
static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
.id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_sclk_apll = {
.clk = {
.name = "sclk_apll",
.id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = {
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
.id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = {
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
.id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = {
static struct clksrc_clk clk_moutcore = {
.clk = {
.name = "moutcore",
.id = -1,
},
.sources = &clkset_moutcore,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = {
static struct clksrc_clk clk_coreclk = {
.clk = {
.name = "core_clk",
.id = -1,
.parent = &clk_moutcore.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = {
static struct clksrc_clk clk_armclk = {
.clk = {
.name = "armclk",
.id = -1,
.parent = &clk_coreclk.clk,
},
};
@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = {
static struct clksrc_clk clk_aclk_corem0 = {
.clk = {
.name = "aclk_corem0",
.id = -1,
.parent = &clk_coreclk.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = {
static struct clksrc_clk clk_aclk_cores = {
.clk = {
.name = "aclk_cores",
.id = -1,
.parent = &clk_coreclk.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = {
static struct clksrc_clk clk_aclk_corem1 = {
.clk = {
.name = "aclk_corem1",
.id = -1,
.parent = &clk_coreclk.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = {
static struct clksrc_clk clk_periphclk = {
.clk = {
.name = "periphclk",
.id = -1,
.parent = &clk_coreclk.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = {
static struct clksrc_clk clk_mout_corebus = {
.clk = {
.name = "mout_corebus",
.id = -1,
},
.sources = &clkset_mout_corebus,
.reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = {
static struct clksrc_clk clk_sclk_dmc = {
.clk = {
.name = "sclk_dmc",
.id = -1,
.parent = &clk_mout_corebus.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = {
static struct clksrc_clk clk_aclk_cored = {
.clk = {
.name = "aclk_cored",
.id = -1,
.parent = &clk_sclk_dmc.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = {
static struct clksrc_clk clk_aclk_corep = {
.clk = {
.name = "aclk_corep",
.id = -1,
.parent = &clk_aclk_cored.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = {
static struct clksrc_clk clk_aclk_acp = {
.clk = {
.name = "aclk_acp",
.id = -1,
.parent = &clk_mout_corebus.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = {
static struct clksrc_clk clk_pclk_acp = {
.clk = {
.name = "pclk_acp",
.id = -1,
.parent = &clk_aclk_acp.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = {
static struct clksrc_clk clk_aclk_200 = {
.clk = {
.name = "aclk_200",
.id = -1,
},
.sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = {
static struct clksrc_clk clk_aclk_100 = {
.clk = {
.name = "aclk_100",
.id = -1,
},
.sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = {
static struct clksrc_clk clk_aclk_160 = {
.clk = {
.name = "aclk_160",
.id = -1,
},
.sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = {
static struct clksrc_clk clk_aclk_133 = {
.clk = {
.name = "aclk_133",
.id = -1,
},
.sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = {
static struct clksrc_clk clk_vpllsrc = {
.clk = {
.name = "vpll_src",
.id = -1,
.enable = exynos4_clksrc_mask_top_ctrl,
.ctrlbit = (1 << 0),
},
@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
static struct clksrc_clk clk_sclk_vpll = {
.clk = {
.name = "sclk_vpll",
.id = -1,
},
.sources = &clkset_sclk_vpll,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
@ -398,161 +371,151 @@ static struct clksrc_clk clk_sclk_vpll = {
static struct clk init_clocks_off[] = {
{
.name = "timers",
.id = -1,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1<<24),
}, {
.name = "csis",
.id = 0,
.devname = "s5p-mipi-csis.0",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "csis",
.id = 1,
.devname = "s5p-mipi-csis.1",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "fimc",
.id = 0,
.devname = "exynos4-fimc.0",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "fimc",
.id = 1,
.devname = "exynos4-fimc.1",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "fimc",
.id = 2,
.devname = "exynos4-fimc.2",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "fimc",
.id = 3,
.devname = "exynos4-fimc.3",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "fimd",
.id = 0,
.devname = "exynos4-fb.0",
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "fimd",
.id = 1,
.devname = "exynos4-fb.1",
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "sataphy",
.id = -1,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "hsmmc",
.id = 0,
.devname = "s3c-sdhci.0",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "hsmmc",
.id = 1,
.devname = "s3c-sdhci.1",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
.id = 2,
.devname = "s3c-sdhci.2",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
.id = 3,
.devname = "s3c-sdhci.3",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "hsmmc",
.id = 4,
.name = "dwmmc",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "sata",
.id = -1,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "pdma",
.id = 0,
.devname = "s3c-pl330.0",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "pdma",
.id = 1,
.devname = "s3c-pl330.1",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "adc",
.id = -1,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "keypad",
.id = -1,
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "rtc",
.id = -1,
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = "usbhost",
.id = -1,
.enable = exynos4_clk_ip_fsys_ctrl ,
.ctrlbit = (1 << 12),
}, {
.name = "otg",
.id = -1,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "spi",
.id = 0,
.devname = "s3c64xx-spi.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "spi",
.id = 1,
.devname = "s3c64xx-spi.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
.id = 2,
.devname = "s3c64xx-spi.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "iis",
.id = 0,
.devname = "samsung-i2s.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "iis",
.id = 1,
.devname = "samsung-i2s.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "iis",
.id = 2,
.devname = "samsung-i2s.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 21),
}, {
@ -562,125 +525,115 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 27),
}, {
.name = "fimg2d",
.id = -1,
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "mfc",
.devname = "s5p-mfc",
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "i2c",
.id = 0,
.devname = "s3c2440-i2c.0",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "i2c",
.id = 1,
.devname = "s3c2440-i2c.1",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "i2c",
.id = 2,
.devname = "s3c2440-i2c.2",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "i2c",
.id = 3,
.devname = "s3c2440-i2c.3",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "i2c",
.id = 4,
.devname = "s3c2440-i2c.4",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "i2c",
.id = 5,
.devname = "s3c2440-i2c.5",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "i2c",
.id = 6,
.devname = "s3c2440-i2c.6",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
.id = 7,
.devname = "s3c2440-i2c.7",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "SYSMMU_MDMA",
.id = -1,
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "SYSMMU_FIMC0",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "SYSMMU_FIMC1",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "SYSMMU_FIMC2",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "SYSMMU_FIMC3",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "SYSMMU_JPEG",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "SYSMMU_FIMD0",
.id = -1,
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_FIMD1",
.id = -1,
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_PCIe",
.id = -1,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "SYSMMU_G2D",
.id = -1,
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "SYSMMU_ROTATOR",
.id = -1,
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_TV",
.id = -1,
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_MFC_L",
.id = -1,
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "SYSMMU_MFC_R",
.id = -1,
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2),
}
@ -689,32 +642,32 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "uart",
.id = 0,
.devname = "s5pv210-uart.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
.id = 1,
.devname = "s5pv210-uart.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.id = 2,
.devname = "s5pv210-uart.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
.id = 3,
.devname = "s5pv210-uart.3",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
.id = 4,
.devname = "s5pv210-uart.4",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "uart",
.id = 5,
.devname = "s5pv210-uart.5",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 5),
}
@ -750,7 +703,6 @@ static struct clksrc_sources clkset_mout_g2d0 = {
static struct clksrc_clk clk_mout_g2d0 = {
.clk = {
.name = "mout_g2d0",
.id = -1,
},
.sources = &clkset_mout_g2d0,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
@ -769,7 +721,6 @@ static struct clksrc_sources clkset_mout_g2d1 = {
static struct clksrc_clk clk_mout_g2d1 = {
.clk = {
.name = "mout_g2d1",
.id = -1,
},
.sources = &clkset_mout_g2d1,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
@ -785,10 +736,55 @@ static struct clksrc_sources clkset_mout_g2d = {
.nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
};
static struct clk *clkset_mout_mfc0_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_sclk_apll.clk,
};
static struct clksrc_sources clkset_mout_mfc0 = {
.sources = clkset_mout_mfc0_list,
.nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
};
static struct clksrc_clk clk_mout_mfc0 = {
.clk = {
.name = "mout_mfc0",
},
.sources = &clkset_mout_mfc0,
.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
};
static struct clk *clkset_mout_mfc1_list[] = {
[0] = &clk_mout_epll.clk,
[1] = &clk_sclk_vpll.clk,
};
static struct clksrc_sources clkset_mout_mfc1 = {
.sources = clkset_mout_mfc1_list,
.nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
};
static struct clksrc_clk clk_mout_mfc1 = {
.clk = {
.name = "mout_mfc1",
},
.sources = &clkset_mout_mfc1,
.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
};
static struct clk *clkset_mout_mfc_list[] = {
[0] = &clk_mout_mfc0.clk,
[1] = &clk_mout_mfc1.clk,
};
static struct clksrc_sources clkset_mout_mfc = {
.sources = clkset_mout_mfc_list,
.nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
};
static struct clksrc_clk clk_dout_mmc0 = {
.clk = {
.name = "dout_mmc0",
.id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
@ -798,7 +794,6 @@ static struct clksrc_clk clk_dout_mmc0 = {
static struct clksrc_clk clk_dout_mmc1 = {
.clk = {
.name = "dout_mmc1",
.id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
@ -808,7 +803,6 @@ static struct clksrc_clk clk_dout_mmc1 = {
static struct clksrc_clk clk_dout_mmc2 = {
.clk = {
.name = "dout_mmc2",
.id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
@ -818,7 +812,6 @@ static struct clksrc_clk clk_dout_mmc2 = {
static struct clksrc_clk clk_dout_mmc3 = {
.clk = {
.name = "dout_mmc3",
.id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
@ -828,7 +821,6 @@ static struct clksrc_clk clk_dout_mmc3 = {
static struct clksrc_clk clk_dout_mmc4 = {
.clk = {
.name = "dout_mmc4",
.id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
@ -839,7 +831,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "uclk1",
.id = 0,
.devname = "s5pv210-uart.0",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0),
},
@ -849,7 +841,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
.id = 1,
.devname = "s5pv210-uart.1",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 4),
},
@ -859,7 +851,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
.id = 2,
.devname = "s5pv210-uart.2",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 8),
},
@ -869,7 +861,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
.id = 3,
.devname = "s5pv210-uart.3",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 12),
},
@ -879,7 +871,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_pwm",
.id = -1,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 24),
},
@ -889,7 +880,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_csis",
.id = 0,
.devname = "s5p-mipi-csis.0",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 24),
},
@ -899,7 +890,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_csis",
.id = 1,
.devname = "s5p-mipi-csis.1",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 28),
},
@ -909,7 +900,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
.id = 0,
.devname = "exynos4-fimc.0",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 16),
},
@ -919,7 +910,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
.id = 1,
.devname = "exynos4-fimc.1",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 20),
},
@ -929,7 +920,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
.id = 0,
.devname = "exynos4-fimc.0",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 0),
},
@ -939,7 +930,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
.id = 1,
.devname = "exynos4-fimc.1",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 4),
},
@ -949,7 +940,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
.id = 2,
.devname = "exynos4-fimc.2",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 8),
},
@ -959,7 +950,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
.id = 3,
.devname = "exynos4-fimc.3",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 12),
},
@ -969,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
.id = 0,
.devname = "exynos4-fb.0",
.enable = exynos4_clksrc_mask_lcd0_ctrl,
.ctrlbit = (1 << 0),
},
@ -979,7 +970,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
.id = 1,
.devname = "exynos4-fb.1",
.enable = exynos4_clksrc_mask_lcd1_ctrl,
.ctrlbit = (1 << 0),
},
@ -989,7 +980,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_sata",
.id = -1,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 24),
},
@ -999,7 +989,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
.id = 0,
.devname = "s3c64xx-spi.0",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
},
@ -1009,7 +999,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
.id = 1,
.devname = "s3c64xx-spi.1",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
},
@ -1019,7 +1009,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
.id = 2,
.devname = "s3c64xx-spi.2",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
},
@ -1029,15 +1019,22 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimg2d",
.id = -1,
},
.sources = &clkset_mout_g2d,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_mfc",
.devname = "s5p-mfc",
},
.sources = &clkset_mout_mfc,
.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
.id = 0,
.devname = "s3c-sdhci.0",
.parent = &clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0),
@ -1046,7 +1043,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 1,
.devname = "s3c-sdhci.1",
.parent = &clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4),
@ -1055,7 +1052,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 2,
.devname = "s3c-sdhci.2",
.parent = &clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8),
@ -1064,7 +1061,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 3,
.devname = "s3c-sdhci.3",
.parent = &clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12),
@ -1072,8 +1069,7 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
}, {
.clk = {
.name = "sclk_mmc",
.id = 4,
.name = "sclk_dwmmc",
.parent = &clk_dout_mmc4.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 16),
@ -1112,6 +1108,8 @@ static struct clksrc_clk *sysclks[] = {
&clk_dout_mmc2,
&clk_dout_mmc3,
&clk_dout_mmc4,
&clk_mout_mfc0,
&clk_mout_mfc1,
};
static int xtal_rate;

39
arch/arm/mach-exynos4/cpu.c
View File

@ -16,12 +16,16 @@
#include <asm/proc-fns.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/exynos4.h>
#include <plat/adc-core.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
#include <plat/fb-core.h>
#include <plat/fimc-core.h>
#include <plat/iic-core.h>
@ -103,7 +107,17 @@ static struct map_desc exynos4_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
.length = SZ_4K,
.type = MT_DEVICE,
}
}, {
.virtual = (unsigned long)S5P_VA_GIC_CPU,
.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_DIST,
.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
.length = SZ_64K,
.type = MT_DEVICE,
},
};
static void exynos4_idle(void)
@ -129,6 +143,8 @@ void __init exynos4_map_io(void)
exynos4_default_sdhci2();
exynos4_default_sdhci3();
s3c_adc_setname("samsung-adc-v3");
s3c_fimc_setname(0, "exynos4-fimc");
s3c_fimc_setname(1, "exynos4-fimc");
s3c_fimc_setname(2, "exynos4-fimc");
@ -138,6 +154,8 @@ void __init exynos4_map_io(void)
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_i2c2_setname("s3c2440-i2c");
s5p_fb_setname(0, "exynos4-fb");
}
void __init exynos4_init_clocks(int xtal)
@ -150,22 +168,23 @@ void __init exynos4_init_clocks(int xtal)
exynos4_setup_clocks();
}
static void exynos4_gic_irq_eoi(struct irq_data *d)
{
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
gic_data->cpu_base = S5P_VA_GIC_CPU +
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
}
void __init exynos4_init_irq(void)
{
int irq;
gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
/*
* From SPI(0) to SPI(39) and SPI(51), SPI(53) are
* connected to the interrupt combiner. These irqs
* should be initialized to support cascade interrupt.
*/
if ((irq >= 40) && !(irq == 51) && !(irq == 53))
continue;
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));

2
arch/arm/mach-exynos4/dev-audio.c
View File

@ -21,6 +21,7 @@
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
#include <mach/regs-audss.h>
static const char *rclksrc[] = {
[0] = "busclk",
@ -55,6 +56,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
| QUIRK_NEED_RSTCLR,
.src_clk = rclksrc,
.idma_addr = EXYNOS4_AUDSS_INT_MEM,
},
},
};

82
arch/arm/mach-exynos4/dev-dwmci.c Normal file
View File

@ -0,0 +1,82 @@
/*
* linux/arch/arm/mach-exynos4/dev-dwmci.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Platform device for Synopsys DesignWare Mobile Storage IP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/mmc/dw_mmc.h>
#include <plat/devs.h>
#include <mach/map.h>
static int exynos4_dwmci_get_bus_wd(u32 slot_id)
{
return 4;
}
static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
{
return 0;
}
static struct resource exynos4_dwmci_resource[] = {
[0] = {
.start = EXYNOS4_PA_DWMCI,
.end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DWMCI,
.end = IRQ_DWMCI,
.flags = IORESOURCE_IRQ,
}
};
static struct dw_mci_board exynos4_dwci_pdata = {
.num_slots = 1,
.quirks = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
.bus_hz = 80 * 1000 * 1000,
.detect_delay_ms = 200,
.init = exynos4_dwmci_init,
.get_bus_wd = exynos4_dwmci_get_bus_wd,
};
static u64 exynos4_dwmci_dmamask = DMA_BIT_MASK(32);
struct platform_device exynos4_device_dwmci = {
.name = "dw_mmc",
.id = -1,
.num_resources = ARRAY_SIZE(exynos4_dwmci_resource),
.resource = exynos4_dwmci_resource,
.dev = {
.dma_mask = &exynos4_dwmci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &exynos4_dwci_pdata,
},
};
void __init exynos4_dwmci_set_platdata(struct dw_mci_board *pd)
{
struct dw_mci_board *npd;
npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
&exynos4_device_dwmci);
if (!npd->init)
npd->init = exynos4_dwmci_init;
if (!npd->get_bus_wd)
npd->get_bus_wd = exynos4_dwmci_get_bus_wd;
}

13
arch/arm/mach-exynos4/hotplug.c
View File

@ -13,9 +13,12 @@
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include <mach/regs-pmu.h>
extern volatile int pen_release;
static inline void cpu_enter_lowpower(void)
@ -58,12 +61,12 @@ static inline void cpu_leave_lowpower(void)
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
{
/*
* there is no power-control hardware on this platform, so all
* we can do is put the core into WFI; this is safe as the calling
* code will have already disabled interrupts
*/
for (;;) {
/* make cpu1 to be turned off at next WFI command */
if (cpu == 1)
__raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
/*
* here's the WFI
*/

7
arch/arm/mach-exynos4/include/mach/clkdev.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

20
arch/arm/mach-exynos4/include/mach/dwmci.h Normal file
View File

@ -0,0 +1,20 @@
/* linux/arch/arm/mach-exynos4/include/mach/dwmci.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Synopsys DesignWare Mobile Storage for EXYNOS4210
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_ARCH_DWMCI_H
#define __ASM_ARM_ARCH_DWMCI_H __FILE__
#include <linux/mmc/dw_mmc.h>
extern void exynos4_dwmci_set_platdata(struct dw_mci_board *pd);
#endif /* __ASM_ARM_ARCH_DWMCI_H */

11
arch/arm/mach-exynos4/include/mach/entry-macro.S
View File

@ -10,6 +10,7 @@
*/
#include <mach/hardware.h>
#include <mach/map.h>
#include <asm/hardware/gic.h>
.macro disable_fiq
@ -18,6 +19,10 @@
.macro get_irqnr_preamble, base, tmp
ldr \base, =gic_cpu_base_addr
ldr \base, [\base]
mrc p15, 0, \tmp, c0, c0, 5
and \tmp, \tmp, #3
cmp \tmp, #1
addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET
.endm
.macro arch_ret_to_user, tmp1, tmp2
@ -75,10 +80,4 @@
/* As above, this assumes that irqstat and base are preserved.. */
.macro test_for_ltirq, irqnr, irqstat, base, tmp
bic \irqnr, \irqstat, #0x1c00
mov \tmp, #0
cmp \irqnr, #29
moveq \tmp, #1
streq \irqstat, [\base, #GIC_CPU_EOI]
cmp \tmp, #0
.endm

194
arch/arm/mach-exynos4/include/mach/irqs.h
View File

@ -19,40 +19,105 @@
#define IRQ_PPI(x) S5P_IRQ(x+16)
#define IRQ_LOCALTIMER IRQ_PPI(13)
/* SPI: Shared Peripheral Interrupt */
#define IRQ_SPI(x) S5P_IRQ(x+32)
#define IRQ_MCT1 IRQ_SPI(35)
#define IRQ_EINT0 IRQ_SPI(16)
#define IRQ_EINT1 IRQ_SPI(17)
#define IRQ_EINT2 IRQ_SPI(18)
#define IRQ_EINT3 IRQ_SPI(19)
#define IRQ_EINT4 IRQ_SPI(20)
#define IRQ_EINT5 IRQ_SPI(21)
#define IRQ_EINT6 IRQ_SPI(22)
#define IRQ_EINT7 IRQ_SPI(23)
#define IRQ_EINT8 IRQ_SPI(24)
#define IRQ_EINT9 IRQ_SPI(25)
#define IRQ_EINT10 IRQ_SPI(26)
#define IRQ_EINT11 IRQ_SPI(27)
#define IRQ_EINT12 IRQ_SPI(28)
#define IRQ_EINT13 IRQ_SPI(29)
#define IRQ_EINT14 IRQ_SPI(30)
#define IRQ_EINT15 IRQ_SPI(31)
#define IRQ_EINT16_31 IRQ_SPI(32)
#define IRQ_EINT0 IRQ_SPI(40)
#define IRQ_EINT1 IRQ_SPI(41)
#define IRQ_EINT2 IRQ_SPI(42)
#define IRQ_EINT3 IRQ_SPI(43)
#define IRQ_USB_HSOTG IRQ_SPI(44)
#define IRQ_USB_HOST IRQ_SPI(45)
#define IRQ_MODEM_IF IRQ_SPI(46)
#define IRQ_ROTATOR IRQ_SPI(47)
#define IRQ_JPEG IRQ_SPI(48)
#define IRQ_2D IRQ_SPI(49)
#define IRQ_PCIE IRQ_SPI(50)
#define IRQ_MCT0 IRQ_SPI(51)
#define IRQ_MFC IRQ_SPI(52)
#define IRQ_AUDIO_SS IRQ_SPI(54)
#define IRQ_AC97 IRQ_SPI(55)
#define IRQ_SPDIF IRQ_SPI(56)
#define IRQ_KEYPAD IRQ_SPI(57)
#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(58)
#define IRQ_SLIMBUS IRQ_SPI(59)
#define IRQ_PMU IRQ_SPI(60)
#define IRQ_TSI IRQ_SPI(61)
#define IRQ_SATA IRQ_SPI(62)
#define IRQ_GPS IRQ_SPI(63)
#define IRQ_PDMA0 IRQ_SPI(35)
#define IRQ_PDMA1 IRQ_SPI(36)
#define IRQ_TIMER0_VIC IRQ_SPI(37)
#define IRQ_TIMER1_VIC IRQ_SPI(38)
#define IRQ_TIMER2_VIC IRQ_SPI(39)
#define IRQ_TIMER3_VIC IRQ_SPI(40)
#define IRQ_TIMER4_VIC IRQ_SPI(41)
#define IRQ_MCT_L0 IRQ_SPI(42)
#define IRQ_WDT IRQ_SPI(43)
#define IRQ_RTC_ALARM IRQ_SPI(44)
#define IRQ_RTC_TIC IRQ_SPI(45)
#define IRQ_GPIO_XB IRQ_SPI(46)
#define IRQ_GPIO_XA IRQ_SPI(47)
#define IRQ_MCT_L1 IRQ_SPI(48)
#define IRQ_UART0 IRQ_SPI(52)
#define IRQ_UART1 IRQ_SPI(53)
#define IRQ_UART2 IRQ_SPI(54)
#define IRQ_UART3 IRQ_SPI(55)
#define IRQ_UART4 IRQ_SPI(56)
#define IRQ_MCT_G0 IRQ_SPI(57)
#define IRQ_IIC IRQ_SPI(58)
#define IRQ_IIC1 IRQ_SPI(59)
#define IRQ_IIC2 IRQ_SPI(60)
#define IRQ_IIC3 IRQ_SPI(61)
#define IRQ_IIC4 IRQ_SPI(62)
#define IRQ_IIC5 IRQ_SPI(63)
#define IRQ_IIC6 IRQ_SPI(64)
#define IRQ_IIC7 IRQ_SPI(65)
#define IRQ_USB_HOST IRQ_SPI(70)
#define IRQ_USB_HSOTG IRQ_SPI(71)
#define IRQ_MODEM_IF IRQ_SPI(72)
#define IRQ_HSMMC0 IRQ_SPI(73)
#define IRQ_HSMMC1 IRQ_SPI(74)
#define IRQ_HSMMC2 IRQ_SPI(75)
#define IRQ_HSMMC3 IRQ_SPI(76)
#define IRQ_DWMCI IRQ_SPI(77)
#define IRQ_MIPICSI0 IRQ_SPI(78)
#define IRQ_MIPICSI1 IRQ_SPI(80)
#define IRQ_ONENAND_AUDI IRQ_SPI(82)
#define IRQ_ROTATOR IRQ_SPI(83)
#define IRQ_FIMC0 IRQ_SPI(84)
#define IRQ_FIMC1 IRQ_SPI(85)
#define IRQ_FIMC2 IRQ_SPI(86)
#define IRQ_FIMC3 IRQ_SPI(87)
#define IRQ_JPEG IRQ_SPI(88)
#define IRQ_2D IRQ_SPI(89)
#define IRQ_PCIE IRQ_SPI(90)
#define IRQ_MFC IRQ_SPI(94)
#define IRQ_AUDIO_SS IRQ_SPI(96)
#define IRQ_I2S0 IRQ_SPI(97)
#define IRQ_I2S1 IRQ_SPI(98)
#define IRQ_I2S2 IRQ_SPI(99)
#define IRQ_AC97 IRQ_SPI(100)
#define IRQ_SPDIF IRQ_SPI(104)
#define IRQ_ADC0 IRQ_SPI(105)
#define IRQ_PEN0 IRQ_SPI(106)
#define IRQ_ADC1 IRQ_SPI(107)
#define IRQ_PEN1 IRQ_SPI(108)
#define IRQ_KEYPAD IRQ_SPI(109)
#define IRQ_PMU IRQ_SPI(110)
#define IRQ_GPS IRQ_SPI(111)
#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
#define IRQ_SLIMBUS IRQ_SPI(113)
#define IRQ_TSI IRQ_SPI(115)
#define IRQ_SATA IRQ_SPI(116)
#define MAX_IRQ_IN_COMBINER 8
#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64))
#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
@ -73,75 +138,14 @@
#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
#define IRQ_PDMA0 COMBINER_IRQ(21, 0)
#define IRQ_PDMA1 COMBINER_IRQ(21, 1)
#define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
#define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
#define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
#define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0)
#define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1)
#define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2)
#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3)
#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4)
#define MAX_COMBINER_NR 16
#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
#define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
#define IRQ_GPIO_XB COMBINER_IRQ(24, 0)
#define IRQ_GPIO_XA COMBINER_IRQ(24, 1)
#define IRQ_UART0 COMBINER_IRQ(26, 0)
#define IRQ_UART1 COMBINER_IRQ(26, 1)
#define IRQ_UART2 COMBINER_IRQ(26, 2)
#define IRQ_UART3 COMBINER_IRQ(26, 3)
#define IRQ_UART4 COMBINER_IRQ(26, 4)
#define IRQ_IIC COMBINER_IRQ(27, 0)
#define IRQ_IIC1 COMBINER_IRQ(27, 1)
#define IRQ_IIC2 COMBINER_IRQ(27, 2)
#define IRQ_IIC3 COMBINER_IRQ(27, 3)
#define IRQ_IIC4 COMBINER_IRQ(27, 4)
#define IRQ_IIC5 COMBINER_IRQ(27, 5)
#define IRQ_IIC6 COMBINER_IRQ(27, 6)
#define IRQ_IIC7 COMBINER_IRQ(27, 7)
#define IRQ_HSMMC0 COMBINER_IRQ(29, 0)
#define IRQ_HSMMC1 COMBINER_IRQ(29, 1)
#define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
#define IRQ_HSMMC3 COMBINER_IRQ(29, 3)
#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
#define IRQ_FIMC0 COMBINER_IRQ(32, 0)
#define IRQ_FIMC1 COMBINER_IRQ(32, 1)
#define IRQ_FIMC2 COMBINER_IRQ(33, 0)
#define IRQ_FIMC3 COMBINER_IRQ(33, 1)
#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
#define IRQ_EINT4 COMBINER_IRQ(37, 0)
#define IRQ_EINT5 COMBINER_IRQ(37, 1)
#define IRQ_EINT6 COMBINER_IRQ(37, 2)
#define IRQ_EINT7 COMBINER_IRQ(37, 3)
#define IRQ_EINT8 COMBINER_IRQ(38, 0)
#define IRQ_EINT9 COMBINER_IRQ(38, 1)
#define IRQ_EINT10 COMBINER_IRQ(38, 2)
#define IRQ_EINT11 COMBINER_IRQ(38, 3)
#define IRQ_EINT12 COMBINER_IRQ(38, 4)
#define IRQ_EINT13 COMBINER_IRQ(38, 5)
#define IRQ_EINT14 COMBINER_IRQ(38, 6)
#define IRQ_EINT15 COMBINER_IRQ(38, 7)
#define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
#define IRQ_WDT COMBINER_IRQ(53, 0)
#define IRQ_MCT_G0 COMBINER_IRQ(53, 4)
#define MAX_COMBINER_NR 54
#define IRQ_ADC IRQ_ADC0
#define IRQ_TC IRQ_PEN0
#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
@ -155,6 +159,6 @@
#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
/* Set the default NR_IRQS */
#define NR_IRQS (IRQ_GPIO_END)
#define NR_IRQS (IRQ_GPIO_END + 64)
#endif /* __ASM_ARCH_IRQS_H */

19
arch/arm/mach-exynos4/include/mach/map.h
View File

@ -57,12 +57,14 @@
#define EXYNOS4_PA_DMC0 0x10400000
#define EXYNOS4_PA_COMBINER 0x10448000
#define EXYNOS4_PA_COMBINER 0x10440000
#define EXYNOS4_PA_GIC_CPU 0x10480000
#define EXYNOS4_PA_GIC_DIST 0x10490000
#define EXYNOS4_GIC_BANK_OFFSET 0x8000
#define EXYNOS4_PA_COREPERI 0x10500000
#define EXYNOS4_PA_GIC_CPU 0x10500100
#define EXYNOS4_PA_TWD 0x10500600
#define EXYNOS4_PA_GIC_DIST 0x10501000
#define EXYNOS4_PA_L2CC 0x10502000
#define EXYNOS4_PA_MDMA 0x10810000
@ -93,7 +95,10 @@
#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
#define EXYNOS4_PA_FIMD0 0x11C00000
#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define EXYNOS4_PA_DWMCI 0x12550000
#define EXYNOS4_PA_SATA 0x12560000
#define EXYNOS4_PA_SATAPHY 0x125D0000
@ -103,11 +108,15 @@
#define EXYNOS4_PA_EHCI 0x12580000
#define EXYNOS4_PA_HSPHY 0x125B0000
#define EXYNOS4_PA_MFC 0x13400000
#define EXYNOS4_PA_UART 0x13800000
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
#define EXYNOS4_PA_ADC 0x13910000
#define EXYNOS4_PA_ADC1 0x13911000
#define EXYNOS4_PA_AC97 0x139A0000
#define EXYNOS4_PA_SPDIF 0x139B0000
@ -130,6 +139,8 @@
#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
#define S3C_PA_RTC EXYNOS4_PA_RTC
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
@ -140,10 +151,12 @@
#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
#define S5P_PA_SROMC EXYNOS4_PA_SROMC
#define S5P_PA_MFC EXYNOS4_PA_MFC
#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
#define S5P_PA_TIMER EXYNOS4_PA_TIMER
#define S5P_PA_EHCI EXYNOS4_PA_EHCI

10
arch/arm/mach-exynos4/include/mach/pm-core.h
View File

@ -47,3 +47,13 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
{
/* nothing here yet */
}
static inline void s3c_pm_restored_gpios(void)
{
/* nothing here yet */
}
static inline void s3c_pm_saved_gpios(void)
{
/* nothing here yet */
}

25
arch/arm/mach-exynos4/include/mach/pmu.h Normal file
View File

@ -0,0 +1,25 @@
/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS4210 - PMU(Power Management Unit) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PMU_H
#define __ASM_ARCH_PMU_H __FILE__
enum sys_powerdown {
SYS_AFTR,
SYS_LPA,
SYS_SLEEP,
NUM_SYS_POWERDOWN,
};
extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
#endif /* __ASM_ARCH_PMU_H */

18
arch/arm/mach-exynos4/include/mach/regs-audss.h Normal file
View File

@ -0,0 +1,18 @@
/* arch/arm/mach-exynos4/include/mach/regs-audss.h
*
* Copyright (c) 2011 Samsung Electronics
* http://www.samsung.com
*
* Exynos4 Audio SubSystem clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_AUDSS_H
#define __PLAT_REGS_AUDSS_H __FILE__
#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
#endif /* _PLAT_REGS_AUDSS_H */

12
arch/arm/mach-exynos4/include/mach/regs-clock.h
View File

@ -25,6 +25,9 @@
#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
@ -33,7 +36,9 @@
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224)
#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
@ -61,6 +66,7 @@
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
@ -120,6 +126,12 @@
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
#define S5P_EPLLCON0_ENABLE_SHIFT (31)
#define S5P_EPLLCON0_LOCKED_SHIFT (29)
#define S5P_VPLLCON0_ENABLE_SHIFT (31)
#define S5P_VPLLCON0_LOCKED_SHIFT (29)
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)

1
arch/arm/mach-exynos4/include/mach/regs-pmu.h
View File

@ -158,6 +158,7 @@
#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
#define S5P_CORE_LOCAL_PWR_EN 0x3
#define S5P_INT_LOCAL_PWR_EN 0x7
#define S5P_CHECK_SLEEP 0x00000BAD

26
arch/arm/mach-exynos4/localtimer.c
View File

@ -1,26 +0,0 @@
/* linux/arch/arm/mach-exynos4/localtimer.c
*
* Cloned from linux/arch/arm/mach-realview/localtimer.c
*
* Copyright (C) 2002 ARM Ltd.
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clockchips.h>
#include <asm/irq.h>
#include <asm/localtimer.h>
/*
* Setup the local clock events for a CPU.
*/
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
evt->irq = IRQ_LOCALTIMER;
twd_timer_setup(evt);
return 0;
}

757
arch/arm/mach-exynos4/mach-nuri.c
View File

@ -13,10 +13,15 @@
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/i2c/atmel_mxt_ts.h>
#include <linux/i2c-gpio.h>
#include <linux/gpio_keys.h>
#include <linux/gpio.h>
#include <linux/power/max8903_charger.h>
#include <linux/power/max17042_battery.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/mfd/max8997.h>
#include <linux/mfd/max8997-private.h>
#include <linux/mmc/host.h>
#include <linux/fb.h>
#include <linux/pwm_backlight.h>
@ -26,6 +31,7 @@
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <plat/adc.h>
#include <plat/regs-serial.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
@ -35,6 +41,8 @@
#include <plat/clock.h>
#include <plat/gpio-cfg.h>
#include <plat/iic.h>
#include <plat/mfc.h>
#include <plat/pd.h>
#include <mach/map.h>
@ -54,6 +62,7 @@
enum fixed_regulator_id {
FIXED_REG_ID_MMC = 0,
FIXED_REG_ID_MAX8903,
};
static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
@ -344,10 +353,730 @@ static void __init nuri_tsp_init(void)
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
}
/* GPIO I2C 5 (PMIC) */
static struct i2c_board_info i2c5_devs[] __initdata = {
/* max8997, To be updated */
static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */
};
static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
};
static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
};
static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
};
static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
};
static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
REGULATOR_SUPPLY("vusb_d", NULL), /* Used by CPU */
REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */
};
static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */
};
static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
};
static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
};
static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
};
static struct regulator_consumer_supply __initdata max8997_ldo15_[] = {
REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */
};
static struct regulator_consumer_supply __initdata max8997_ldo16_[] = {
REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */
};
static struct regulator_consumer_supply __initdata max8997_ldo18_[] = {
REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */
};
static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
};
static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
};
static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
};
static struct regulator_consumer_supply __initdata max8997_buck4_[] = {
REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */
};
static struct regulator_consumer_supply __initdata max8997_buck6_[] = {
REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */
};
static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = {
REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */
};
static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = {
REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */
};
static struct regulator_consumer_supply __initdata max8997_charger_[] = {
REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
};
static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = {
REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */
};
static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = {
REGULATOR_SUPPLY("gps_clk", "bcm4751"),
REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"),
REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"),
};
static struct regulator_init_data __initdata max8997_ldo1_data = {
.constraints = {
.name = "VADC_3.3V_C210",
.min_uV = 3300000,
.max_uV = 3300000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_ldo1_),
.consumer_supplies = max8997_ldo1_,
};
static struct regulator_init_data __initdata max8997_ldo2_data = {
.constraints = {
.name = "VALIVE_1.1V_C210",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_ldo3_data = {
.constraints = {
.name = "VUSB_1.1V_C210",
.min_uV = 1100000,
.max_uV = 1100000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_ldo3_),
.consumer_supplies = max8997_ldo3_,
};
static struct regulator_init_data __initdata max8997_ldo4_data = {
.constraints = {
.name = "VMIPI_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_ldo4_),
.consumer_supplies = max8997_ldo4_,
};
static struct regulator_init_data __initdata max8997_ldo5_data = {
.constraints = {
.name = "VHSIC_1.2V_C210",
.min_uV = 1200000,
.max_uV = 1200000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_ldo5_),
.consumer_supplies = max8997_ldo5_,
};
static struct regulator_init_data __initdata max8997_ldo6_data = {
.constraints = {
.name = "VCC_1.8V_PDA",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_ldo7_data = {
.constraints = {
.name = "CAM_ISP_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_ldo7_),
.consumer_supplies = max8997_ldo7_,
};
static struct regulator_init_data __initdata max8997_ldo8_data = {
.constraints = {
.name = "VUSB/VDAC_3.3V_C210",
.min_uV = 3300000,
.max_uV = 3300000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_ldo8_),
.consumer_supplies = max8997_ldo8_,
};
static struct regulator_init_data __initdata max8997_ldo9_data = {
.constraints = {
.name = "VCC_2.8V_PDA",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_ldo10_data = {
.constraints = {
.name = "VPLL_1.1V_C210",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_ldo11_data = {
.constraints = {
.name = "LVDS_VDD3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
.boot_on = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_ldo11_),
.consumer_supplies = max8997_ldo11_,
};
static struct regulator_init_data __initdata max8997_ldo12_data = {
.constraints = {
.name = "VT_CAM_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_ldo12_),
.consumer_supplies = max8997_ldo12_,
};
static struct regulator_init_data __initdata max8997_ldo13_data = {
.constraints = {
.name = "VTF_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_ldo13_),
.consumer_supplies = max8997_ldo13_,
};
static struct regulator_init_data __initdata max8997_ldo14_data = {
.constraints = {
.name = "VCC_3.0V_MOTOR",
.min_uV = 3000000,
.max_uV = 3000000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_ldo14_),
.consumer_supplies = max8997_ldo14_,
};
static struct regulator_init_data __initdata max8997_ldo15_data = {
.constraints = {
.name = "VTOUCH_ADVV2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_ldo15_),
.consumer_supplies = max8997_ldo15_,
};
static struct regulator_init_data __initdata max8997_ldo16_data = {
.constraints = {
.name = "CAM_SENSOR_IO_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_ldo16_),
.consumer_supplies = max8997_ldo16_,
};
static struct regulator_init_data __initdata max8997_ldo18_data = {
.constraints = {
.name = "VTOUCH_VDD2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_ldo18_),
.consumer_supplies = max8997_ldo18_,
};
static struct regulator_init_data __initdata max8997_ldo21_data = {
.constraints = {
.name = "VDDQ_M1M2_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_buck1_data = {
.constraints = {
.name = "VARM_1.2V_C210",
.min_uV = 900000,
.max_uV = 1350000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_buck1_),
.consumer_supplies = max8997_buck1_,
};
static struct regulator_init_data __initdata max8997_buck2_data = {
.constraints = {
.name = "VINT_1.1V_C210",
.min_uV = 900000,
.max_uV = 1100000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_buck2_),
.consumer_supplies = max8997_buck2_,
};
static struct regulator_init_data __initdata max8997_buck3_data = {
.constraints = {
.name = "VG3D_1.1V_C210",
.min_uV = 900000,
.max_uV = 1100000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_buck3_),
.consumer_supplies = max8997_buck3_,
};
static struct regulator_init_data __initdata max8997_buck4_data = {
.constraints = {
.name = "CAM_ISP_CORE_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_buck4_),
.consumer_supplies = max8997_buck4_,
};
static struct regulator_init_data __initdata max8997_buck5_data = {
.constraints = {
.name = "VMEM_1.2V_C210",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_buck6_data = {
.constraints = {
.name = "CAM_AF_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_buck6_),
.consumer_supplies = max8997_buck6_,
};
static struct regulator_init_data __initdata max8997_buck7_data = {
.constraints = {
.name = "VCC_SUB_2.0V",
.min_uV = 2000000,
.max_uV = 2000000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_32khz_ap_data = {
.constraints = {
.name = "32KHz AP",
.always_on = 1,
.state_mem = {
.enabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_),
.consumer_supplies = max8997_32khz_ap_,
};
static struct regulator_init_data __initdata max8997_32khz_cp_data = {
.constraints = {
.name = "32KHz CP",
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_vichg_data = {
.constraints = {
.name = "VICHG",
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data __initdata max8997_esafeout1_data = {
.constraints = {
.name = "SAFEOUT1",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_esafeout1_),
.consumer_supplies = max8997_esafeout1_,
};
static struct regulator_init_data __initdata max8997_esafeout2_data = {
.constraints = {
.name = "SAFEOUT2",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(max8997_esafeout2_),
.consumer_supplies = max8997_esafeout2_,
};
static struct regulator_init_data __initdata max8997_charger_cv_data = {
.constraints = {
.name = "CHARGER_CV",
.min_uV = 4200000,
.max_uV = 4200000,
.apply_uV = 1,
},
};
static struct regulator_init_data __initdata max8997_charger_data = {
.constraints = {
.name = "CHARGER",
.min_uA = 200000,
.max_uA = 950000,
.boot_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS |
REGULATOR_CHANGE_CURRENT,
},
.num_consumer_supplies = ARRAY_SIZE(max8997_charger_),
.consumer_supplies = max8997_charger_,
};
static struct regulator_init_data __initdata max8997_charger_topoff_data = {
.constraints = {
.name = "CHARGER TOPOFF",
.min_uA = 50000,
.max_uA = 200000,
.valid_ops_mask = REGULATOR_CHANGE_CURRENT,
},
.num_consumer_supplies = ARRAY_SIZE(max8997_chg_toff_),
.consumer_supplies = max8997_chg_toff_,
};
static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = {
{ MAX8997_LDO1, &max8997_ldo1_data },
{ MAX8997_LDO2, &max8997_ldo2_data },
{ MAX8997_LDO3, &max8997_ldo3_data },
{ MAX8997_LDO4, &max8997_ldo4_data },
{ MAX8997_LDO5, &max8997_ldo5_data },
{ MAX8997_LDO6, &max8997_ldo6_data },
{ MAX8997_LDO7, &max8997_ldo7_data },
{ MAX8997_LDO8, &max8997_ldo8_data },
{ MAX8997_LDO9, &max8997_ldo9_data },
{ MAX8997_LDO10, &max8997_ldo10_data },
{ MAX8997_LDO11, &max8997_ldo11_data },
{ MAX8997_LDO12, &max8997_ldo12_data },
{ MAX8997_LDO13, &max8997_ldo13_data },
{ MAX8997_LDO14, &max8997_ldo14_data },
{ MAX8997_LDO15, &max8997_ldo15_data },
{ MAX8997_LDO16, &max8997_ldo16_data },
{ MAX8997_LDO18, &max8997_ldo18_data },
{ MAX8997_LDO21, &max8997_ldo21_data },
{ MAX8997_BUCK1, &max8997_buck1_data },
{ MAX8997_BUCK2, &max8997_buck2_data },
{ MAX8997_BUCK3, &max8997_buck3_data },
{ MAX8997_BUCK4, &max8997_buck4_data },
{ MAX8997_BUCK5, &max8997_buck5_data },
{ MAX8997_BUCK6, &max8997_buck6_data },
{ MAX8997_BUCK7, &max8997_buck7_data },
{ MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data },
{ MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data },
{ MAX8997_ENVICHG, &max8997_vichg_data },
{ MAX8997_ESAFEOUT1, &max8997_esafeout1_data },
{ MAX8997_ESAFEOUT2, &max8997_esafeout2_data },
{ MAX8997_CHARGER_CV, &max8997_charger_cv_data },
{ MAX8997_CHARGER, &max8997_charger_data },
{ MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data },
};
static struct max8997_platform_data __initdata nuri_max8997_pdata = {
.wakeup = 1,
.num_regulators = ARRAY_SIZE(nuri_max8997_regulators),
.regulators = nuri_max8997_regulators,
.buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
.buck2_gpiodvs = true,
.buck1_voltage[0] = 1350000, /* 1.35V */
.buck1_voltage[1] = 1300000, /* 1.3V */
.buck1_voltage[2] = 1250000, /* 1.25V */
.buck1_voltage[3] = 1200000, /* 1.2V */
.buck1_voltage[4] = 1150000, /* 1.15V */
.buck1_voltage[5] = 1100000, /* 1.1V */
.buck1_voltage[6] = 1000000, /* 1.0V */
.buck1_voltage[7] = 950000, /* 0.95V */
.buck2_voltage[0] = 1100000, /* 1.1V */
.buck2_voltage[1] = 1000000, /* 1.0V */
.buck2_voltage[2] = 950000, /* 0.95V */
.buck2_voltage[3] = 900000, /* 0.9V */
.buck2_voltage[4] = 1100000, /* 1.1V */
.buck2_voltage[5] = 1000000, /* 1.0V */
.buck2_voltage[6] = 950000, /* 0.95V */
.buck2_voltage[7] = 900000, /* 0.9V */
.buck5_voltage[0] = 1200000, /* 1.2V */
.buck5_voltage[1] = 1200000, /* 1.2V */
.buck5_voltage[2] = 1200000, /* 1.2V */
.buck5_voltage[3] = 1200000, /* 1.2V */
.buck5_voltage[4] = 1200000, /* 1.2V */
.buck5_voltage[5] = 1200000, /* 1.2V */
.buck5_voltage[6] = 1200000, /* 1.2V */
.buck5_voltage[7] = 1200000, /* 1.2V */
};
/* GPIO I2C 5 (PMIC) */
enum { I2C5_MAX8997 };
static struct i2c_board_info i2c5_devs[] __initdata = {
[I2C5_MAX8997] = {
I2C_BOARD_INFO("max8997", 0xCC >> 1),
.platform_data = &nuri_max8997_pdata,
},
};
static struct max17042_platform_data nuri_battery_platform_data = {
};
/* GPIO I2C 9 (Fuel Gauge) */
static struct i2c_gpio_platform_data i2c9_gpio_data = {
.sda_pin = EXYNOS4_GPY4(0), /* XM0ADDR_8 */
.scl_pin = EXYNOS4_GPY4(1), /* XM0ADDR_9 */
};
static struct platform_device i2c9_gpio = {
.name = "i2c-gpio",
.id = 9,
.dev = {
.platform_data = &i2c9_gpio_data,
},
};
enum { I2C9_MAX17042};
static struct i2c_board_info i2c9_devs[] __initdata = {
[I2C9_MAX17042] = {
I2C_BOARD_INFO("max17042", 0x36),
.platform_data = &nuri_battery_platform_data,
},
};
/* MAX8903 Secondary Charger */
static struct regulator_consumer_supply supplies_max8903[] = {
REGULATOR_SUPPLY("vinchg2", "charger-manager.0"),
};
static struct regulator_init_data max8903_charger_en_data = {
.constraints = {
.name = "VOUT_CHARGER",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.boot_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(supplies_max8903),
.consumer_supplies = supplies_max8903,
};
static struct fixed_voltage_config max8903_charger_en = {
.supply_name = "VOUT_CHARGER",
.microvolts = 5000000, /* Assume 5VDC */
.gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */
.enable_high = 0, /* Enable = Low */
.enabled_at_boot = 1,
.init_data = &max8903_charger_en_data,
};
static struct platform_device max8903_fixed_reg_dev = {
.name = "reg-fixed-voltage",
.id = FIXED_REG_ID_MAX8903,
.dev = { .platform_data = &max8903_charger_en },
};
static struct max8903_pdata nuri_max8903 = {
/*
* cen: don't control with the driver, let it be
* controlled by regulator above
*/
.dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
/* uok, usus: not connected */
.chg = EXYNOS4_GPE2(0), /* TA_nCHG */
/* flt: vcc_1.8V_pda */
.dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
.dc_valid = true,
.usb_valid = false, /* USB is not wired to MAX8903 */
};
static struct platform_device nuri_max8903_device = {
.name = "max8903-charger",
.dev = {
.platform_data = &nuri_max8903,
},
};
static struct device *nuri_cm_devices[] = {
&s3c_device_i2c5.dev,
&s3c_device_adc.dev,
NULL, /* Reserved for UART */
NULL,
};
static void __init nuri_power_init(void)
{
int gpio;
int irq_base = IRQ_GPIO_END + 1;
int ta_en = 0;
nuri_max8997_pdata.irq_base = irq_base;
irq_base += MAX8997_IRQ_NR;
gpio = EXYNOS4_GPX0(7);
gpio_request(gpio, "AP_PMIC_IRQ");
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
gpio = EXYNOS4_GPX2(3);
gpio_request(gpio, "FUEL_ALERT");
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
gpio = nuri_max8903.dok;
gpio_request(gpio, "TA_nCONNECTED");
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
ta_en = gpio_get_value(gpio) ? 0 : 1;
gpio = nuri_max8903.chg;
gpio_request(gpio, "TA_nCHG");
gpio_direction_input(gpio);
gpio = nuri_max8903.dcm;
gpio_request(gpio, "CURR_ADJ");
gpio_direction_output(gpio, ta_en);
}
/* USB EHCI */
static struct s5p_ehci_platdata nuri_ehci_pdata;
@ -361,6 +1090,7 @@ static void __init nuri_ehci_init(void)
static struct platform_device *nuri_devices[] __initdata = {
/* Samsung Platform Devices */
&s3c_device_i2c5, /* PMIC should initialize first */
&emmc_fixed_voltage,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
@ -369,11 +1099,20 @@ static struct platform_device *nuri_devices[] __initdata = {
&s3c_device_timer[0],
&s5p_device_ehci,
&s3c_device_i2c3,
&i2c9_gpio,
&s3c_device_adc,
&s3c_device_rtc,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&exynos4_device_pd[PD_MFC],
/* NURI Devices */
&nuri_gpio_keys,
&nuri_lcd_device,
&nuri_backlight_device,
&max8903_fixed_reg_dev,
&nuri_max8903_device,
};
static void __init nuri_map_io(void)
@ -383,21 +1122,32 @@ static void __init nuri_map_io(void)
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
}
static void __init nuri_reserve(void)
{
s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
}
static void __init nuri_machine_init(void)
{
nuri_sdhci_init();
nuri_tsp_init();
nuri_power_init();
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
s3c_i2c3_set_platdata(&i2c3_data);
i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
s3c_i2c5_set_platdata(NULL);
i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7));
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
nuri_ehci_init();
clk_xusbxti.rate = 24000000;
/* Last */
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
}
MACHINE_START(NURI, "NURI")
@ -407,4 +1157,5 @@ MACHINE_START(NURI, "NURI")
.map_io = nuri_map_io,
.init_machine = nuri_machine_init,
.timer = &exynos4_timer,
.reserve = &nuri_reserve,
MACHINE_END

71
arch/arm/mach-exynos4/mach-smdkc210.c
View File

@ -9,7 +9,9 @@
*/
#include <linux/serial_core.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/lcd.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
@ -19,11 +21,15 @@
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <video/platform_lcd.h>
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/regs-fb-v4.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/sdhci.h>
#include <plat/iic.h>
#include <plat/pd.h>
@ -111,6 +117,67 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
unsigned int power)
{
if (power) {
#if !defined(CONFIG_BACKLIGHT_PWM)
gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
gpio_free(EXYNOS4_GPD0(1));
#endif
/* fire nRESET on power up */
gpio_request(EXYNOS4_GPX0(6), "GPX0");
gpio_direction_output(EXYNOS4_GPX0(6), 1);
mdelay(100);
gpio_set_value(EXYNOS4_GPX0(6), 0);
mdelay(10);
gpio_set_value(EXYNOS4_GPX0(6), 1);
mdelay(10);
gpio_free(EXYNOS4_GPX0(6));
} else {
#if !defined(CONFIG_BACKLIGHT_PWM)
gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
gpio_free(EXYNOS4_GPD0(1));
#endif
}
}
static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
.set_power = lcd_lte480wv_set_power,
};
static struct platform_device smdkc210_lcd_lte480wv = {
.name = "platform-lcd",
.dev.parent = &s5p_device_fimd0.dev,
.dev.platform_data = &smdkc210_lcd_lte480wv_data,
};
static struct s3c_fb_pd_win smdkc210_fb_win0 = {
.win_mode = {
.left_margin = 13,
.right_margin = 8,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.max_bpp = 32,
.default_bpp = 24,
};
static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
.win[0] = &smdkc210_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
};
static struct resource smdkc210_smsc911x_resources[] = {
[0] = {
.start = EXYNOS4_PA_SROM_BANK(1),
@ -165,6 +232,8 @@ static struct platform_device *smdkc210_devices[] __initdata = {
&exynos4_device_pd[PD_GPS],
&exynos4_device_sysmmu,
&samsung_asoc_dma,
&s5p_device_fimd0,
&smdkc210_lcd_lte480wv,
&smdkc210_smsc911x,
};
@ -210,6 +279,8 @@ static void __init smdkc210_machine_init(void)
s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
}

3
arch/arm/mach-exynos4/mach-smdkv310.c
View File

@ -181,9 +181,12 @@ static struct platform_device *smdkv310_devices[] __initdata = {
&exynos4_device_pd[PD_CAM],
&exynos4_device_pd[PD_TV],
&exynos4_device_pd[PD_GPS],
&exynos4_device_spdif,
&exynos4_device_sysmmu,
&samsung_asoc_dma,
&samsung_asoc_idma,
&smdkv310_smsc911x,
&exynos4_device_ahci,
};
static void __init smdkv310_smsc911x_init(void)

121
arch/arm/mach-exynos4/mach-universal_c210.c
View File

@ -18,6 +18,9 @@
#include <linux/regulator/fixed.h>
#include <linux/regulator/max8952.h>
#include <linux/mmc/host.h>
#include <linux/i2c-gpio.h>
#include <linux/i2c/mcs.h>
#include <linux/i2c/atmel_mxt_ts.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@ -27,7 +30,10 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/iic.h>
#include <plat/gpio-cfg.h>
#include <plat/mfc.h>
#include <plat/sdhci.h>
#include <plat/pd.h>
#include <mach/map.h>
@ -477,6 +483,96 @@ static struct i2c_board_info i2c5_devs[] __initdata = {
},
};
/* I2C3 (TSP) */
static struct mxt_platform_data qt602240_platform_data = {
.x_line = 19,
.y_line = 11,
.x_size = 800,
.y_size = 480,
.blen = 0x11,
.threshold = 0x28,
.voltage = 2800000, /* 2.8V */
.orient = MXT_DIAGONAL,
};
static struct i2c_board_info i2c3_devs[] __initdata = {
{
I2C_BOARD_INFO("qt602240_ts", 0x4a),
.platform_data = &qt602240_platform_data,
},
};
static void __init universal_tsp_init(void)
{
int gpio;
/* TSP_LDO_ON: XMDMADDR_11 */
gpio = EXYNOS4_GPE2(3);
gpio_request(gpio, "TSP_LDO_ON");
gpio_direction_output(gpio, 1);
gpio_export(gpio, 0);
/* TSP_INT: XMDMADDR_7 */
gpio = EXYNOS4_GPE1(7);
gpio_request(gpio, "TSP_INT");
s5p_register_gpio_interrupt(gpio);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
i2c3_devs[0].irq = gpio_to_irq(gpio);
}
/* GPIO I2C 12 (3 Touchkey) */
static uint32_t touchkey_keymap[] = {
/* MCS_KEY_MAP(value, keycode) */
MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */
MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */
};
static struct mcs_platform_data touchkey_data = {
.keymap = touchkey_keymap,
.keymap_size = ARRAY_SIZE(touchkey_keymap),
.key_maxval = 2,
};
/* GPIO I2C 3_TOUCH 2.8V */
#define I2C_GPIO_BUS_12 12
static struct i2c_gpio_platform_data i2c_gpio12_data = {
.sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */
.scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */
};
static struct platform_device i2c_gpio12 = {
.name = "i2c-gpio",
.id = I2C_GPIO_BUS_12,
.dev = {
.platform_data = &i2c_gpio12_data,
},
};
static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
{
I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
.platform_data = &touchkey_data,
},
};
static void __init universal_touchkey_init(void)
{
int gpio;
gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */
gpio_request(gpio, "3_TOUCH_INT");
s5p_register_gpio_interrupt(gpio);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
gpio_request(gpio, "3_TOUCH_EN");
gpio_direction_output(gpio, 1);
}
/* GPIO KEYS */
static struct gpio_keys_button universal_gpio_keys_tables[] = {
{
@ -608,15 +704,25 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
static struct platform_device *universal_devices[] __initdata = {
/* Samsung Platform Devices */
&s5p_device_fimc0,
&s5p_device_fimc1,
&s5p_device_fimc2,
&s5p_device_fimc3,
&mmc0_fixed_voltage,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
&s3c_device_i2c3,
&s3c_device_i2c5,
/* Universal Devices */
&i2c_gpio12,
&universal_gpio_keys,
&s5p_device_onenand,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&exynos4_device_pd[PD_MFC],
};
static void __init universal_map_io(void)
@ -626,6 +732,11 @@ static void __init universal_map_io(void)
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
}
static void __init universal_reserve(void)
{
s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
}
static void __init universal_machine_init(void)
{
universal_sdhci_init();
@ -633,11 +744,20 @@ static void __init universal_machine_init(void)
i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
universal_tsp_init();
s3c_i2c3_set_platdata(NULL);
i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
s3c_i2c5_set_platdata(NULL);
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
universal_touchkey_init();
i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
ARRAY_SIZE(i2c_gpio12_devs));
/* Last */
platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
}
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
@ -647,4 +767,5 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
.map_io = universal_map_io,
.init_machine = universal_machine_init,
.timer = &exynos4_timer,
.reserve = &universal_reserve,
MACHINE_END

2
arch/arm/mach-exynos4/mct.c
View File

@ -383,8 +383,8 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
} else {
mct_tick1_event_irq.dev_id = &mct_tick[cpu];
irq_set_affinity(IRQ_MCT1, cpumask_of(1));
setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
}
}

57
arch/arm/mach-exynos4/platsmp.c
View File

@ -28,9 +28,12 @@
#include <mach/hardware.h>
#include <mach/regs-clock.h>
#include <mach/regs-pmu.h>
extern void exynos4_secondary_startup(void);
#define CPU1_BOOT_REG S5P_VA_SYSRAM
/*
* control for which core is the next to come out of the secondary
* boot "holding pen"
@ -58,6 +61,31 @@ static void __iomem *scu_base_addr(void)
static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit exynos4_gic_secondary_init(void)
{
void __iomem *dist_base = S5P_VA_GIC_DIST +
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
void __iomem *cpu_base = S5P_VA_GIC_CPU +
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
int i;
/*
* Deal with the banked PPI and SGI interrupts - disable all
* PPI interrupts, ensure all SGI interrupts are enabled.
*/
__raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
__raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
/*
* Set priority on PPI and SGI interrupts
*/
for (i = 0; i < 32; i += 4)
__raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
__raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
__raw_writel(1, cpu_base + GIC_CPU_CTRL);
}
void __cpuinit platform_secondary_init(unsigned int cpu)
{
/*
@ -65,7 +93,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_secondary_init(0);
exynos4_gic_secondary_init();
/*
* let the primary processor know we're out of the
@ -100,16 +128,41 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
write_pen_release(cpu);
if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
S5P_ARM_CORE1_CONFIGURATION);
timeout = 10;
/* wait max 10 ms until cpu1 is on */
while ((__raw_readl(S5P_ARM_CORE1_STATUS)
& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
mdelay(1);
}
if (timeout == 0) {
printk(KERN_ERR "cpu1 power enable failed");
spin_unlock(&boot_lock);
return -ETIMEDOUT;
}
}
/*
* Send the secondary CPU a soft interrupt, thereby causing
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
gic_raise_softirq(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
smp_rmb();
__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
CPU1_BOOT_REG);
gic_raise_softirq(cpumask_of(cpu), 1);
if (pen_release == -1)
break;

275
arch/arm/mach-exynos4/pm.c
View File

@ -18,92 +18,23 @@
#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/pll.h>
#include <plat/regs-srom.h>
#include <mach/regs-irq.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#include <mach/regs-pmu.h>
#include <mach/pm-core.h>
static struct sleep_save exynos4_sleep[] = {
{ .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, },
{ .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, },
{ .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, },
{ .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, },
{ .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, },
{ .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, },
{ .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, },
{ .reg = S5P_L2_0_LOWPWR , .val = 0x3, },
{ .reg = S5P_L2_1_LOWPWR , .val = 0x3, },
{ .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, },
{ .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, },
{ .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, },
{ .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, },
{ .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, },
{ .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, },
{ .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, },
{ .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, },
{ .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, },
{ .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, },
{ .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, },
{ .reg = S5P_XXTI_LOWPWR , .val = 0x0, },
{ .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, },
{ .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, },
{ .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_CAM_LOWPWR , .val = 0x0, },
{ .reg = S5P_TV_LOWPWR , .val = 0x0, },
{ .reg = S5P_MFC_LOWPWR , .val = 0x0, },
{ .reg = S5P_G3D_LOWPWR , .val = 0x0, },
{ .reg = S5P_LCD0_LOWPWR , .val = 0x0, },
{ .reg = S5P_LCD1_LOWPWR , .val = 0x0, },
{ .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_GPS_LOWPWR , .val = 0x0, },
{ .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, },
};
#include <mach/pmu.h>
static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
@ -118,20 +49,28 @@ static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
};
static struct sleep_save exynos4_epll_save[] = {
SAVE_ITEM(S5P_EPLL_CON0),
SAVE_ITEM(S5P_EPLL_CON1),
};
static struct sleep_save exynos4_vpll_save[] = {
SAVE_ITEM(S5P_VPLL_CON0),
SAVE_ITEM(S5P_VPLL_CON1),
};
static struct sleep_save exynos4_core_save[] = {
/* CMU side */
SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
SAVE_ITEM(S5P_EPLL_CON0),
SAVE_ITEM(S5P_EPLL_CON1),
SAVE_ITEM(S5P_VPLL_CON0),
SAVE_ITEM(S5P_VPLL_CON1),
SAVE_ITEM(S5P_CLKSRC_TOP0),
SAVE_ITEM(S5P_CLKSRC_TOP1),
SAVE_ITEM(S5P_CLKSRC_CAM),
SAVE_ITEM(S5P_CLKSRC_TV),
SAVE_ITEM(S5P_CLKSRC_MFC),
SAVE_ITEM(S5P_CLKSRC_G3D),
SAVE_ITEM(S5P_CLKSRC_IMAGE),
SAVE_ITEM(S5P_CLKSRC_LCD0),
SAVE_ITEM(S5P_CLKSRC_LCD1),
@ -158,6 +97,7 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_CLKDIV_PERIL4),
SAVE_ITEM(S5P_CLKDIV_PERIL5),
SAVE_ITEM(S5P_CLKDIV_TOP),
SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
SAVE_ITEM(S5P_CLKSRC_MASK_TV),
SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
@ -166,6 +106,7 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
SAVE_ITEM(S5P_CLKDIV2_RATIO),
SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
SAVE_ITEM(S5P_CLKGATE_IP_CAM),
SAVE_ITEM(S5P_CLKGATE_IP_TV),
@ -186,8 +127,10 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_CLKGATE_IP_DMC),
SAVE_ITEM(S5P_CLKSRC_CPU),
SAVE_ITEM(S5P_CLKDIV_CPU),
SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
SAVE_ITEM(S5P_CLKGATE_IP_CPU),
/* GIC side */
SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
@ -270,6 +213,13 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
/* SROM side */
SAVE_ITEM(S5P_SROM_BW),
SAVE_ITEM(S5P_SROM_BC0),
SAVE_ITEM(S5P_SROM_BC1),
SAVE_ITEM(S5P_SROM_BC2),
SAVE_ITEM(S5P_SROM_BC3),
};
static struct sleep_save exynos4_l2cc_save[] = {
@ -280,37 +230,11 @@ static struct sleep_save exynos4_l2cc_save[] = {
SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
};
void exynos4_cpu_suspend(void)
/* For Cortex-A9 Diagnostic and Power control register */
static unsigned int save_arm_register[2];
void exynos4_cpu_suspend(unsigned long arg)
{
unsigned long tmp;
unsigned long mask = 0xFFFFFFFF;
/* Setting Central Sequence Register for power down mode */
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* Setting Central Sequence option Register */
tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
tmp &= ~(S5P_USE_MASK);
tmp |= S5P_USE_STANDBY_WFI0;
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
/* Clear all interrupt pending to avoid early wakeup */
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
/* Disable all interrupt */
__raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
__raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
outer_flush_all();
/* issue the standby signal into the pm unit. */
@ -326,12 +250,14 @@ static void exynos4_pm_prepare(void)
s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
tmp = __raw_readl(S5P_INFORM1);
/* Set value of power down register for sleep mode */
s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep));
exynos4_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure at least INFORM0 has the resume address */
@ -373,12 +299,80 @@ void exynos4_scu_enable(void __iomem *scu_base)
flush_cache_all();
}
static unsigned long pll_base_rate;
static void exynos4_restore_pll(void)
{
unsigned long pll_con, locktime, lockcnt;
unsigned long pll_in_rate;
unsigned int p_div, epll_wait = 0, vpll_wait = 0;
if (pll_base_rate == 0)
return;
pll_in_rate = pll_base_rate;
/* EPLL */
pll_con = exynos4_epll_save[0].val;
if (pll_con & (1 << 31)) {
pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
pll_in_rate /= 1000000;
locktime = (3000 / pll_in_rate) * p_div;
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
__raw_writel(lockcnt, S5P_EPLL_LOCK);
s3c_pm_do_restore_core(exynos4_epll_save,
ARRAY_SIZE(exynos4_epll_save));
epll_wait = 1;
}
pll_in_rate = pll_base_rate;
/* VPLL */
pll_con = exynos4_vpll_save[0].val;
if (pll_con & (1 << 31)) {
pll_in_rate /= 1000000;
/* 750us */
locktime = 750;
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
__raw_writel(lockcnt, S5P_VPLL_LOCK);
s3c_pm_do_restore_core(exynos4_vpll_save,
ARRAY_SIZE(exynos4_vpll_save));
vpll_wait = 1;
}
/* Wait PLL locking */
do {
if (epll_wait) {
pll_con = __raw_readl(S5P_EPLL_CON0);
if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
epll_wait = 0;
}
if (vpll_wait) {
pll_con = __raw_readl(S5P_VPLL_CON0);
if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
vpll_wait = 0;
}
} while (epll_wait || vpll_wait);
}
static struct sysdev_driver exynos4_pm_driver = {
.add = exynos4_pm_add,
};
static __init int exynos4_pm_drvinit(void)
{
struct clk *pll_base;
unsigned int tmp;
s3c_pm_init();
@ -389,12 +383,69 @@ static __init int exynos4_pm_drvinit(void)
tmp |= ((0xFF << 8) | (0x1F << 1));
__raw_writel(tmp, S5P_WAKEUP_MASK);
pll_base = clk_get(NULL, "xtal");
if (!IS_ERR(pll_base)) {
pll_base_rate = clk_get_rate(pll_base);
clk_put(pll_base);
}
return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
}
arch_initcall(exynos4_pm_drvinit);
static int exynos4_pm_suspend(void)
{
unsigned long tmp;
/* Setting Central Sequence Register for power down mode */
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* Save Power control register */
asm ("mrc p15, 0, %0, c15, c0, 0"
: "=r" (tmp) : : "cc");
save_arm_register[0] = tmp;
/* Save Diagnostic register */
asm ("mrc p15, 0, %0, c15, c0, 1"
: "=r" (tmp) : : "cc");
save_arm_register[1] = tmp;
return 0;
}
static void exynos4_pm_resume(void)
{
unsigned long tmp;
/*
* If PMU failed while entering sleep mode, WFI will be
* ignored by PMU and then exiting cpu_do_idle().
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
* in this situation.
*/
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* No need to perform below restore code */
goto early_wakeup;
}
/* Restore Power control register */
tmp = save_arm_register[0];
asm volatile ("mcr p15, 0, %0, c15, c0, 0"
: : "r" (tmp)
: "cc");
/* Restore Diagnostic register */
tmp = save_arm_register[1];
asm volatile ("mcr p15, 0, %0, c15, c0, 1"
: : "r" (tmp)
: "cc");
/* For release retention */
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
@ -407,6 +458,8 @@ static void exynos4_pm_resume(void)
s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
exynos4_restore_pll();
exynos4_scu_enable(S5P_VA_SCU);
#ifdef CONFIG_CACHE_L2X0
@ -415,9 +468,13 @@ static void exynos4_pm_resume(void)
/* enable L2X0*/
writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
#endif
early_wakeup:
return;
}
static struct syscore_ops exynos4_pm_syscore_ops = {
.suspend = exynos4_pm_suspend,
.resume = exynos4_pm_resume,
};

175
arch/arm/mach-exynos4/pmu.c Normal file
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@ -0,0 +1,175 @@
/* linux/arch/arm/mach-exynos4/pmu.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS4210 - CPU PMU(Power Management Unit) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/io.h>
#include <linux/kernel.h>
#include <mach/regs-clock.h>
#include <mach/pmu.h>
static void __iomem *sys_powerdown_reg[] = {
S5P_ARM_CORE0_LOWPWR,
S5P_DIS_IRQ_CORE0,
S5P_DIS_IRQ_CENTRAL0,
S5P_ARM_CORE1_LOWPWR,
S5P_DIS_IRQ_CORE1,
S5P_DIS_IRQ_CENTRAL1,
S5P_ARM_COMMON_LOWPWR,
S5P_L2_0_LOWPWR,
S5P_L2_1_LOWPWR,
S5P_CMU_ACLKSTOP_LOWPWR,
S5P_CMU_SCLKSTOP_LOWPWR,
S5P_CMU_RESET_LOWPWR,
S5P_APLL_SYSCLK_LOWPWR,
S5P_MPLL_SYSCLK_LOWPWR,
S5P_VPLL_SYSCLK_LOWPWR,
S5P_EPLL_SYSCLK_LOWPWR,
S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
S5P_CMU_RESET_GPSALIVE_LOWPWR,
S5P_CMU_CLKSTOP_CAM_LOWPWR,
S5P_CMU_CLKSTOP_TV_LOWPWR,
S5P_CMU_CLKSTOP_MFC_LOWPWR,
S5P_CMU_CLKSTOP_G3D_LOWPWR,
S5P_CMU_CLKSTOP_LCD0_LOWPWR,
S5P_CMU_CLKSTOP_LCD1_LOWPWR,
S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
S5P_CMU_CLKSTOP_GPS_LOWPWR,
S5P_CMU_RESET_CAM_LOWPWR,
S5P_CMU_RESET_TV_LOWPWR,
S5P_CMU_RESET_MFC_LOWPWR,
S5P_CMU_RESET_G3D_LOWPWR,
S5P_CMU_RESET_LCD0_LOWPWR,
S5P_CMU_RESET_LCD1_LOWPWR,
S5P_CMU_RESET_MAUDIO_LOWPWR,
S5P_CMU_RESET_GPS_LOWPWR,
S5P_TOP_BUS_LOWPWR,
S5P_TOP_RETENTION_LOWPWR,
S5P_TOP_PWR_LOWPWR,
S5P_LOGIC_RESET_LOWPWR,
S5P_ONENAND_MEM_LOWPWR,
S5P_MODIMIF_MEM_LOWPWR,
S5P_G2D_ACP_MEM_LOWPWR,
S5P_USBOTG_MEM_LOWPWR,
S5P_HSMMC_MEM_LOWPWR,
S5P_CSSYS_MEM_LOWPWR,
S5P_SECSS_MEM_LOWPWR,
S5P_PCIE_MEM_LOWPWR,
S5P_SATA_MEM_LOWPWR,
S5P_PAD_RETENTION_DRAM_LOWPWR,
S5P_PAD_RETENTION_MAUDIO_LOWPWR,
S5P_PAD_RETENTION_GPIO_LOWPWR,
S5P_PAD_RETENTION_UART_LOWPWR,
S5P_PAD_RETENTION_MMCA_LOWPWR,
S5P_PAD_RETENTION_MMCB_LOWPWR,
S5P_PAD_RETENTION_EBIA_LOWPWR,
S5P_PAD_RETENTION_EBIB_LOWPWR,
S5P_PAD_RETENTION_ISOLATION_LOWPWR,
S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
S5P_XUSBXTI_LOWPWR,
S5P_XXTI_LOWPWR,
S5P_EXT_REGULATOR_LOWPWR,
S5P_GPIO_MODE_LOWPWR,
S5P_GPIO_MODE_MAUDIO_LOWPWR,
S5P_CAM_LOWPWR,
S5P_TV_LOWPWR,
S5P_MFC_LOWPWR,
S5P_G3D_LOWPWR,
S5P_LCD0_LOWPWR,
S5P_LCD1_LOWPWR,
S5P_MAUDIO_LOWPWR,
S5P_GPS_LOWPWR,
S5P_GPS_ALIVE_LOWPWR,
};
static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
/* { AFTR, LPA, SLEEP }*/
{ 0, 0, 2 }, /* ARM_CORE0 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */
{ 0, 0, 2 }, /* ARM_CORE1 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */
{ 0, 0, 2 }, /* ARM_COMMON */
{ 2, 2, 3 }, /* ARM_CPU_L2_0 */
{ 2, 2, 3 }, /* ARM_CPU_L2_1 */
{ 1, 0, 0 }, /* CMU_ACLKSTOP */
{ 1, 0, 0 }, /* CMU_SCLKSTOP */
{ 1, 1, 0 }, /* CMU_RESET */
{ 1, 0, 0 }, /* APLL_SYSCLK */
{ 1, 0, 0 }, /* MPLL_SYSCLK */
{ 1, 0, 0 }, /* VPLL_SYSCLK */
{ 1, 1, 0 }, /* EPLL_SYSCLK */
{ 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */
{ 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */
{ 1, 1, 0 }, /* CMU_CLKSTOP_CAM */
{ 1, 1, 0 }, /* CMU_CLKSTOP_TV */
{ 1, 1, 0 }, /* CMU_CLKSTOP_MFC */
{ 1, 1, 0 }, /* CMU_CLKSTOP_G3D */
{ 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */
{ 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */
{ 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */
{ 1, 1, 0 }, /* CMU_CLKSTOP_GPS */
{ 1, 1, 0 }, /* CMU_RESET_CAM */
{ 1, 1, 0 }, /* CMU_RESET_TV */
{ 1, 1, 0 }, /* CMU_RESET_MFC */
{ 1, 1, 0 }, /* CMU_RESET_G3D */
{ 1, 1, 0 }, /* CMU_RESET_LCD0 */
{ 1, 1, 0 }, /* CMU_RESET_LCD1 */
{ 1, 1, 0 }, /* CMU_RESET_MAUDIO */
{ 1, 1, 0 }, /* CMU_RESET_GPS */
{ 3, 0, 0 }, /* TOP_BUS */
{ 1, 0, 1 }, /* TOP_RETENTION */
{ 3, 0, 3 }, /* TOP_PWR */
{ 1, 1, 0 }, /* LOGIC_RESET */
{ 3, 0, 0 }, /* ONENAND_MEM */
{ 3, 0, 0 }, /* MODIMIF_MEM */
{ 3, 0, 0 }, /* G2D_ACP_MEM */
{ 3, 0, 0 }, /* USBOTG_MEM */
{ 3, 0, 0 }, /* HSMMC_MEM */
{ 3, 0, 0 }, /* CSSYS_MEM */
{ 3, 0, 0 }, /* SECSS_MEM */
{ 3, 0, 0 }, /* PCIE_MEM */
{ 3, 0, 0 }, /* SATA_MEM */
{ 1, 0, 0 }, /* PAD_RETENTION_DRAM */
{ 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */
{ 1, 0, 0 }, /* PAD_RETENTION_GPIO */
{ 1, 0, 0 }, /* PAD_RETENTION_UART */
{ 1, 0, 0 }, /* PAD_RETENTION_MMCA */
{ 1, 0, 0 }, /* PAD_RETENTION_MMCB */
{ 1, 0, 0 }, /* PAD_RETENTION_EBIA */
{ 1, 0, 0 }, /* PAD_RETENTION_EBIB */
{ 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */
{ 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */
{ 1, 1, 0 }, /* XUSBXTI */
{ 1, 1, 0 }, /* XXTI */
{ 1, 1, 0 }, /* EXT_REGULATOR */
{ 1, 0, 0 }, /* GPIO_MODE */
{ 1, 1, 0 }, /* GPIO_MODE_MAUDIO */
{ 7, 0, 0 }, /* CAM */
{ 7, 0, 0 }, /* TV */
{ 7, 0, 0 }, /* MFC */
{ 7, 0, 0 }, /* G3D */
{ 7, 0, 0 }, /* LCD0 */
{ 7, 0, 0 }, /* LCD1 */
{ 7, 7, 0 }, /* MAUDIO */
{ 7, 0, 0 }, /* GPS */
{ 7, 0, 0 }, /* GPS_ALIVE */
};
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
{
unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
for (; count > 0; count--)
__raw_writel(sys_powerdown_val[count - 1][mode],
sys_powerdown_reg[count - 1]);
}

43
arch/arm/mach-exynos4/setup-fimd0.c Normal file
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@ -0,0 +1,43 @@
/* linux/arch/arm/mach-exynos4/setup-fimd0.c
*
* Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Base Exynos4 FIMD 0 configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/fb.h>
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-fb-v4.h>
#include <mach/map.h>
void exynos4_fimd0_gpio_setup_24bpp(void)
{
unsigned int reg;
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
/*
* Set DISPLAY_CONTROL register for Display path selection.
*
* DISPLAY_CONTROL[1:0]
* ---------------------
* 00 | MIE
* 01 | MDINE
* 10 | FIMD : selected
* 11 | FIMD
*/
reg = __raw_readl(S3C_VA_SYS + 0x0210);
reg |= (1 << 1);
__raw_writel(reg, S3C_VA_SYS + 0x0210);
}

301
arch/arm/mach-exynos4/time.c
View File

@ -1,301 +0,0 @@
/* linux/arch/arm/mach-exynos4/time.c
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 (and compatible) HRT support
* PWM 2/4 is used for this feature
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/platform_device.h>
#include <asm/smp_twd.h>
#include <mach/map.h>
#include <plat/regs-timer.h>
#include <asm/mach/time.h>
static unsigned long clock_count_per_tick;
static struct clk *tin2;
static struct clk *tin4;
static struct clk *tdiv2;
static struct clk *tdiv4;
static struct clk *timerclk;
static void exynos4_pwm_stop(unsigned int pwm_id)
{
unsigned long tcon;
tcon = __raw_readl(S3C2410_TCON);
switch (pwm_id) {
case 2:
tcon &= ~S3C2410_TCON_T2START;
break;
case 4:
tcon &= ~S3C2410_TCON_T4START;
break;
default:
break;
}
__raw_writel(tcon, S3C2410_TCON);
}
static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
{
unsigned long tcon;
tcon = __raw_readl(S3C2410_TCON);
/* timers reload after counting zero, so reduce the count by 1 */
tcnt--;
/* ensure timer is stopped... */
switch (pwm_id) {
case 2:
tcon &= ~(0xf<<12);
tcon |= S3C2410_TCON_T2MANUALUPD;
__raw_writel(tcnt, S3C2410_TCNTB(2));
__raw_writel(tcnt, S3C2410_TCMPB(2));
__raw_writel(tcon, S3C2410_TCON);
break;
case 4:
tcon &= ~(7<<20);
tcon |= S3C2410_TCON_T4MANUALUPD;
__raw_writel(tcnt, S3C2410_TCNTB(4));
__raw_writel(tcnt, S3C2410_TCMPB(4));
__raw_writel(tcon, S3C2410_TCON);
break;
default:
break;
}
}
static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
{
unsigned long tcon;
tcon = __raw_readl(S3C2410_TCON);
switch (pwm_id) {
case 2:
tcon |= S3C2410_TCON_T2START;
tcon &= ~S3C2410_TCON_T2MANUALUPD;
if (periodic)
tcon |= S3C2410_TCON_T2RELOAD;
else
tcon &= ~S3C2410_TCON_T2RELOAD;
break;
case 4:
tcon |= S3C2410_TCON_T4START;
tcon &= ~S3C2410_TCON_T4MANUALUPD;
if (periodic)
tcon |= S3C2410_TCON_T4RELOAD;
else
tcon &= ~S3C2410_TCON_T4RELOAD;
break;
default:
break;
}
__raw_writel(tcon, S3C2410_TCON);
}
static int exynos4_pwm_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
exynos4_pwm_init(2, cycles);
exynos4_pwm_start(2, 0);
return 0;
}
static void exynos4_pwm_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
exynos4_pwm_stop(2);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
exynos4_pwm_init(2, clock_count_per_tick);
exynos4_pwm_start(2, 1);
break;
case CLOCK_EVT_MODE_ONESHOT:
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static struct clock_event_device pwm_event_device = {
.name = "pwm_timer2",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.shift = 32,
.set_next_event = exynos4_pwm_set_next_event,
.set_mode = exynos4_pwm_set_mode,
};
irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
{
struct clock_event_device *evt = &pwm_event_device;
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction exynos4_clock_event_irq = {
.name = "pwm_timer2_irq",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = exynos4_clock_event_isr,
};
static void __init exynos4_clockevent_init(void)
{
unsigned long pclk;
unsigned long clock_rate;
struct clk *tscaler;
pclk = clk_get_rate(timerclk);
/* configure clock tick */
tscaler = clk_get_parent(tdiv2);
clk_set_rate(tscaler, pclk / 2);
clk_set_rate(tdiv2, pclk / 2);
clk_set_parent(tin2, tdiv2);
clock_rate = clk_get_rate(tin2);
clock_count_per_tick = clock_rate / HZ;
pwm_event_device.mult =
div_sc(clock_rate, NSEC_PER_SEC, pwm_event_device.shift);
pwm_event_device.max_delta_ns =
clockevent_delta2ns(-1, &pwm_event_device);
pwm_event_device.min_delta_ns =
clockevent_delta2ns(1, &pwm_event_device);
pwm_event_device.cpumask = cpumask_of(0);
clockevents_register_device(&pwm_event_device);
setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
}
static cycle_t exynos4_pwm4_read(struct clocksource *cs)
{
return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
}
#ifdef CONFIG_PM
static void exynos4_pwm4_resume(struct clocksource *cs)
{
unsigned long pclk;
pclk = clk_get_rate(timerclk);
clk_set_rate(tdiv4, pclk / 2);
clk_set_parent(tin4, tdiv4);
exynos4_pwm_init(4, ~0);
exynos4_pwm_start(4, 1);
}
#endif
struct clocksource pwm_clocksource = {
.name = "pwm_timer4",
.rating = 250,
.read = exynos4_pwm4_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS ,
#ifdef CONFIG_PM
.resume = exynos4_pwm4_resume,
#endif
};
static void __init exynos4_clocksource_init(void)
{
unsigned long pclk;
unsigned long clock_rate;
pclk = clk_get_rate(timerclk);
clk_set_rate(tdiv4, pclk / 2);
clk_set_parent(tin4, tdiv4);
clock_rate = clk_get_rate(tin4);
exynos4_pwm_init(4, ~0);
exynos4_pwm_start(4, 1);
if (clocksource_register_hz(&pwm_clocksource, clock_rate))
panic("%s: can't register clocksource\n", pwm_clocksource.name);
}
static void __init exynos4_timer_resources(void)
{
struct platform_device tmpdev;
tmpdev.dev.bus = &platform_bus_type;
timerclk = clk_get(NULL, "timers");
if (IS_ERR(timerclk))
panic("failed to get timers clock for system timer");
clk_enable(timerclk);
tmpdev.id = 2;
tin2 = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin2))
panic("failed to get pwm-tin2 clock for system timer");
tdiv2 = clk_get(&tmpdev.dev, "pwm-tdiv");
if (IS_ERR(tdiv2))
panic("failed to get pwm-tdiv2 clock for system timer");
clk_enable(tin2);
tmpdev.id = 4;
tin4 = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin4))
panic("failed to get pwm-tin4 clock for system timer");
tdiv4 = clk_get(&tmpdev.dev, "pwm-tdiv");
if (IS_ERR(tdiv4))
panic("failed to get pwm-tdiv4 clock for system timer");
clk_enable(tin4);
}
static void __init exynos4_timer_init(void)
{
#ifdef CONFIG_LOCAL_TIMERS
twd_base = S5P_VA_TWD;
#endif
exynos4_timer_resources();
exynos4_clockevent_init();
exynos4_clocksource_init();
}
struct sys_timer exynos4_timer = {
.init = exynos4_timer_init,
};

3
arch/arm/mach-s3c2410/include/mach/pm-core.h
View File

@ -62,3 +62,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
struct pm_uart_save *save)
{
}
static inline void s3c_pm_restored_gpios(void) { }
static inline void s3c_pm_saved_gpios(void) { }

36
arch/arm/mach-s3c2412/clock.c
View File

@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable)
static struct clk clk_erefclk = {
.name = "erefclk",
.id = -1,
};
static struct clk clk_urefclk = {
.name = "urefclk",
.id = -1,
};
static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
static struct clk clk_usysclk = {
.name = "usysclk",
.id = -1,
.parent = &clk_xtal,
.ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_usysclk,
@ -132,13 +129,11 @@ static struct clk clk_usysclk = {
static struct clk clk_mrefclk = {
.name = "mrefclk",
.parent = &clk_xtal,
.id = -1,
};
static struct clk clk_mdivclk = {
.name = "mdivclk",
.parent = &clk_xtal,
.id = -1,
};
static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
static struct clk clk_usbsrc = {
.name = "usbsrc",
.id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_usbsrc,
.set_rate = s3c2412_setrate_usbsrc,
@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
static struct clk clk_msysclk = {
.name = "msysclk",
.id = -1,
.ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_msysclk,
},
@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
static struct clk clk_armclk = {
.name = "armclk",
.id = -1,
.parent = &clk_msysclk,
.ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_armclk,
@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
static struct clk clk_uart = {
.name = "uartclk",
.id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_uart,
.set_rate = s3c2412_setrate_uart,
@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
static struct clk clk_i2s = {
.name = "i2sclk",
.id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_i2s,
.set_rate = s3c2412_setrate_i2s,
@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
static struct clk clk_cam = {
.name = "camif-upll", /* same as 2440 name */
.id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_cam,
.set_rate = s3c2412_setrate_cam,
@ -463,37 +452,31 @@ static struct clk clk_cam = {
static struct clk init_clocks_disable[] = {
{
.name = "nand",
.id = -1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_NAND,
}, {
.name = "sdi",
.id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_SDI,
}, {
.name = "adc",
.id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_ADC,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_IIC,
}, {
.name = "iis",
.id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_IIS,
}, {
.name = "spi",
.id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_SPI,
@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = {
static struct clk init_clocks[] = {
{
.name = "dma",
.id = 0,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA0,
}, {
.name = "dma",
.id = 1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA1,
}, {
.name = "dma",
.id = 2,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA2,
}, {
.name = "dma",
.id = 3,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA3,
}, {
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_LCDC,
}, {
.name = "gpio",
.id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_GPIO,
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USBH,
}, {
.name = "usb-device",
.id = -1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USBD,
}, {
.name = "timers",
.id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_PWMT,
}, {
.name = "uart",
.id = 0,
.devname = "s3c2412-uart.0",
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART0,
}, {
.name = "uart",
.id = 1,
.devname = "s3c2412-uart.1",
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART1,
}, {
.name = "uart",
.id = 2,
.devname = "s3c2412-uart.2",
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART2,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_RTC,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p,
.ctrlbit = 0,
}, {
.name = "usb-bus-gadget",
.id = -1,
.parent = &clk_usb_bus,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USB_DEV48,
}, {
.name = "usb-bus-host",
.id = -1,
.parent = &clk_usb_bus,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USB_HOST48,

10
arch/arm/mach-s3c2416/clock.c
View File

@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = {
[0] = {
.clk = {
.name = "hsmmc-div",
.id = 0,
.devname = "s3c-sdhci.0",
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = {
[1] = {
.clk = {
.name = "hsmmc-div",
.id = 1,
.devname = "s3c-sdhci.1",
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = {
static struct clksrc_clk hsmmc_mux[] = {
[0] = {
.clk = {
.id = 0,
.name = "hsmmc-if",
.devname = "s3c-sdhci.0",
.ctrlbit = (1 << 6),
.enable = s3c2443_clkcon_enable_s,
},
@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = {
},
[1] = {
.clk = {
.id = 1,
.name = "hsmmc-if",
.devname = "s3c-sdhci.1",
.ctrlbit = (1 << 12),
.enable = s3c2443_clkcon_enable_s,
},
@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = {
static struct clk hsmmc0_clk = {
.name = "hsmmc",
.id = 0,
.devname = "s3c-sdhci.0",
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2416_HCLKCON_HSMMC0,

3
arch/arm/mach-s3c2440/clock.c
View File

@ -90,14 +90,12 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
static struct clk s3c2440_clk_cam = {
.name = "camif",
.id = -1,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2440_CLKCON_CAMERA,
};
static struct clk s3c2440_clk_cam_upll = {
.name = "camif-upll",
.id = -1,
.ops = &(struct clk_ops) {
.set_rate = s3c2440_camif_upll_setrate,
.round_rate = s3c2440_camif_upll_round,
@ -106,7 +104,6 @@ static struct clk s3c2440_clk_cam_upll = {
static struct clk s3c2440_clk_ac97 = {
.name = "ac97",
.id = -1,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2440_CLKCON_CAMERA,
};

16
arch/arm/mach-s3c2443/clock.c
View File

@ -59,7 +59,6 @@
static struct clk clk_i2s_ext = {
.name = "i2s-ext",
.id = -1,
};
/* armdiv
@ -139,7 +138,6 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
static struct clk clk_armdiv = {
.name = "armdiv",
.id = -1,
.parent = &clk_msysclk.clk,
.ops = &(struct clk_ops) {
.round_rate = s3c2443_armclk_roundrate,
@ -160,7 +158,6 @@ static struct clk *clk_arm_sources[] = {
static struct clksrc_clk clk_arm = {
.clk = {
.name = "armclk",
.id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_arm_sources,
@ -177,7 +174,6 @@ static struct clksrc_clk clk_arm = {
static struct clksrc_clk clk_hsspi = {
.clk = {
.name = "hsspi",
.id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_HSSPICLK,
.enable = s3c2443_clkcon_enable_s,
@ -196,7 +192,7 @@ static struct clksrc_clk clk_hsspi = {
static struct clksrc_clk clk_hsmmc_div = {
.clk = {
.name = "hsmmc-div",
.id = 1,
.devname = "s3c-sdhci.1",
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@ -231,7 +227,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
static struct clk clk_hsmmc = {
.name = "hsmmc-if",
.id = 1,
.devname = "s3c-sdhci.1",
.parent = &clk_hsmmc_div.clk,
.enable = s3c2443_enable_hsmmc,
.ops = &(struct clk_ops) {
@ -248,7 +244,6 @@ static struct clk clk_hsmmc = {
static struct clksrc_clk clk_i2s_eplldiv = {
.clk = {
.name = "i2s-eplldiv",
.id = -1,
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
@ -271,7 +266,6 @@ struct clk *clk_i2s_srclist[] = {
static struct clksrc_clk clk_i2s = {
.clk = {
.name = "i2s-if",
.id = -1,
.ctrlbit = S3C2443_SCLKCON_I2SCLK,
.enable = s3c2443_clkcon_enable_s,
@ -288,25 +282,23 @@ static struct clksrc_clk clk_i2s = {
static struct clk init_clocks_off[] = {
{
.name = "sdi",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SDI,
}, {
.name = "iis",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIS,
}, {
.name = "spi",
.id = 0,
.devname = "s3c2410-spi.0",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SPI0,
}, {
.name = "spi",
.id = 1,
.devname = "s3c2410-spi.1",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SPI1,

86
arch/arm/mach-s3c64xx/clock.c
View File

@ -39,7 +39,6 @@
static struct clk clk_ext_xtal_mux = {
.name = "ext_xtal",
.id = -1,
};
#define clk_fin_apll clk_ext_xtal_mux
@ -51,13 +50,11 @@ static struct clk clk_ext_xtal_mux = {
struct clk clk_h2 = {
.name = "hclk2",
.id = -1,
.rate = 0,
};
struct clk clk_27m = {
.name = "clk_27m",
.id = -1,
.rate = 27000000,
};
@ -83,14 +80,12 @@ static int clk_48m_ctrl(struct clk *clk, int enable)
struct clk clk_48m = {
.name = "clk_48m",
.id = -1,
.rate = 48000000,
.enable = clk_48m_ctrl,
};
struct clk clk_xusbxti = {
.name = "xusbxti",
.id = -1,
.rate = 48000000,
};
@ -130,109 +125,101 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
static struct clk init_clocks_off[] = {
{
.name = "nand",
.id = -1,
.parent = &clk_h,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_RTC,
}, {
.name = "adc",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_TSADC,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIC,
}, {
.name = "i2c",
.id = 1,
.devname = "s3c2440-i2c.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
}, {
.name = "iis",
.id = 0,
.devname = "samsung-i2s.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS0,
}, {
.name = "iis",
.id = 1,
.devname = "samsung-i2s.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS1,
}, {
#ifdef CONFIG_CPU_S3C6410
.name = "iis",
.id = -1, /* There's only one IISv4 port */
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
}, {
#endif
.name = "keypad",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
}, {
.name = "spi",
.id = 0,
.devname = "s3c64xx-spi.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI0,
}, {
.name = "spi",
.id = 1,
.devname = "s3c64xx-spi.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1,
}, {
.name = "spi_48m",
.id = 0,
.devname = "s3c64xx-spi.0",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
}, {
.name = "spi_48m",
.id = 1,
.devname = "s3c64xx-spi.1",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
}, {
.name = "48m",
.id = 0,
.devname = "s3c-sdhci.0",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
}, {
.name = "48m",
.id = 1,
.devname = "s3c-sdhci.1",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
}, {
.name = "48m",
.id = 2,
.devname = "s3c-sdhci.2",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
}, {
.name = "dma0",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA0,
}, {
.name = "dma1",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA1,
@ -242,89 +229,81 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_LCD,
}, {
.name = "gpio",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_GPIO,
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, {
.name = "hsmmc",
.id = 0,
.devname = "s3c-sdhci.0",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
}, {
.name = "hsmmc",
.id = 1,
.devname = "s3c-sdhci.1",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
}, {
.name = "hsmmc",
.id = 2,
.devname = "s3c-sdhci.2",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
}, {
.name = "otg",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_USB,
}, {
.name = "timers",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_PWM,
}, {
.name = "uart",
.id = 0,
.devname = "s3c6400-uart.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART0,
}, {
.name = "uart",
.id = 1,
.devname = "s3c6400-uart.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART1,
}, {
.name = "uart",
.id = 2,
.devname = "s3c6400-uart.2",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART2,
}, {
.name = "uart",
.id = 3,
.devname = "s3c6400-uart.3",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART3,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_WDT,
}, {
.name = "ac97",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_AC97,
}, {
.name = "cfcon",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_IHOST,
@ -334,7 +313,6 @@ static struct clk init_clocks[] = {
static struct clk clk_fout_apll = {
.name = "fout_apll",
.id = -1,
};
static struct clk *clk_src_apll_list[] = {
@ -350,7 +328,6 @@ static struct clksrc_sources clk_src_apll = {
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
.id = -1,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
.sources = &clk_src_apll,
@ -369,7 +346,6 @@ static struct clksrc_sources clk_src_epll = {
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
.id = -1,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
.sources = &clk_src_epll,
@ -388,7 +364,6 @@ static struct clksrc_sources clk_src_mpll = {
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
.id = -1,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
.sources = &clk_src_mpll,
@ -446,7 +421,6 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
static struct clk clk_arm = {
.name = "armclk",
.id = -1,
.parent = &clk_mout_apll.clk,
.ops = &(struct clk_ops) {
.get_rate = s3c64xx_clk_arm_get_rate,
@ -473,7 +447,6 @@ static struct clk_ops clk_dout_ops = {
static struct clk clk_dout_mpll = {
.name = "dout_mpll",
.id = -1,
.parent = &clk_mout_mpll.clk,
.ops = &clk_dout_ops,
};
@ -540,22 +513,18 @@ static struct clksrc_sources clkset_uhost = {
static struct clk clk_iis_cd0 = {
.name = "iis_cdclk0",
.id = -1,
};
static struct clk clk_iis_cd1 = {
.name = "iis_cdclk1",
.id = -1,
};
static struct clk clk_iisv4_cd = {
.name = "iis_cdclk_v4",
.id = -1,
};
static struct clk clk_pcm_cd = {
.name = "pcm_cdclk",
.id = -1,
};
static struct clk *clkset_audio0_list[] = {
@ -610,7 +579,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "mmc_bus",
.id = 0,
.devname = "s3c-sdhci.0",
.ctrlbit = S3C_CLKCON_SCLK_MMC0,
.enable = s3c64xx_sclk_ctrl,
},
@ -620,7 +589,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "mmc_bus",
.id = 1,
.devname = "s3c-sdhci.1",
.ctrlbit = S3C_CLKCON_SCLK_MMC1,
.enable = s3c64xx_sclk_ctrl,
},
@ -630,7 +599,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "mmc_bus",
.id = 2,
.devname = "s3c-sdhci.2",
.ctrlbit = S3C_CLKCON_SCLK_MMC2,
.enable = s3c64xx_sclk_ctrl,
},
@ -640,7 +609,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "usb-bus-host",
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UHOST,
.enable = s3c64xx_sclk_ctrl,
},
@ -650,7 +618,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UART,
.enable = s3c64xx_sclk_ctrl,
},
@ -661,7 +628,7 @@ static struct clksrc_clk clksrcs[] = {
/* Where does UCLK0 come from? */
.clk = {
.name = "spi-bus",
.id = 0,
.devname = "s3c64xx-spi.0",
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl,
},
@ -671,8 +638,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "spi-bus",
.id = 1,
.ctrlbit = S3C_CLKCON_SCLK_SPI1,
.devname = "s3c64xx-spi.1",
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
@ -681,7 +647,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "audio-bus",
.id = 0,
.devname = "samsung-i2s.0",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
.enable = s3c64xx_sclk_ctrl,
},
@ -691,7 +657,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "audio-bus",
.id = 1,
.devname = "samsung-i2s.1",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
.enable = s3c64xx_sclk_ctrl,
},
@ -701,7 +667,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "audio-bus",
.id = 2,
.devname = "samsung-i2s.2",
.ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
.enable = s3c64xx_sclk_ctrl,
},
@ -711,7 +677,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "irda-bus",
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_IRDA,
.enable = s3c64xx_sclk_ctrl,
},
@ -721,7 +686,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "camera",
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_CAM,
.enable = s3c64xx_sclk_ctrl,
},

7
arch/arm/mach-s3c64xx/include/mach/clkdev.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

1
arch/arm/mach-s3c64xx/include/mach/irqs.h
View File

@ -215,6 +215,7 @@
/* Compatibility */
#define IRQ_ONENAND IRQ_ONENAND0
#define IRQ_I2S0 IRQ_S3C6410_IIS
#endif /* __ASM_MACH_S3C64XX_IRQS_H */

19
arch/arm/mach-s3c64xx/include/mach/pm-core.h
View File

@ -53,7 +53,7 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
* the IRQ wake controls depending on the CPU we are running on */
#define s3c_irqwake_eintallow ((1 << 28) - 1)
#define s3c_irqwake_intallow (0)
#define s3c_irqwake_intallow (~0)
static inline void s3c_pm_arch_update_uart(void __iomem *regs,
struct pm_uart_save *save)
@ -96,3 +96,20 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
save->ucon = new_ucon;
}
}
static inline void s3c_pm_restored_gpios(void)
{
/* ensure sleep mode has been cleared from the system */
__raw_writel(0, S3C64XX_SLPEN);
}
static inline void s3c_pm_saved_gpios(void)
{
/* turn on the sleep mode and keep it there, as it seems that during
* suspend the xCON registers get re-set and thus you can end up with
* problems between going to sleep and resuming.
*/
__raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
}

12
arch/arm/mach-s3c64xx/irq.c
View File

@ -48,14 +48,22 @@ static struct s3c_uart_irq uart_irqs[] = {
},
};
/* setup the sources the vic should advertise resume for, even though it
* is not doing the wake (set_irq_wake needs to be valid) */
#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
{
printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
/* initialise the pair of VICs */
vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0);
vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0);
vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
/* add the timer sub-irqs */
s3c_init_vic_timer_irq(5, IRQ_TIMER0);

2
arch/arm/mach-s5p64x0/Makefile
View File

@ -13,7 +13,7 @@ obj- :=
# Core support for S5P64X0 system
obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o
obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o
obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o
obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o

74
arch/arm/mach-s5p64x0/clock-s5p6440.c
View File

@ -95,7 +95,6 @@ static struct clk_ops s5p6440_epll_ops = {
static struct clksrc_clk clk_hclk = {
.clk = {
.name = "clk_hclk",
.id = -1,
.parent = &clk_armclk.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
@ -104,7 +103,6 @@ static struct clksrc_clk clk_hclk = {
static struct clksrc_clk clk_pclk = {
.clk = {
.name = "clk_pclk",
.id = -1,
.parent = &clk_hclk.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@ -112,7 +110,6 @@ static struct clksrc_clk clk_pclk = {
static struct clksrc_clk clk_hclk_low = {
.clk = {
.name = "clk_hclk_low",
.id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
@ -122,7 +119,6 @@ static struct clksrc_clk clk_hclk_low = {
static struct clksrc_clk clk_pclk_low = {
.clk = {
.name = "clk_pclk_low",
.id = -1,
.parent = &clk_hclk_low.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@ -136,187 +132,167 @@ static struct clksrc_clk clk_pclk_low = {
static struct clk init_clocks_off[] = {
{
.name = "nand",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_mem_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "post",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 5)
}, {
.name = "2d",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "pdma",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "hsmmc",
.id = 0,
.devname = "s3c-sdhci.0",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "hsmmc",
.id = 1,
.devname = "s3c-sdhci.1",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "hsmmc",
.id = 2,
.devname = "s3c-sdhci.2",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "otg",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 20)
}, {
.name = "irom",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "lcd",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "hclk_fimgvg",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "tsi",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "rtc",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "timers",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "pcm",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "adc",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
.id = 0,
.devname = "s3c64xx-spi.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
.id = 1,
.devname = "s3c64xx-spi.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "gps",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "iis",
.id = 0,
.devname = "samsung-i2s.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "dsim",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 28),
}, {
.name = "etm",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 29),
}, {
.name = "dmc0",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 30),
}, {
.name = "pclk_fimgvg",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 31),
}, {
.name = "sclk_spi_48",
.id = 0,
.devname = "s3c64xx-spi.0",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "sclk_spi_48",
.id = 1,
.devname = "s3c64xx-spi.1",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 23),
}, {
.name = "mmc_48m",
.id = 0,
.devname = "s3c-sdhci.0",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "mmc_48m",
.id = 1,
.devname = "s3c-sdhci.1",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 28),
}, {
.name = "mmc_48m",
.id = 2,
.devname = "s3c-sdhci.2",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 29),
@ -329,43 +305,40 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "intc",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "mem",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "uart",
.id = 0,
.devname = "s3c6400-uart.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.id = 1,
.devname = "s3c6400-uart.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
.id = 2,
.devname = "s3c6400-uart.2",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
.id = 3,
.devname = "s3c6400-uart.3",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "gpio",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 18),
@ -374,12 +347,10 @@ static struct clk init_clocks[] = {
static struct clk clk_iis_cd_v40 = {
.name = "iis_cdclk_v40",
.id = -1,
};
static struct clk clk_pcm_cd = {
.name = "pcm_cdclk",
.id = -1,
};
static struct clk *clkset_group1_list[] = {
@ -420,7 +391,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_mmc",
.id = 0,
.devname = "s3c-sdhci.0",
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
},
@ -430,7 +401,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 1,
.devname = "s3c-sdhci.1",
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
},
@ -440,7 +411,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 2,
.devname = "s3c-sdhci.2",
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
},
@ -450,7 +421,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
.id = -1,
.ctrlbit = (1 << 5),
.enable = s5p64x0_sclk_ctrl,
},
@ -460,7 +430,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
.id = 0,
.devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
@ -470,7 +440,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
.id = 1,
.devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
@ -480,7 +450,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_post",
.id = -1,
.ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl,
},
@ -490,7 +459,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_dispcon",
.id = -1,
.ctrlbit = (1 << 1),
.enable = s5p64x0_sclk1_ctrl,
},
@ -500,7 +468,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimgvg",
.id = -1,
.ctrlbit = (1 << 2),
.enable = s5p64x0_sclk1_ctrl,
},
@ -510,7 +477,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_audio2",
.id = -1,
.ctrlbit = (1 << 11),
.enable = s5p64x0_sclk_ctrl,
},

68
arch/arm/mach-s5p64x0/clock-s5p6450.c
View File

@ -36,7 +36,6 @@
static struct clksrc_clk clk_mout_dpll = {
.clk = {
.name = "mout_dpll",
.id = -1,
},
.sources = &clk_src_dpll,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
@ -96,7 +95,6 @@ static struct clk_ops s5p6450_epll_ops = {
static struct clksrc_clk clk_dout_epll = {
.clk = {
.name = "dout_epll",
.id = -1,
.parent = &clk_mout_epll.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
@ -105,7 +103,6 @@ static struct clksrc_clk clk_dout_epll = {
static struct clksrc_clk clk_mout_hclk_sel = {
.clk = {
.name = "mout_hclk_sel",
.id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
@ -124,7 +121,6 @@ static struct clksrc_sources clkset_hclk = {
static struct clksrc_clk clk_hclk = {
.clk = {
.name = "clk_hclk",
.id = -1,
},
.sources = &clkset_hclk,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
@ -134,7 +130,6 @@ static struct clksrc_clk clk_hclk = {
static struct clksrc_clk clk_pclk = {
.clk = {
.name = "clk_pclk",
.id = -1,
.parent = &clk_hclk.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@ -142,7 +137,6 @@ static struct clksrc_clk clk_pclk = {
static struct clksrc_clk clk_dout_pwm_ratio0 = {
.clk = {
.name = "clk_dout_pwm_ratio0",
.id = -1,
.parent = &clk_mout_hclk_sel.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
@ -151,7 +145,6 @@ static struct clksrc_clk clk_dout_pwm_ratio0 = {
static struct clksrc_clk clk_pclk_to_wdt_pwm = {
.clk = {
.name = "clk_pclk_to_wdt_pwm",
.id = -1,
.parent = &clk_dout_pwm_ratio0.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
@ -160,7 +153,6 @@ static struct clksrc_clk clk_pclk_to_wdt_pwm = {
static struct clksrc_clk clk_hclk_low = {
.clk = {
.name = "clk_hclk_low",
.id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
@ -170,7 +162,6 @@ static struct clksrc_clk clk_hclk_low = {
static struct clksrc_clk clk_pclk_low = {
.clk = {
.name = "clk_pclk_low",
.id = -1,
.parent = &clk_hclk_low.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@ -184,109 +175,101 @@ static struct clksrc_clk clk_pclk_low = {
static struct clk init_clocks_off[] = {
{
.name = "usbhost",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "pdma",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "hsmmc",
.id = 0,
.devname = "s3c-sdhci.0",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "hsmmc",
.id = 1,
.devname = "s3c-sdhci.1",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "hsmmc",
.id = 2,
.devname = "s3c-sdhci.2",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "usbotg",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "rtc",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "adc",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
.id = 0,
.devname = "s3c2440-i2c.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
.id = 0,
.devname = "s3c64xx-spi.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
.id = 1,
.devname = "s3c64xx-spi.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "iis",
.id = 0,
.devname = "samsung-i2s.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "iis",
.id = 1,
.devname = "samsung-i2s.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "iis",
.id = 2,
.devname = "samsung-i2s.2",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "i2c",
.id = 1,
.devname = "s3c2440-i2c.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "dmc0",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 30),
@ -299,49 +282,45 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "intc",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "mem",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "uart",
.id = 0,
.devname = "s3c6400-uart.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.id = 1,
.devname = "s3c6400-uart.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
.id = 2,
.devname = "s3c6400-uart.2",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
.id = 3,
.devname = "s3c6400-uart.3",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "timers",
.id = -1,
.parent = &clk_pclk_to_wdt_pwm.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "gpio",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 18),
@ -421,7 +400,6 @@ static struct clksrc_sources clkset_sclk_audio0 = {
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "audio-bus",
.id = -1,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 8),
.parent = &clk_dout_epll.clk,
@ -435,7 +413,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_mmc",
.id = 0,
.devname = "s3c-sdhci.0",
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
},
@ -445,7 +423,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 1,
.devname = "s3c-sdhci.1",
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
},
@ -455,7 +433,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 2,
.devname = "s3c-sdhci.2",
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
},
@ -465,7 +443,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
.id = -1,
.ctrlbit = (1 << 5),
.enable = s5p64x0_sclk_ctrl,
},
@ -475,7 +452,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
.id = 0,
.devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
@ -485,7 +462,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
.id = 1,
.devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
@ -495,7 +472,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
.id = -1,
.ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl,
},
@ -505,7 +481,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "aclk_mali",
.id = -1,
.ctrlbit = (1 << 2),
.enable = s5p64x0_sclk1_ctrl,
},
@ -515,7 +490,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_2d",
.id = -1,
.ctrlbit = (1 << 12),
.enable = s5p64x0_sclk_ctrl,
},
@ -525,7 +499,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_usi",
.id = -1,
.ctrlbit = (1 << 7),
.enable = s5p64x0_sclk_ctrl,
},
@ -535,7 +508,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_camif",
.id = -1,
.ctrlbit = (1 << 6),
.enable = s5p64x0_sclk_ctrl,
},
@ -545,7 +517,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_dispcon",
.id = -1,
.ctrlbit = (1 << 1),
.enable = s5p64x0_sclk1_ctrl,
},
@ -555,7 +526,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_hsmmc44",
.id = -1,
.ctrlbit = (1 << 30),
.enable = s5p64x0_sclk_ctrl,
},

7
arch/arm/mach-s5p64x0/include/mach/clkdev.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

2
arch/arm/mach-s5p64x0/include/mach/irqs.h
View File

@ -85,6 +85,8 @@
#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4
#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5
#define IRQ_I2S0 IRQ_I2SV40
/* S5P6450 EINT feature will be added */
/*

10
arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
View File

@ -34,4 +34,14 @@
#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
/* External interrupt control registers for group0 */
#define EINT0CON0_OFFSET (0x900)
#define EINT0MASK_OFFSET (0x920)
#define EINT0PEND_OFFSET (0x924)
#define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET)
#define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET)
#define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET)
#endif /* __ASM_ARCH_REGS_GPIO_H */

152
arch/arm/mach-s5p64x0/irq-eint.c Normal file
View File

@ -0,0 +1,152 @@
/* arch/arm/mach-s5p64x0/irq-eint.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com/
*
* Based on linux/arch/arm/mach-s3c64xx/irq-eint.c
*
* S5P64X0 - Interrupt handling for External Interrupts.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <plat/regs-irqtype.h>
#include <plat/gpio-cfg.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#define eint_offset(irq) ((irq) - IRQ_EINT(0))
static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
int offs = eint_offset(data->irq);
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
if (offs > 15)
return -EINVAL;
switch (type) {
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
case IRQ_TYPE_EDGE_RISING:
newvalue = S3C2410_EXTINT_RISEEDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
newvalue = S3C2410_EXTINT_FALLEDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
newvalue = S3C2410_EXTINT_BOTHEDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
newvalue = S3C2410_EXTINT_LOWLEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S3C2410_EXTINT_HILEV;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -EINVAL;
}
shift = (offs / 2) * 4;
mask = 0x7 << shift;
ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, S5P64X0_EINT0CON0);
/* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000))
s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
else
s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
return 0;
}
/*
* s5p64x0_irq_demux_eint
*
* This function demuxes the IRQ from the group0 external interrupts,
* from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
* the specific handlers s5p64x0_irq_demux_eintX_Y.
*/
static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
{
u32 status = __raw_readl(S5P64X0_EINT0PEND);
u32 mask = __raw_readl(S5P64X0_EINT0MASK);
unsigned int irq;
status &= ~mask;
status >>= start;
status &= (1 << (end - start + 1)) - 1;
for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
if (status & 1)
generic_handle_irq(irq);
status >>= 1;
}
}
static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
{
s5p64x0_irq_demux_eint(0, 3);
}
static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
{
s5p64x0_irq_demux_eint(4, 11);
}
static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
struct irq_desc *desc)
{
s5p64x0_irq_demux_eint(12, 15);
}
static int s5p64x0_alloc_gc(void)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
S5P_VA_GPIO, handle_level_irq);
if (!gc) {
printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
"external interrupts failed\n", __func__);
return -EINVAL;
}
ct = gc->chip_types;
ct->chip.irq_ack = irq_gc_ack;
ct->chip.irq_mask = irq_gc_mask_set_bit;
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
ct->regs.ack = EINT0PEND_OFFSET;
ct->regs.mask = EINT0MASK_OFFSET;
irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
return 0;
}
static int __init s5p64x0_init_irq_eint(void)
{
int ret = s5p64x0_alloc_gc();
irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
return ret;
}
arch_initcall(s5p64x0_init_irq_eint);

163
arch/arm/mach-s5pc100/clock.c
View File

@ -31,7 +31,6 @@
static struct clk s5p_clk_otgphy = {
.name = "otg_phy",
.id = -1,
};
static struct clk *clk_src_mout_href_list[] = {
@ -47,7 +46,6 @@ static struct clksrc_sources clk_src_mout_href = {
static struct clksrc_clk clk_mout_href = {
.clk = {
.name = "mout_href",
.id = -1,
},
.sources = &clk_src_mout_href,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@ -66,7 +64,6 @@ static struct clksrc_sources clk_src_mout_48m = {
static struct clksrc_clk clk_mout_48m = {
.clk = {
.name = "mout_48m",
.id = -1,
},
.sources = &clk_src_mout_48m,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
@ -75,7 +72,6 @@ static struct clksrc_clk clk_mout_48m = {
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
.id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@ -85,7 +81,6 @@ static struct clksrc_clk clk_mout_mpll = {
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
.id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@ -94,7 +89,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
.id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@ -112,7 +106,6 @@ static struct clksrc_sources clk_src_mout_hpll = {
static struct clksrc_clk clk_mout_hpll = {
.clk = {
.name = "mout_hpll",
.id = -1,
},
.sources = &clk_src_mout_hpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@ -121,7 +114,6 @@ static struct clksrc_clk clk_mout_hpll = {
static struct clksrc_clk clk_div_apll = {
.clk = {
.name = "div_apll",
.id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
@ -130,7 +122,6 @@ static struct clksrc_clk clk_div_apll = {
static struct clksrc_clk clk_div_arm = {
.clk = {
.name = "div_arm",
.id = -1,
.parent = &clk_div_apll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@ -139,7 +130,6 @@ static struct clksrc_clk clk_div_arm = {
static struct clksrc_clk clk_div_d0_bus = {
.clk = {
.name = "div_d0_bus",
.id = -1,
.parent = &clk_div_arm.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@ -148,7 +138,6 @@ static struct clksrc_clk clk_div_d0_bus = {
static struct clksrc_clk clk_div_pclkd0 = {
.clk = {
.name = "div_pclkd0",
.id = -1,
.parent = &clk_div_d0_bus.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@ -157,7 +146,6 @@ static struct clksrc_clk clk_div_pclkd0 = {
static struct clksrc_clk clk_div_secss = {
.clk = {
.name = "div_secss",
.id = -1,
.parent = &clk_div_d0_bus.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
@ -166,7 +154,6 @@ static struct clksrc_clk clk_div_secss = {
static struct clksrc_clk clk_div_apll2 = {
.clk = {
.name = "div_apll2",
.id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
@ -185,7 +172,6 @@ struct clksrc_sources clk_src_mout_am = {
static struct clksrc_clk clk_mout_am = {
.clk = {
.name = "mout_am",
.id = -1,
},
.sources = &clk_src_mout_am,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@ -194,7 +180,6 @@ static struct clksrc_clk clk_mout_am = {
static struct clksrc_clk clk_div_d1_bus = {
.clk = {
.name = "div_d1_bus",
.id = -1,
.parent = &clk_mout_am.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
@ -203,7 +188,6 @@ static struct clksrc_clk clk_div_d1_bus = {
static struct clksrc_clk clk_div_mpll2 = {
.clk = {
.name = "div_mpll2",
.id = -1,
.parent = &clk_mout_am.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
@ -212,7 +196,6 @@ static struct clksrc_clk clk_div_mpll2 = {
static struct clksrc_clk clk_div_mpll = {
.clk = {
.name = "div_mpll",
.id = -1,
.parent = &clk_mout_am.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
@ -231,7 +214,6 @@ struct clksrc_sources clk_src_mout_onenand = {
static struct clksrc_clk clk_mout_onenand = {
.clk = {
.name = "mout_onenand",
.id = -1,
},
.sources = &clk_src_mout_onenand,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@ -240,7 +222,6 @@ static struct clksrc_clk clk_mout_onenand = {
static struct clksrc_clk clk_div_onenand = {
.clk = {
.name = "div_onenand",
.id = -1,
.parent = &clk_mout_onenand.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
@ -249,7 +230,6 @@ static struct clksrc_clk clk_div_onenand = {
static struct clksrc_clk clk_div_pclkd1 = {
.clk = {
.name = "div_pclkd1",
.id = -1,
.parent = &clk_div_d1_bus.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
@ -258,7 +238,6 @@ static struct clksrc_clk clk_div_pclkd1 = {
static struct clksrc_clk clk_div_cam = {
.clk = {
.name = "div_cam",
.id = -1,
.parent = &clk_div_mpll2.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
@ -267,7 +246,6 @@ static struct clksrc_clk clk_div_cam = {
static struct clksrc_clk clk_div_hdmi = {
.clk = {
.name = "div_hdmi",
.id = -1,
.parent = &clk_mout_hpll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
@ -399,367 +377,329 @@ static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
static struct clk init_clocks_off[] = {
{
.name = "cssys",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "secss",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "g2d",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "mdma",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "cfcon",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "nfcon",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "onenandc",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "sdm",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_2_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "seckey",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_2_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "hsmmc",
.id = 2,
.devname = "s3c-sdhci.2",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
.id = 1,
.devname = "s3c-sdhci.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
.id = 0,
.devname = "s3c-sdhci.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "modemif",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "otg",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "usbhost",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "pdma",
.id = 1,
.devname = "s3c-pl330.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "pdma",
.id = 0,
.devname = "s3c-pl330.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "lcd",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "rotator",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "fimc",
.id = 0,
.devname = "s5p-fimc.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "fimc",
.id = 1,
.devname = "s5p-fimc.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "fimc",
.id = 2,
.parent = &clk_div_d1_bus.clk,
.devname = "s5p-fimc.2",
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "jpeg",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "mipi-dsim",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "mipi-csis",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "g3d",
.id = 0,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "tv",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "vp",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "mixer",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "hdmi",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "mfc",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "apc",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "iec",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "systimer",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "rtc",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "i2c",
.id = 0,
.devname = "s3c2440-i2c.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "i2c",
.id = 1,
.devname = "s3c2440-i2c.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "spi",
.id = 0,
.devname = "s3c64xx-spi.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "spi",
.id = 1,
.devname = "s3c64xx-spi.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "spi",
.id = 2,
.devname = "s3c64xx-spi.2",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "irda",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "ccan",
.id = 0,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "ccan",
.id = 1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "hsitx",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "hsirx",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "iis",
.id = 0,
.devname = "samsung-i2s.0",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "iis",
.id = 1,
.devname = "samsung-i2s.1",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "iis",
.id = 2,
.devname = "samsung-i2s.2",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "ac97",
.id = -1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "pcm",
.id = 0,
.devname = "samsung-pcm.0",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "pcm",
.id = 1,
.devname = "samsung-pcm.1",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "spdif",
.id = -1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "adc",
.id = -1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "keypad",
.id = -1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "spi_48m",
.id = 0,
.devname = "s3c64xx-spi.0",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "spi_48m",
.id = 1,
.devname = "s3c64xx-spi.1",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "spi_48m",
.id = 2,
.devname = "s3c64xx-spi.2",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "mmc_48m",
.id = 0,
.devname = "s3c-sdhci.0",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "mmc_48m",
.id = 1,
.devname = "s3c-sdhci.1",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "mmc_48m",
.id = 2,
.devname = "s3c-sdhci.2",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 17),
@ -768,33 +708,27 @@ static struct clk init_clocks_off[] = {
static struct clk clk_vclk54m = {
.name = "vclk_54m",
.id = -1,
.rate = 54000000,
};
static struct clk clk_i2scdclk0 = {
.name = "i2s_cdclk0",
.id = -1,
};
static struct clk clk_i2scdclk1 = {
.name = "i2s_cdclk1",
.id = -1,
};
static struct clk clk_i2scdclk2 = {
.name = "i2s_cdclk2",
.id = -1,
};
static struct clk clk_pcmcdclk0 = {
.name = "pcm_cdclk0",
.id = -1,
};
static struct clk clk_pcmcdclk1 = {
.name = "pcm_cdclk1",
.id = -1,
};
static struct clk *clk_src_group1_list[] = {
@ -836,7 +770,7 @@ struct clksrc_sources clk_src_group3 = {
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "sclk_audio",
.id = 0,
.devname = "samsung-pcm.0",
.ctrlbit = (1 << 8),
.enable = s5pc100_sclk1_ctrl,
},
@ -862,7 +796,7 @@ struct clksrc_sources clk_src_group4 = {
static struct clksrc_clk clk_sclk_audio1 = {
.clk = {
.name = "sclk_audio",
.id = 1,
.devname = "samsung-pcm.1",
.ctrlbit = (1 << 9),
.enable = s5pc100_sclk1_ctrl,
},
@ -887,7 +821,7 @@ struct clksrc_sources clk_src_group5 = {
static struct clksrc_clk clk_sclk_audio2 = {
.clk = {
.name = "sclk_audio",
.id = 2,
.devname = "samsung-pcm.2",
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk1_ctrl,
},
@ -1014,7 +948,6 @@ static struct clk_ops s5pc100_sclk_spdif_ops = {
static struct clksrc_clk clk_sclk_spdif = {
.clk = {
.name = "sclk_spdif",
.id = -1,
.ctrlbit = (1 << 11),
.enable = s5pc100_sclk1_ctrl,
.ops = &s5pc100_sclk_spdif_ops,
@ -1027,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_spi",
.id = 0,
.devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 4),
.enable = s5pc100_sclk0_ctrl,
@ -1038,7 +971,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
.id = 1,
.devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 5),
.enable = s5pc100_sclk0_ctrl,
@ -1049,7 +982,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
.id = 2,
.devname = "s3c64xx-spi.2",
.ctrlbit = (1 << 6),
.enable = s5pc100_sclk0_ctrl,
@ -1060,7 +993,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
.id = -1,
.ctrlbit = (1 << 3),
.enable = s5pc100_sclk0_ctrl,
@ -1071,7 +1003,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mixer",
.id = -1,
.ctrlbit = (1 << 6),
.enable = s5pc100_sclk0_ctrl,
@ -1081,7 +1012,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_lcd",
.id = -1,
.ctrlbit = (1 << 0),
.enable = s5pc100_sclk1_ctrl,
@ -1092,7 +1022,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
.id = 0,
.devname = "s5p-fimc.0",
.ctrlbit = (1 << 1),
.enable = s5pc100_sclk1_ctrl,
@ -1103,7 +1033,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
.id = 1,
.devname = "s5p-fimc.1",
.ctrlbit = (1 << 2),
.enable = s5pc100_sclk1_ctrl,
@ -1114,7 +1044,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
.id = 2,
.devname = "s5p-fimc.2",
.ctrlbit = (1 << 3),
.enable = s5pc100_sclk1_ctrl,
@ -1125,7 +1055,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 0,
.devname = "s3c-sdhci.0",
.ctrlbit = (1 << 12),
.enable = s5pc100_sclk1_ctrl,
@ -1136,7 +1066,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 1,
.devname = "s3c-sdhci.1",
.ctrlbit = (1 << 13),
.enable = s5pc100_sclk1_ctrl,
@ -1147,7 +1077,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 2,
.devname = "s3c-sdhci.2",
.ctrlbit = (1 << 14),
.enable = s5pc100_sclk1_ctrl,
@ -1158,7 +1088,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_irda",
.id = 2,
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk0_ctrl,
@ -1169,7 +1098,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_irda",
.id = -1,
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk0_ctrl,
@ -1180,7 +1108,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_pwi",
.id = -1,
.ctrlbit = (1 << 1),
.enable = s5pc100_sclk0_ctrl,
@ -1191,7 +1118,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_uhost",
.id = -1,
.ctrlbit = (1 << 11),
.enable = s5pc100_sclk0_ctrl,
@ -1291,79 +1217,70 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
static struct clk init_clocks[] = {
{
.name = "tzic",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "intc",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "ebi",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "intmem",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "sromc",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "dmc",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "chipid",
.id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "gpio",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.id = 0,
.devname = "s3c6400-uart.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
.id = 1,
.devname = "s3c6400-uart.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.id = 2,
.devname = "s3c6400-uart.2",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
.id = 3,
.devname = "s3c6400-uart.3",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "timers",
.id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 6),

7
arch/arm/mach-s5pc100/include/mach/clkdev.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

1
arch/arm/mach-s5pv210/Kconfig
View File

@ -90,6 +90,7 @@ config MACH_GONI
select S3C_DEV_HSMMC2
select S3C_DEV_I2C1
select S3C_DEV_I2C2
select S5P_DEV_MFC
select S3C_DEV_USB_HSOTG
select S5P_DEV_ONENAND
select SAMSUNG_DEV_KEYPAD

137
arch/arm/mach-s5pv210/clock.c
View File

@ -36,7 +36,6 @@ static unsigned long xtal;
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
.id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
.id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = {
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
.id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = {
static struct clksrc_clk clk_armclk = {
.clk = {
.name = "armclk",
.id = -1,
},
.sources = &clkset_armclk,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = {
static struct clksrc_clk clk_hclk_msys = {
.clk = {
.name = "hclk_msys",
.id = -1,
.parent = &clk_armclk.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = {
static struct clksrc_clk clk_pclk_msys = {
.clk = {
.name = "pclk_msys",
.id = -1,
.parent = &clk_hclk_msys.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = {
static struct clksrc_clk clk_sclk_a2m = {
.clk = {
.name = "sclk_a2m",
.id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = {
static struct clksrc_clk clk_hclk_dsys = {
.clk = {
.name = "hclk_dsys",
.id = -1,
},
.sources = &clkset_hclk_sys,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = {
static struct clksrc_clk clk_pclk_dsys = {
.clk = {
.name = "pclk_dsys",
.id = -1,
.parent = &clk_hclk_dsys.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = {
static struct clksrc_clk clk_hclk_psys = {
.clk = {
.name = "hclk_psys",
.id = -1,
},
.sources = &clkset_hclk_sys,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = {
static struct clksrc_clk clk_pclk_psys = {
.clk = {
.name = "pclk_psys",
.id = -1,
.parent = &clk_hclk_psys.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
.id = -1,
.rate = 27000000,
};
static struct clk clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy",
.id = -1,
};
static struct clk clk_sclk_usbphy0 = {
.name = "sclk_usbphy0",
.id = -1,
};
static struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1",
.id = -1,
};
static struct clk clk_pcmcdclk0 = {
.name = "pcmcdclk",
.id = -1,
};
static struct clk clk_pcmcdclk1 = {
.name = "pcmcdclk",
.id = -1,
};
static struct clk clk_pcmcdclk2 = {
.name = "pcmcdclk",
.id = -1,
};
static struct clk *clkset_vpllsrc_list[] = {
@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = {
static struct clksrc_clk clk_vpllsrc = {
.clk = {
.name = "vpll_src",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 7),
},
@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
static struct clksrc_clk clk_sclk_vpll = {
.clk = {
.name = "sclk_vpll",
.id = -1,
},
.sources = &clkset_sclk_vpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = {
static struct clksrc_clk clk_mout_dmc0 = {
.clk = {
.name = "mout_dmc0",
.id = -1,
},
.sources = &clkset_moutdmc0src,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = {
static struct clksrc_clk clk_sclk_dmc0 = {
.clk = {
.name = "sclk_dmc0",
.id = -1,
.parent = &clk_mout_dmc0.clk,
},
.reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
@ -312,181 +290,175 @@ static struct clk_ops clk_fout_apll_ops = {
static struct clk init_clocks_off[] = {
{
.name = "pdma",
.id = 0,
.devname = "s3c-pl330.0",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "pdma",
.id = 1,
.devname = "s3c-pl330.1",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "rot",
.id = -1,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1<<29),
}, {
.name = "fimc",
.id = 0,
.devname = "s5pv210-fimc.0",
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 24),
}, {
.name = "fimc",
.id = 1,
.devname = "s5pv210-fimc.1",
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "fimc",
.id = 2,
.devname = "s5pv210-fimc.2",
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "mfc",
.devname = "s5p-mfc",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "otg",
.id = -1,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<17),
}, {
.name = "lcd",
.id = -1,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<0),
}, {
.name = "cfcon",
.id = 0,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<25),
}, {
.name = "hsmmc",
.id = 0,
.devname = "s3c-sdhci.0",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "hsmmc",
.id = 1,
.devname = "s3c-sdhci.1",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<17),
}, {
.name = "hsmmc",
.id = 2,
.devname = "s3c-sdhci.2",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<18),
}, {
.name = "hsmmc",
.id = 3,
.devname = "s3c-sdhci.3",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<19),
}, {
.name = "systimer",
.id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<22),
}, {
.name = "rtc",
.id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<15),
}, {
.name = "i2c",
.id = 0,
.devname = "s3c2440-i2c.0",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<7),
}, {
.name = "i2c",
.id = 1,
.devname = "s3c2440-i2c.1",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "i2c",
.id = 2,
.devname = "s3c2440-i2c.2",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<9),
}, {
.name = "spi",
.id = 0,
.devname = "s3c64xx-spi.0",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<12),
}, {
.name = "spi",
.id = 1,
.devname = "s3c64xx-spi.1",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<13),
}, {
.name = "spi",
.id = 2,
.devname = "s3c64xx-spi.2",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<14),
}, {
.name = "timers",
.id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<23),
}, {
.name = "adc",
.id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<24),
}, {
.name = "keypad",
.id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<21),
}, {
.name = "iis",
.id = 0,
.devname = "samsung-i2s.0",
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<4),
}, {
.name = "iis",
.id = 1,
.devname = "samsung-i2s.1",
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "iis",
.id = 2,
.devname = "samsung-i2s.2",
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "spdif",
.id = -1,
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 0),
@ -496,38 +468,36 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "hclk_imem",
.id = -1,
.parent = &clk_hclk_msys.clk,
.ctrlbit = (1 << 5),
.enable = s5pv210_clk_ip0_ctrl,
.ops = &clk_hclk_imem_ops,
}, {
.name = "uart",
.id = 0,
.devname = "s5pv210-uart.0",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "uart",
.id = 1,
.devname = "s5pv210-uart.1",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "uart",
.id = 2,
.devname = "s5pv210-uart.2",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "uart",
.id = 3,
.devname = "s5pv210-uart.3",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "sromc",
.id = -1,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1 << 26),
@ -579,7 +549,6 @@ static struct clksrc_sources clkset_sclk_dac = {
static struct clksrc_clk clk_sclk_dac = {
.clk = {
.name = "sclk_dac",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 2),
},
@ -590,7 +559,6 @@ static struct clksrc_clk clk_sclk_dac = {
static struct clksrc_clk clk_sclk_pixel = {
.clk = {
.name = "sclk_pixel",
.id = -1,
.parent = &clk_sclk_vpll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
@ -609,7 +577,6 @@ static struct clksrc_sources clkset_sclk_hdmi = {
static struct clksrc_clk clk_sclk_hdmi = {
.clk = {
.name = "sclk_hdmi",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 0),
},
@ -647,7 +614,7 @@ static struct clksrc_sources clkset_sclk_audio0 = {
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "sclk_audio",
.id = 0,
.devname = "soc-audio.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 24),
},
@ -676,7 +643,7 @@ static struct clksrc_sources clkset_sclk_audio1 = {
static struct clksrc_clk clk_sclk_audio1 = {
.clk = {
.name = "sclk_audio",
.id = 1,
.devname = "soc-audio.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 25),
},
@ -705,7 +672,7 @@ static struct clksrc_sources clkset_sclk_audio2 = {
static struct clksrc_clk clk_sclk_audio2 = {
.clk = {
.name = "sclk_audio",
.id = 2,
.devname = "soc-audio.2",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 26),
},
@ -763,7 +730,6 @@ static struct clk_ops s5pv210_sclk_spdif_ops = {
static struct clksrc_clk clk_sclk_spdif = {
.clk = {
.name = "sclk_spdif",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 27),
.ops = &s5pv210_sclk_spdif_ops,
@ -793,7 +759,6 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_dmc",
.id = -1,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@ -801,7 +766,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_onenand",
.id = -1,
},
.sources = &clkset_sclk_onenand,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
@ -809,7 +773,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
.id = 0,
.devname = "s5pv210-uart.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 12),
},
@ -819,7 +783,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
.id = 1,
.devname = "s5pv210-uart.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 13),
},
@ -829,7 +793,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
.id = 2,
.devname = "s5pv210-uart.2",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 14),
},
@ -839,7 +803,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
.id = 3,
.devname = "s5pv210-uart.3",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 15),
},
@ -849,7 +813,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mixer",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 1),
},
@ -858,7 +821,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
.id = 0,
.devname = "s5pv210-fimc.0",
.enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 2),
},
@ -868,7 +831,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
.id = 1,
.devname = "s5pv210-fimc.1",
.enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 3),
},
@ -878,7 +841,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
.id = 2,
.devname = "s5pv210-fimc.2",
.enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 4),
},
@ -888,7 +851,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
.id = 0,
.devname = "s5pv210-fimc.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 3),
},
@ -898,7 +861,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
.id = 1,
.devname = "s5pv210-fimc.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 4),
},
@ -908,7 +871,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 5),
},
@ -918,7 +880,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 0,
.devname = "s3c-sdhci.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 8),
},
@ -928,7 +890,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 1,
.devname = "s3c-sdhci.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 9),
},
@ -938,7 +900,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 2,
.devname = "s3c-sdhci.2",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 10),
},
@ -948,7 +910,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
.id = 3,
.devname = "s3c-sdhci.3",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 11),
},
@ -958,7 +920,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mfc",
.id = -1,
.devname = "s5p-mfc",
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 16),
},
@ -968,7 +930,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_g2d",
.id = -1,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 12),
},
@ -978,7 +939,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_g3d",
.id = -1,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 8),
},
@ -988,7 +948,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_csis",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 6),
},
@ -998,7 +957,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
.id = 0,
.devname = "s3c64xx-spi.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 16),
},
@ -1008,7 +967,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
.id = 1,
.devname = "s3c64xx-spi.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 17),
},
@ -1018,7 +977,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_pwi",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 29),
},
@ -1028,7 +986,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_pwm",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 19),
},

2
arch/arm/mach-s5pv210/cpu.c
View File

@ -126,7 +126,7 @@ void __init s5pv210_map_io(void)
s5pv210_default_sdhci2();
s5pv210_default_sdhci3();
s3c_adc_setname("s3c64xx-adc");
s3c_adc_setname("samsung-adc-v3");
s3c_cfcon_setname("s5pv210-pata");

2
arch/arm/mach-s5pv210/dev-audio.c
View File

@ -18,6 +18,7 @@
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
#include <mach/regs-audss.h>
static const char *rclksrc[] = {
[0] = "busclk",
@ -52,6 +53,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
| QUIRK_NEED_RSTCLR,
.src_clk = rclksrc,
.idma_addr = S5PV210_AUDSS_INT_MEM,
},
},
};

7
arch/arm/mach-s5pv210/include/mach/clkdev.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

3
arch/arm/mach-s5pv210/include/mach/map.h
View File

@ -59,6 +59,8 @@
#define S5PV210_PA_CFCON 0xE8200000
#define S5PV210_PA_MFC 0xF1700000
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
#define S5PV210_PA_HSOTG 0xEC000000
@ -107,6 +109,7 @@
#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
#define S5P_PA_MFC S5PV210_PA_MFC
#define S5P_PA_ONENAND S5PC110_PA_ONENAND
#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
#define S5P_PA_SDRAM S5PV210_PA_SDRAM

3
arch/arm/mach-s5pv210/include/mach/pm-core.h
View File

@ -41,3 +41,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
{
/* nothing here yet */
}
static inline void s3c_pm_restored_gpios(void) { }
static inline void s3c_pm_saved_gpios(void) { }

18
arch/arm/mach-s5pv210/include/mach/regs-audss.h Normal file
View File

@ -0,0 +1,18 @@
/* arch/arm/mach-s5pv210/include/mach/regs-audss.h
*
* Copyright (c) 2011 Samsung Electronics
* http://www.samsung.com
*
* S5PV210 Audio SubSystem clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_AUDSS_H
#define __PLAT_REGS_AUDSS_H __FILE__
#define S5PV210_AUDSS_INT_MEM (0xC0000000)
#endif /* _PLAT_REGS_AUDSS_H */

11
arch/arm/mach-s5pv210/mach-goni.c
View File

@ -47,6 +47,8 @@
#include <plat/sdhci.h>
#include <plat/clock.h>
#include <plat/s5p-time.h>
#include <plat/mfc.h>
#include <plat/regs-fb-v4.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@ -808,6 +810,9 @@ static struct platform_device *goni_devices[] __initdata = {
&goni_i2c_gpio5,
&mmc2_fixed_voltage,
&goni_device_gpiokeys,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&s3c_device_i2c0,
&s5p_device_fimc0,
&s5p_device_fimc1,
@ -841,6 +846,11 @@ static void __init goni_map_io(void)
s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
}
static void __init goni_reserve(void)
{
s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
}
static void __init goni_machine_init(void)
{
/* Radio: call before I2C 1 registeration */
@ -893,4 +903,5 @@ MACHINE_START(GONI, "GONI")
.map_io = goni_map_io,
.init_machine = goni_machine_init,
.timer = &s5p_timer,
.reserve = &goni_reserve,
MACHINE_END

1
arch/arm/mach-s5pv210/mach-smdkv210.c
View File

@ -267,6 +267,7 @@ static struct platform_device *smdkv210_devices[] __initdata = {
&s5pv210_device_iis0,
&s5pv210_device_spdif,
&samsung_asoc_dma,
&samsung_asoc_idma,
&samsung_device_keypad,
&smdkv210_dm9000,
&smdkv210_lcd_lte480wv,

4
arch/arm/plat-s3c24xx/clock-dclk.c
View File

@ -169,7 +169,6 @@ static struct clk_ops dclk_ops = {
struct clk s3c24xx_dclk0 = {
.name = "dclk0",
.id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
.enable = s3c24xx_dclk_enable,
.ops = &dclk_ops,
@ -177,7 +176,6 @@ struct clk s3c24xx_dclk0 = {
struct clk s3c24xx_dclk1 = {
.name = "dclk1",
.id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK1EN,
.enable = s3c24xx_dclk_enable,
.ops = &dclk_ops,
@ -189,12 +187,10 @@ static struct clk_ops clkout_ops = {
struct clk s3c24xx_clkout0 = {
.name = "clkout0",
.id = -1,
.ops = &clkout_ops,
};
struct clk s3c24xx_clkout1 = {
.name = "clkout1",
.id = -1,
.ops = &clkout_ops,
};

7
arch/arm/plat-s3c24xx/include/mach/clkdev.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

21
arch/arm/plat-s3c24xx/s3c2410-clock.c
View File

@ -90,37 +90,31 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)
static struct clk init_clocks_off[] = {
{
.name = "nand",
.id = -1,
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_NAND,
}, {
.name = "sdi",
.id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_SDI,
}, {
.name = "adc",
.id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_ADC,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_IIC,
}, {
.name = "iis",
.id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_IIS,
}, {
.name = "spi",
.id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_SPI,
@ -130,70 +124,61 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_LCDC,
}, {
.name = "gpio",
.id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_GPIO,
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_USBH,
}, {
.name = "usb-device",
.id = -1,
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_USBD,
}, {
.name = "timers",
.id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_PWMT,
}, {
.name = "uart",
.id = 0,
.devname = "s3c2410-uart.0",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART0,
}, {
.name = "uart",
.id = 1,
.devname = "s3c2410-uart.1",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART1,
}, {
.name = "uart",
.id = 2,
.devname = "s3c2410-uart.2",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART2,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_RTC,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p,
.ctrlbit = 0,
}, {
.name = "usb-bus-host",
.id = -1,
.parent = &clk_usb_bus,
}, {
.name = "usb-bus-gadget",
.id = -1,
.parent = &clk_usb_bus,
},
};

39
arch/arm/plat-s3c24xx/s3c2443-clock.c
View File

@ -56,7 +56,6 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
struct clk clk_mpllref = {
.name = "mpllref",
.parent = &clk_xtal,
.id = -1,
};
static struct clk *clk_epllref_sources[] = {
@ -69,7 +68,6 @@ static struct clk *clk_epllref_sources[] = {
struct clksrc_clk clk_epllref = {
.clk = {
.name = "epllref",
.id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_epllref_sources,
@ -92,7 +90,6 @@ struct clksrc_clk clk_esysclk = {
.clk = {
.name = "esysclk",
.parent = &clk_epll,
.id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_sysclk_sources,
@ -115,7 +112,6 @@ static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
static struct clk clk_mdivclk = {
.name = "mdivclk",
.parent = &clk_mpllref,
.id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2443_getrate_mdivclk,
},
@ -132,7 +128,6 @@ struct clksrc_clk clk_msysclk = {
.clk = {
.name = "msysclk",
.parent = &clk_xtal,
.id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_msysclk_sources,
@ -159,7 +154,6 @@ static unsigned long s3c2443_prediv_getrate(struct clk *clk)
static struct clk clk_prediv = {
.name = "prediv",
.id = -1,
.parent = &clk_msysclk.clk,
.ops = &(struct clk_ops) {
.get_rate = s3c2443_prediv_getrate,
@ -174,7 +168,6 @@ static struct clk clk_prediv = {
static struct clksrc_clk clk_usb_bus_host = {
.clk = {
.name = "usb-bus-host-parent",
.id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_USBHOST,
.enable = s3c2443_clkcon_enable_s,
@ -189,7 +182,6 @@ static struct clksrc_clk clksrc_clks[] = {
/* ART baud-rate clock sourced from esysclk via a divisor */
.clk = {
.name = "uartclk",
.id = -1,
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
@ -197,7 +189,6 @@ static struct clksrc_clk clksrc_clks[] = {
/* camera interface bus-clock, divided down from esysclk */
.clk = {
.name = "camif-upll", /* same as 2440 name */
.id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_CAMCLK,
.enable = s3c2443_clkcon_enable_s,
@ -206,7 +197,6 @@ static struct clksrc_clk clksrc_clks[] = {
}, {
.clk = {
.name = "display-if",
.id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_DISPCLK,
.enable = s3c2443_clkcon_enable_s,
@ -219,13 +209,11 @@ static struct clksrc_clk clksrc_clks[] = {
static struct clk init_clocks_off[] = {
{
.name = "adc",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_ADC,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIC,
@ -235,136 +223,117 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "dma",
.id = 0,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA0,
}, {
.name = "dma",
.id = 1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA1,
}, {
.name = "dma",
.id = 2,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA2,
}, {
.name = "dma",
.id = 3,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA3,
}, {
.name = "dma",
.id = 4,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA4,
}, {
.name = "dma",
.id = 5,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA5,
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_HSMMC,
}, {
.name = "gpio",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_GPIO,
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_USBH,
}, {
.name = "usb-device",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_USBD,
}, {
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_LCDC,
}, {
.name = "timers",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_PWMT,
}, {
.name = "cfc",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_CFC,
}, {
.name = "ssmc",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_SSMC,
}, {
.name = "uart",
.id = 0,
.devname = "s3c2440-uart.0",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART0,
}, {
.name = "uart",
.id = 1,
.devname = "s3c2440-uart.1",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART1,
}, {
.name = "uart",
.id = 2,
.devname = "s3c2440-uart.2",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART2,
}, {
.name = "uart",
.id = 3,
.devname = "s3c2440-uart.3",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART3,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_RTC,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C2443_PCLKCON_WDT,
}, {
.name = "ac97",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C2443_PCLKCON_AC97,
}, {
.name = "nand",
.id = -1,
.parent = &clk_h,
}, {
.name = "usb-bus-host",
.id = -1,
.parent = &clk_usb_bus_host.clk,
}
};

11
arch/arm/plat-s5p/Kconfig
View File

@ -39,6 +39,7 @@ config S5P_GPIO_INT
config S5P_HRT
bool
select SAMSUNG_DEV_PWM
help
Use the High Resolution timer support
@ -70,6 +71,16 @@ config S5P_DEV_FIMC3
help
Compile in platform device definitions for FIMC controller 3
config S5P_DEV_FIMD0
bool
help
Compile in platform device definitions for FIMD controller 0
config S5P_DEV_MFC
bool
help
Compile in platform device definitions for MFC
config S5P_DEV_ONENAND
bool
help

3
arch/arm/plat-s5p/Makefile
View File

@ -25,11 +25,12 @@ obj-$(CONFIG_PM) += irq-pm.o
obj-$(CONFIG_S5P_HRT) += s5p-time.o
# devices
obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o
obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o
obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o
obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o
obj-$(CONFIG_S5P_DEV_FIMC3) += dev-fimc3.o
obj-$(CONFIG_S5P_DEV_FIMD0) += dev-fimd0.o
obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o
obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o
obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o

67
arch/arm/plat-s5p/dev-fimd0.c Normal file
View File

@ -0,0 +1,67 @@
/* linux/arch/arm/plat-s5p/dev-fimd0.c
*
* Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Core file for Samsung Display Controller (FIMD) driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <linux/gfp.h>
#include <linux/dma-mapping.h>
#include <mach/irqs.h>
#include <mach/map.h>
#include <plat/fb.h>
#include <plat/devs.h>
#include <plat/cpu.h>
static struct resource s5p_fimd0_resource[] = {
[0] = {
.start = S5P_PA_FIMD0,
.end = S5P_PA_FIMD0 + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_FIMD0_VSYNC,
.end = IRQ_FIMD0_VSYNC,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_FIMD0_FIFO,
.end = IRQ_FIMD0_FIFO,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_FIMD0_SYSTEM,
.end = IRQ_FIMD0_SYSTEM,
.flags = IORESOURCE_IRQ,
},
};
static u64 fimd0_dmamask = DMA_BIT_MASK(32);
struct platform_device s5p_device_fimd0 = {
.name = "s5p-fb",
.id = 0,
.num_resources = ARRAY_SIZE(s5p_fimd0_resource),
.resource = s5p_fimd0_resource,
.dev = {
.dma_mask = &fimd0_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
{
s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
&s5p_device_fimd0);
}

123
arch/arm/plat-s5p/dev-mfc.c Normal file
View File

@ -0,0 +1,123 @@
/* linux/arch/arm/plat-s5p/dev-mfc.c
*
* Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
*
* Base S5P MFC resource and device definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/memblock.h>
#include <linux/ioport.h>
#include <mach/map.h>
#include <plat/devs.h>
#include <plat/irqs.h>
#include <plat/mfc.h>
static struct resource s5p_mfc_resource[] = {
[0] = {
.start = S5P_PA_MFC,
.end = S5P_PA_MFC + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_MFC,
.end = IRQ_MFC,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device s5p_device_mfc = {
.name = "s5p-mfc",
.id = -1,
.num_resources = ARRAY_SIZE(s5p_mfc_resource),
.resource = s5p_mfc_resource,
};
/*
* MFC hardware has 2 memory interfaces which are modelled as two separate
* platform devices to let dma-mapping distinguish between them.
*
* MFC parent device (s5p_device_mfc) must be registered before memory
* interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
*/
static u64 s5p_mfc_dma_mask = DMA_BIT_MASK(32);
struct platform_device s5p_device_mfc_l = {
.name = "s5p-mfc-l",
.id = -1,
.dev = {
.parent = &s5p_device_mfc.dev,
.dma_mask = &s5p_mfc_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
struct platform_device s5p_device_mfc_r = {
.name = "s5p-mfc-r",
.id = -1,
.dev = {
.parent = &s5p_device_mfc.dev,
.dma_mask = &s5p_mfc_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
struct s5p_mfc_reserved_mem {
phys_addr_t base;
unsigned long size;
struct device *dev;
};
static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
phys_addr_t lbase, unsigned int lsize)
{
int i;
s5p_mfc_mem[0].dev = &s5p_device_mfc_r.dev;
s5p_mfc_mem[0].base = rbase;
s5p_mfc_mem[0].size = rsize;
s5p_mfc_mem[1].dev = &s5p_device_mfc_l.dev;
s5p_mfc_mem[1].base = lbase;
s5p_mfc_mem[1].size = lsize;
for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
if (memblock_remove(area->base, area->size)) {
printk(KERN_ERR "Failed to reserve memory for MFC device (%ld bytes at 0x%08lx)\n",
area->size, (unsigned long) area->base);
area->base = 0;
}
}
}
static int __init s5p_mfc_memory_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
if (!area->base)
continue;
if (dma_declare_coherent_memory(area->dev, area->base,
area->base, area->size,
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0)
printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n",
area->size, (unsigned long) area->base);
}
return 0;
}
device_initcall(s5p_mfc_memory_init);

5
arch/arm/plat-s5p/include/plat/map-s5p.h
View File

@ -35,9 +35,10 @@
#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000)
#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))
#define S5P_VA_SCU S5P_VA_COREPERI(0x0)
#define S5P_VA_GIC_CPU S5P_VA_COREPERI(0x100)
#define S5P_VA_TWD S5P_VA_COREPERI(0x600)
#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000)
#define S5P_VA_GIC_CPU S3C_ADDR(0x02810000)
#define S5P_VA_GIC_DIST S3C_ADDR(0x02820000)
#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000)

27
arch/arm/plat-s5p/include/plat/mfc.h Normal file
View File

@ -0,0 +1,27 @@
/*
* Copyright (C) 2011 Samsung Electronics Co.Ltd
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __PLAT_S5P_MFC_H
#define __PLAT_S5P_MFC_H
/**
* s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
* @rbase: base address for MFC 'right' memory interface
* @rsize: size of the memory reserved for MFC 'right' interface
* @lbase: base address for MFC 'left' memory interface
* @lsize: size of the memory reserved for MFC 'left' interface
*
* This function reserves system memory for both MFC device memory
* interfaces and registers it to respective struct device entries as
* coherent memory.
*/
void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
phys_addr_t lbase, unsigned int lsize);
#endif /* __PLAT_S5P_MFC_H */

9
arch/arm/plat-s5p/s5p-time.c
View File

@ -384,6 +384,7 @@ static void __init s5p_timer_resources(void)
unsigned long event_id = timer_source.event_id;
unsigned long source_id = timer_source.source_id;
char devname[15];
timerclk = clk_get(NULL, "timers");
if (IS_ERR(timerclk))
@ -391,6 +392,10 @@ static void __init s5p_timer_resources(void)
clk_enable(timerclk);
sprintf(devname, "s3c24xx-pwm.%lu", event_id);
s3c_device_timer[event_id].id = event_id;
s3c_device_timer[event_id].dev.init_name = devname;
tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
if (IS_ERR(tin_event))
panic("failed to get pwm-tin clock for event timer");
@ -401,6 +406,10 @@ static void __init s5p_timer_resources(void)
clk_enable(tin_event);
sprintf(devname, "s3c24xx-pwm.%lu", source_id);
s3c_device_timer[source_id].id = source_id;
s3c_device_timer[source_id].dev.init_name = devname;
tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
if (IS_ERR(tin_source))
panic("failed to get pwm-tin clock for source timer");

84
arch/arm/plat-samsung/adc.c
View File

@ -21,6 +21,7 @@
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/regulator/consumer.h>
#include <plat/regs-adc.h>
#include <plat/adc.h>
@ -39,8 +40,9 @@
*/
enum s3c_cpu_type {
TYPE_S3C24XX,
TYPE_S3C64XX
TYPE_ADCV1, /* S3C24XX */
TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
};
struct s3c_adc_client {
@ -71,6 +73,7 @@ struct adc_device {
unsigned int prescale;
int irq;
struct regulator *vdd;
};
static struct adc_device *adc_dev;
@ -91,6 +94,7 @@ static inline void s3c_adc_select(struct adc_device *adc,
struct s3c_adc_client *client)
{
unsigned con = readl(adc->regs + S3C2410_ADCCON);
enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
client->select_cb(client, 1);
@ -98,8 +102,12 @@ static inline void s3c_adc_select(struct adc_device *adc,
con &= ~S3C2410_ADCCON_STDBM;
con &= ~S3C2410_ADCCON_STARTMASK;
if (!client->is_ts)
con |= S3C2410_ADCCON_SELMUX(client->channel);
if (!client->is_ts) {
if (cpu == TYPE_ADCV3)
writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
else
con |= S3C2410_ADCCON_SELMUX(client->channel);
}
writel(con, adc->regs + S3C2410_ADCCON);
}
@ -285,8 +293,8 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
client->nr_samples--;
if (cpu == TYPE_S3C64XX) {
/* S3C64XX ADC resolution is 12-bit */
if (cpu != TYPE_ADCV1) {
/* S3C64XX/S5P ADC resolution is 12-bit */
data0 &= 0xfff;
data1 &= 0xfff;
} else {
@ -312,7 +320,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
}
exit:
if (cpu == TYPE_S3C64XX) {
if (cpu != TYPE_ADCV1) {
/* Clear ADC interrupt */
writel(0, adc->regs + S3C64XX_ADCCLRINT);
}
@ -338,17 +346,24 @@ static int s3c_adc_probe(struct platform_device *pdev)
adc->pdev = pdev;
adc->prescale = S3C2410_ADCCON_PRSCVL(49);
adc->vdd = regulator_get(dev, "vdd");
if (IS_ERR(adc->vdd)) {
dev_err(dev, "operating without regulator \"vdd\" .\n");
ret = PTR_ERR(adc->vdd);
goto err_alloc;
}
adc->irq = platform_get_irq(pdev, 1);
if (adc->irq <= 0) {
dev_err(dev, "failed to get adc irq\n");
ret = -ENOENT;
goto err_alloc;
goto err_reg;
}
ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc);
if (ret < 0) {
dev_err(dev, "failed to attach adc irq\n");
goto err_alloc;
goto err_reg;
}
adc->clk = clk_get(dev, "adc");
@ -372,10 +387,14 @@ static int s3c_adc_probe(struct platform_device *pdev)
goto err_clk;
}
ret = regulator_enable(adc->vdd);
if (ret)
goto err_ioremap;
clk_enable(adc->clk);
tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
if (platform_get_device_id(pdev)->driver_data == TYPE_S3C64XX) {
if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1) {
/* Enable 12-bit ADC resolution */
tmp |= S3C64XX_ADCCON_RESSEL;
}
@ -388,12 +407,15 @@ static int s3c_adc_probe(struct platform_device *pdev)
return 0;
err_ioremap:
iounmap(adc->regs);
err_clk:
clk_put(adc->clk);
err_irq:
free_irq(adc->irq, adc);
err_reg:
regulator_put(adc->vdd);
err_alloc:
kfree(adc);
return ret;
@ -406,6 +428,8 @@ static int __devexit s3c_adc_remove(struct platform_device *pdev)
iounmap(adc->regs);
free_irq(adc->irq, adc);
clk_disable(adc->clk);
regulator_disable(adc->vdd);
regulator_put(adc->vdd);
clk_put(adc->clk);
kfree(adc);
@ -413,8 +437,10 @@ static int __devexit s3c_adc_remove(struct platform_device *pdev)
}
#ifdef CONFIG_PM
static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
static int s3c_adc_suspend(struct device *dev)
{
struct platform_device *pdev = container_of(dev,
struct platform_device, dev);
struct adc_device *adc = platform_get_drvdata(pdev);
unsigned long flags;
u32 con;
@ -428,19 +454,30 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
disable_irq(adc->irq);
spin_unlock_irqrestore(&adc->lock, flags);
clk_disable(adc->clk);
regulator_disable(adc->vdd);
return 0;
}
static int s3c_adc_resume(struct platform_device *pdev)
static int s3c_adc_resume(struct device *dev)
{
struct platform_device *pdev = container_of(dev,
struct platform_device, dev);
struct adc_device *adc = platform_get_drvdata(pdev);
int ret;
unsigned long tmp;
ret = regulator_enable(adc->vdd);
if (ret)
return ret;
clk_enable(adc->clk);
enable_irq(adc->irq);
writel(adc->prescale | S3C2410_ADCCON_PRSCEN,
adc->regs + S3C2410_ADCCON);
tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
/* Enable 12-bit ADC resolution */
if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1)
tmp |= S3C64XX_ADCCON_RESSEL;
writel(tmp, adc->regs + S3C2410_ADCCON);
return 0;
}
@ -453,25 +490,32 @@ static int s3c_adc_resume(struct platform_device *pdev)
static struct platform_device_id s3c_adc_driver_ids[] = {
{
.name = "s3c24xx-adc",
.driver_data = TYPE_S3C24XX,
.driver_data = TYPE_ADCV1,
}, {
.name = "s3c64xx-adc",
.driver_data = TYPE_S3C64XX,
.driver_data = TYPE_ADCV2,
}, {
.name = "samsung-adc-v3",
.driver_data = TYPE_ADCV3,
},
{ }
};
MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids);
static const struct dev_pm_ops adc_pm_ops = {
.suspend = s3c_adc_suspend,
.resume = s3c_adc_resume,
};
static struct platform_driver s3c_adc_driver = {
.id_table = s3c_adc_driver_ids,
.driver = {
.name = "s3c-adc",
.owner = THIS_MODULE,
.pm = &adc_pm_ops,
},
.probe = s3c_adc_probe,
.remove = __devexit_p(s3c_adc_remove),
.suspend = s3c_adc_suspend,
.resume = s3c_adc_resume,
};
static int __init adc_init(void)
@ -485,4 +529,4 @@ static int __init adc_init(void)
return ret;
}
arch_initcall(adc_init);
module_init(adc_init);

98
arch/arm/plat-samsung/clock.c
View File

@ -71,74 +71,6 @@ static int clk_null_enable(struct clk *clk, int enable)
return 0;
}
static int dev_is_s3c_uart(struct device *dev)
{
struct platform_device **pdev = s3c24xx_uart_devs;
int i;
for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++)
if (*pdev && dev == &(*pdev)->dev)
return 1;
return 0;
}
/*
* Serial drivers call get_clock() very early, before platform bus
* has been set up, this requires a special check to let them get
* a proper clock
*/
static int dev_is_platform_device(struct device *dev)
{
return dev->bus == &platform_bus_type ||
(dev->bus == NULL && dev_is_s3c_uart(dev));
}
/* Clock API calls */
struct clk *clk_get(struct device *dev, const char *id)
{
struct clk *p;
struct clk *clk = ERR_PTR(-ENOENT);
int idno;
if (dev == NULL || !dev_is_platform_device(dev))
idno = -1;
else
idno = to_platform_device(dev)->id;
spin_lock(&clocks_lock);
list_for_each_entry(p, &clocks, list) {
if (p->id == idno &&
strcmp(id, p->name) == 0 &&
try_module_get(p->owner)) {
clk = p;
break;
}
}
/* check for the case where a device was supplied, but the
* clock that was being searched for is not device specific */
if (IS_ERR(clk)) {
list_for_each_entry(p, &clocks, list) {
if (p->id == -1 && strcmp(id, p->name) == 0 &&
try_module_get(p->owner)) {
clk = p;
break;
}
}
}
spin_unlock(&clocks_lock);
return clk;
}
void clk_put(struct clk *clk)
{
module_put(clk->owner);
}
int clk_enable(struct clk *clk)
{
if (IS_ERR(clk) || clk == NULL)
@ -241,8 +173,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
return ret;
}
EXPORT_SYMBOL(clk_get);
EXPORT_SYMBOL(clk_put);
EXPORT_SYMBOL(clk_enable);
EXPORT_SYMBOL(clk_disable);
EXPORT_SYMBOL(clk_get_rate);
@ -265,7 +195,6 @@ struct clk_ops clk_ops_def_setrate = {
struct clk clk_xtal = {
.name = "xtal",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
@ -273,30 +202,25 @@ struct clk clk_xtal = {
struct clk clk_ext = {
.name = "ext",
.id = -1,
};
struct clk clk_epll = {
.name = "epll",
.id = -1,
};
struct clk clk_mpll = {
.name = "mpll",
.id = -1,
.ops = &clk_ops_def_setrate,
};
struct clk clk_upll = {
.name = "upll",
.id = -1,
.parent = NULL,
.ctrlbit = 0,
};
struct clk clk_f = {
.name = "fclk",
.id = -1,
.rate = 0,
.parent = &clk_mpll,
.ctrlbit = 0,
@ -304,7 +228,6 @@ struct clk clk_f = {
struct clk clk_h = {
.name = "hclk",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
@ -313,7 +236,6 @@ struct clk clk_h = {
struct clk clk_p = {
.name = "pclk",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
@ -322,7 +244,6 @@ struct clk clk_p = {
struct clk clk_usb_bus = {
.name = "usb-bus",
.id = -1,
.rate = 0,
.parent = &clk_upll,
};
@ -330,7 +251,6 @@ struct clk clk_usb_bus = {
struct clk s3c24xx_uclk = {
.name = "uclk",
.id = -1,
};
/* initialise the clock system */
@ -346,14 +266,11 @@ int s3c24xx_register_clock(struct clk *clk)
if (clk->enable == NULL)
clk->enable = clk_null_enable;
/* add to the list of available clocks */
/* Quick check to see if this clock has already been registered. */
BUG_ON(clk->list.prev != clk->list.next);
spin_lock(&clocks_lock);
list_add(&clk->list, &clocks);
spin_unlock(&clocks_lock);
/* fill up the clk_lookup structure and register it*/
clk->lookup.dev_id = clk->devname;
clk->lookup.con_id = clk->name;
clk->lookup.clk = clk;
clkdev_add(&clk->lookup);
return 0;
}
@ -463,10 +380,7 @@ static int clk_debugfs_register_one(struct clk *c)
char s[255];
char *p = s;
p += sprintf(p, "%s", c->name);
if (c->id >= 0)
sprintf(p, ":%d", c->id);
p += sprintf(p, "%s", c->devname);
d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
if (!d)

10
arch/arm/plat-samsung/dev-asocdma.c
View File

@ -23,3 +23,13 @@ struct platform_device samsung_asoc_dma = {
}
};
EXPORT_SYMBOL(samsung_asoc_dma);
struct platform_device samsung_asoc_idma = {
.name = "samsung-idma",
.id = -1,
.dev = {
.dma_mask = &audio_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
}
};
EXPORT_SYMBOL(samsung_asoc_idma);

1
arch/arm/plat-samsung/include/plat/audio.h
View File

@ -44,6 +44,7 @@ struct samsung_i2s {
* Also corresponds to clocks of I2SMOD[10]
*/
const char **src_clk;
dma_addr_t idma_addr;
};
/**

3
arch/arm/plat-samsung/include/plat/clock.h
View File

@ -10,6 +10,7 @@
*/
#include <linux/spinlock.h>
#include <linux/clkdev.h>
struct clk;
@ -40,6 +41,7 @@ struct clk {
struct module *owner;
struct clk *parent;
const char *name;
const char *devname;
int id;
int usage;
unsigned long rate;
@ -47,6 +49,7 @@ struct clk {
struct clk_ops *ops;
int (*enable)(struct clk *, int enable);
struct clk_lookup lookup;
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
struct dentry *dent; /* For visible tree hierarchy */
#endif

6
arch/arm/plat-samsung/include/plat/devs.h
View File

@ -40,6 +40,7 @@ extern struct platform_device s3c64xx_device_spi0;
extern struct platform_device s3c64xx_device_spi1;
extern struct platform_device samsung_asoc_dma;
extern struct platform_device samsung_asoc_idma;
extern struct platform_device s3c64xx_device_pcm0;
extern struct platform_device s3c64xx_device_pcm1;
@ -49,6 +50,7 @@ extern struct platform_device s3c64xx_device_ac97;
extern struct platform_device s3c_device_ts;
extern struct platform_device s3c_device_fb;
extern struct platform_device s5p_device_fimd0;
extern struct platform_device s3c_device_ohci;
extern struct platform_device s3c_device_lcd;
extern struct platform_device s3c_device_wdt;
@ -112,6 +114,7 @@ extern struct platform_device exynos4_device_i2s2;
extern struct platform_device exynos4_device_spdif;
extern struct platform_device exynos4_device_pd[];
extern struct platform_device exynos4_device_ahci;
extern struct platform_device exynos4_device_dwmci;
extern struct platform_device s5p6440_device_pcm;
extern struct platform_device s5p6440_device_iis;
@ -136,6 +139,9 @@ extern struct platform_device s5p_device_fimc1;
extern struct platform_device s5p_device_fimc2;
extern struct platform_device s5p_device_fimc3;
extern struct platform_device s5p_device_mfc;
extern struct platform_device s5p_device_mfc_l;
extern struct platform_device s5p_device_mfc_r;
extern struct platform_device s5p_device_mipi_csis0;
extern struct platform_device s5p_device_mipi_csis1;

15
arch/arm/plat-samsung/include/plat/fb-core.h
View File

@ -26,4 +26,19 @@ static inline void s3c_fb_setname(char *name)
#endif
}
/* Re-define device name depending on support. */
static inline void s5p_fb_setname(int id, char *name)
{
switch (id) {
#ifdef CONFIG_S5P_DEV_FIMD0
case 0:
s5p_device_fimd0.name = name;
break;
#endif
default:
printk(KERN_ERR "%s: invalid device id(%d)\n", __func__, id);
break;
}
}
#endif /* __ASM_PLAT_FB_CORE_H */

15
arch/arm/plat-samsung/include/plat/fb.h
View File

@ -73,6 +73,14 @@ struct s3c_fb_platdata {
*/
extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
/**
* s5p_fimd0_set_platdata() - Setup the FB device with platform data.
* @pd: The platform data to set. The data is copied from the passed structure
* so the machine data can mark the data __initdata so that any unused
* machines will end up dumping their data at runtime.
*/
extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
/**
* s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
*
@ -94,4 +102,11 @@ extern void s5pc100_fb_gpio_setup_24bpp(void);
*/
extern void s5pv210_fb_gpio_setup_24bpp(void);
/**
* exynos4_fimd0_gpio_setup_24bpp() - Exynos4 setup function for 24bpp LCD0
*
* Initialise the GPIO for an 24bpp LCD display on the RGB interface 0.
*/
extern void exynos4_fimd0_gpio_setup_24bpp(void);
#endif /* __PLAT_S3C_FB_H */

1
arch/arm/plat-samsung/include/plat/regs-adc.h
View File

@ -21,6 +21,7 @@
#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14)
#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18)
#define S5P_ADCMUX S3C2410_ADCREG(0x1C)
#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)

7
arch/arm/plat-samsung/irq-uart.c
View File

@ -19,6 +19,8 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/mach/irq.h>
#include <mach/map.h>
#include <plat/irq-uart.h>
#include <plat/regs-serial.h>
@ -30,9 +32,12 @@
static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
{
struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
struct irq_chip *chip = irq_get_chip(irq);
u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
int base = uirq->base_irq;
chained_irq_enter(chip, desc);
if (pend & (1 << 0))
generic_handle_irq(base);
if (pend & (1 << 1))
@ -41,6 +46,8 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
generic_handle_irq(base + 2);
if (pend & (1 << 3))
generic_handle_irq(base + 3);
chained_irq_exit(chip, desc);
}
static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)

2
arch/arm/plat-samsung/pm.c
View File

@ -268,6 +268,7 @@ static int s3c_pm_enter(suspend_state_t state)
/* save all necessary core registers not covered by the drivers */
s3c_pm_save_gpios();
s3c_pm_saved_gpios();
s3c_pm_save_uarts();
s3c_pm_save_core();
@ -309,6 +310,7 @@ static int s3c_pm_enter(suspend_state_t state)
s3c_pm_restore_core();
s3c_pm_restore_uarts();
s3c_pm_restore_gpios();
s3c_pm_restored_gpios();
s3c_pm_debug_init();

10
arch/arm/plat-samsung/pwm-clock.c
View File

@ -268,6 +268,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[0] = {
.clk = {
.name = "pwm-tdiv",
.devname = "s3c24xx-pwm.0",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[0],
},
@ -275,6 +276,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[1] = {
.clk = {
.name = "pwm-tdiv",
.devname = "s3c24xx-pwm.1",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[0],
}
@ -282,6 +284,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[2] = {
.clk = {
.name = "pwm-tdiv",
.devname = "s3c24xx-pwm.2",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1],
},
@ -289,6 +292,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[3] = {
.clk = {
.name = "pwm-tdiv",
.devname = "s3c24xx-pwm.3",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1],
},
@ -296,6 +300,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[4] = {
.clk = {
.name = "pwm-tdiv",
.devname = "s3c24xx-pwm.4",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1],
},
@ -361,26 +366,31 @@ static struct clk_ops clk_tin_ops = {
static struct clk clk_tin[] = {
[0] = {
.name = "pwm-tin",
.devname = "s3c24xx-pwm.0",
.id = 0,
.ops = &clk_tin_ops,
},
[1] = {
.name = "pwm-tin",
.devname = "s3c24xx-pwm.1",
.id = 1,
.ops = &clk_tin_ops,
},
[2] = {
.name = "pwm-tin",
.devname = "s3c24xx-pwm.2",
.id = 2,
.ops = &clk_tin_ops,
},
[3] = {
.name = "pwm-tin",
.devname = "s3c24xx-pwm.3",
.id = 3,
.ops = &clk_tin_ops,
},
[4] = {
.name = "pwm-tin",
.devname = "s3c24xx-pwm.4",
.id = 4,
.ops = &clk_tin_ops,
},

2
arch/arm/plat-samsung/time.c
View File

@ -259,6 +259,8 @@ static void __init s3c2410_timer_resources(void)
clk_enable(timerclk);
if (!use_tclk1_12()) {
tmpdev.id = 4;
tmpdev.dev.init_name = "s3c24xx-pwm.4";
tin = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin))
panic("failed to get pwm-tin clock for system timer");

2
drivers/tty/serial/s3c2410.c
View File

@ -96,8 +96,6 @@ static struct platform_driver s3c2410_serial_driver = {
},
};
s3c24xx_console_init(&s3c2410_serial_driver, &s3c2410_uart_inf);
static int __init s3c2410_serial_init(void)
{
return s3c24xx_serial_init(&s3c2410_serial_driver, &s3c2410_uart_inf);

2
drivers/tty/serial/s3c2412.c
View File

@ -130,8 +130,6 @@ static struct platform_driver s3c2412_serial_driver = {
},
};
s3c24xx_console_init(&s3c2412_serial_driver, &s3c2412_uart_inf);
static inline int s3c2412_serial_init(void)
{
return s3c24xx_serial_init(&s3c2412_serial_driver, &s3c2412_uart_inf);

2
drivers/tty/serial/s3c2440.c
View File

@ -159,8 +159,6 @@ static struct platform_driver s3c2440_serial_driver = {
},
};
s3c24xx_console_init(&s3c2440_serial_driver, &s3c2440_uart_inf);
static int __init s3c2440_serial_init(void)
{
return s3c24xx_serial_init(&s3c2440_serial_driver, &s3c2440_uart_inf);

2
drivers/tty/serial/s3c6400.c
View File

@ -130,8 +130,6 @@ static struct platform_driver s3c6400_serial_driver = {
},
};
s3c24xx_console_init(&s3c6400_serial_driver, &s3c6400_uart_inf);
static int __init s3c6400_serial_init(void)
{
return s3c24xx_serial_init(&s3c6400_serial_driver, &s3c6400_uart_inf);

7
drivers/tty/serial/s5pv210.c
View File

@ -135,13 +135,6 @@ static struct platform_driver s5p_serial_driver = {
},
};
static int __init s5pv210_serial_console_init(void)
{
return s3c24xx_serial_initconsole(&s5p_serial_driver, s5p_uart_inf);
}
console_initcall(s5pv210_serial_console_init);
static int __init s5p_serial_init(void)
{
return s3c24xx_serial_init(&s5p_serial_driver, *s5p_uart_inf);

9
drivers/tty/serial/samsung.c
View File

@ -1416,10 +1416,8 @@ s3c24xx_serial_console_setup(struct console *co, char *options)
/* is the port configured? */
if (port->mapbase == 0x0) {
co->index = 0;
port = &s3c24xx_serial_ports[co->index].port;
}
if (port->mapbase == 0x0)
return -ENODEV;
cons_uart = port;
@ -1451,7 +1449,8 @@ static struct console s3c24xx_serial_console = {
.flags = CON_PRINTBUFFER,
.index = -1,
.write = s3c24xx_serial_console_write,
.setup = s3c24xx_serial_console_setup
.setup = s3c24xx_serial_console_setup,
.data = &s3c24xx_uart_drv,
};
int s3c24xx_serial_initconsole(struct platform_driver *drv,

19
drivers/tty/serial/samsung.h
View File

@ -79,25 +79,6 @@ extern int s3c24xx_serial_initconsole(struct platform_driver *drv,
extern int s3c24xx_serial_init(struct platform_driver *drv,
struct s3c24xx_uart_info *info);
#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
#define s3c24xx_console_init(__drv, __inf) \
static int __init s3c_serial_console_init(void) \
{ \
struct s3c24xx_uart_info *uinfo[CONFIG_SERIAL_SAMSUNG_UARTS]; \
int i; \
\
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) \
uinfo[i] = __inf; \
return s3c24xx_serial_initconsole(__drv, uinfo); \
} \
\
console_initcall(s3c_serial_console_init)
#else
#define s3c24xx_console_init(drv, inf) extern void no_console(void)
#endif
#ifdef CONFIG_SERIAL_SAMSUNG_DEBUG
extern void printascii(const char *);