drm/amdgpu: Set TTM pools for memory partitions
For native mode only, create TTM pool for each memory partition to store the NUMA node id, then the TTM pool will be selected using memory partition id to allocate memory from the correct partition. Acked-by: Christian König <christian.koenig@amd.com> (rajneesh: changed need_swiotlb and need_dma32 to false for pool init) Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-and-tested-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -631,6 +631,7 @@ struct amdgpu_ttm_tt {
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struct task_struct *usertask;
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uint32_t userflags;
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bool bound;
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int32_t pool_id;
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};
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#define ttm_to_amdgpu_ttm_tt(ptr) container_of(ptr, struct amdgpu_ttm_tt, ttm)
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@ -1059,6 +1060,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
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return NULL;
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}
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gtt->gobj = &bo->base;
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gtt->pool_id = NUMA_NO_NODE;
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if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
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caching = ttm_write_combined;
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@ -1085,6 +1087,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
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struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
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struct ttm_pool *pool;
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pgoff_t i;
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int ret;
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@ -1099,7 +1102,11 @@ static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
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if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
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return 0;
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ret = ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
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if (adev->mman.ttm_pools && gtt->pool_id >= 0)
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pool = &adev->mman.ttm_pools[gtt->pool_id];
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else
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pool = &adev->mman.bdev.pool;
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ret = ttm_pool_alloc(pool, ttm, ctx);
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if (ret)
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return ret;
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@ -1120,6 +1127,7 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
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{
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struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
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struct amdgpu_device *adev;
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struct ttm_pool *pool;
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pgoff_t i;
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amdgpu_ttm_backend_unbind(bdev, ttm);
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@ -1138,7 +1146,13 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
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ttm->pages[i]->mapping = NULL;
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adev = amdgpu_ttm_adev(bdev);
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return ttm_pool_free(&adev->mman.bdev.pool, ttm);
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if (adev->mman.ttm_pools && gtt->pool_id >= 0)
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pool = &adev->mman.ttm_pools[gtt->pool_id];
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else
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pool = &adev->mman.bdev.pool;
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return ttm_pool_free(pool, ttm);
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}
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/**
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@ -1728,6 +1742,41 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
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return 0;
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}
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static int amdgpu_ttm_pools_init(struct amdgpu_device *adev)
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{
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int i;
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if (!adev->gmc.is_app_apu || !adev->gmc.num_mem_partitions)
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return 0;
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adev->mman.ttm_pools = kcalloc(adev->gmc.num_mem_partitions,
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sizeof(*adev->mman.ttm_pools),
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GFP_KERNEL);
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if (!adev->mman.ttm_pools)
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return -ENOMEM;
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for (i = 0; i < adev->gmc.num_mem_partitions; i++) {
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ttm_pool_init(&adev->mman.ttm_pools[i], adev->dev,
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adev->gmc.mem_partitions[i].numa.node,
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false, false);
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}
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return 0;
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}
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static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev)
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{
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int i;
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if (!adev->gmc.is_app_apu || !adev->mman.ttm_pools)
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return;
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for (i = 0; i < adev->gmc.num_mem_partitions; i++)
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ttm_pool_fini(&adev->mman.ttm_pools[i]);
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kfree(adev->mman.ttm_pools);
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adev->mman.ttm_pools = NULL;
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}
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/*
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* amdgpu_ttm_init - Init the memory management (ttm) as well as various
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* gtt/vram related fields.
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@ -1754,6 +1803,12 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
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DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
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return r;
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}
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r = amdgpu_ttm_pools_init(adev);
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if (r) {
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DRM_ERROR("failed to init ttm pools(%d).\n", r);
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return r;
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}
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adev->mman.initialized = true;
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/* Initialize VRAM pool with all of VRAM divided into pages */
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@ -1901,6 +1956,8 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
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if (!adev->mman.initialized)
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return;
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amdgpu_ttm_pools_fini(adev);
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amdgpu_ttm_training_reserve_vram_fini(adev);
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/* return the stolen vga memory back to VRAM */
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if (!adev->gmc.is_app_apu) {
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@ -49,6 +49,7 @@ struct amdgpu_gtt_mgr {
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struct amdgpu_mman {
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struct ttm_device bdev;
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struct ttm_pool *ttm_pools;
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bool initialized;
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void __iomem *aper_base_kaddr;
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