ARM: tegra: Remove duplicate code
Remove Tegra legacy clock framework code. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Prashant Gaikwad
Stephen Warren
parent
92fe58f07f
commit
1dfacc1613
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@ -20,8 +20,6 @@
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/module.h>
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@ -37,642 +35,13 @@
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/*
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* Locking:
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*
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* Each struct clk has a spinlock.
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*
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* To avoid AB-BA locking problems, locks must always be traversed from child
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* clock to parent clock. For example, when enabling a clock, the clock's lock
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* is taken, and then clk_enable is called on the parent, which take's the
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* parent clock's lock. There is one exceptions to this ordering: When dumping
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* the clock tree through debugfs. In this case, clk_lock_all is called,
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* which attemps to iterate through the entire list of clocks and take every
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* clock lock. If any call to spin_trylock fails, all locked clocks are
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* unlocked, and the process is retried. When all the locks are held,
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* the only clock operation that can be called is clk_get_rate_all_locked.
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*
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* Within a single clock, no clock operation can call another clock operation
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* on itself, except for clk_get_rate_locked and clk_set_rate_locked. Any
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* clock operation can call any other clock operation on any of it's possible
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* parents.
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*
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* An additional mutex, clock_list_lock, is used to protect the list of all
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* clocks.
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*
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* The clock operations must lock internally to protect against
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* read-modify-write on registers that are shared by multiple clocks
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*/
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static DEFINE_MUTEX(clock_list_lock);
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static LIST_HEAD(clocks);
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#ifndef CONFIG_COMMON_CLK
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struct clk *tegra_get_clock_by_name(const char *name)
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{
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struct clk *c;
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struct clk *ret = NULL;
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mutex_lock(&clock_list_lock);
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list_for_each_entry(c, &clocks, node) {
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if (strcmp(c->name, name) == 0) {
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ret = c;
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break;
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}
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}
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mutex_unlock(&clock_list_lock);
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return ret;
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}
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/* Must be called with c->spinlock held */
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static unsigned long clk_predict_rate_from_parent(struct clk *c, struct clk *p)
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{
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u64 rate;
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rate = clk_get_rate(p);
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if (c->mul != 0 && c->div != 0) {
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rate *= c->mul;
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rate += c->div - 1; /* round up */
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do_div(rate, c->div);
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}
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return rate;
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}
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/* Must be called with c->spinlock held */
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unsigned long clk_get_rate_locked(struct clk *c)
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{
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unsigned long rate;
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if (c->parent)
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rate = clk_predict_rate_from_parent(c, c->parent);
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else
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rate = c->rate;
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return rate;
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}
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unsigned long clk_get_rate(struct clk *c)
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{
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unsigned long flags;
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unsigned long rate;
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spin_lock_irqsave(&c->spinlock, flags);
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rate = clk_get_rate_locked(c);
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spin_unlock_irqrestore(&c->spinlock, flags);
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return rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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int clk_reparent(struct clk *c, struct clk *parent)
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{
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c->parent = parent;
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return 0;
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}
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void clk_init(struct clk *c)
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{
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spin_lock_init(&c->spinlock);
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if (c->ops && c->ops->init)
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c->ops->init(c);
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if (!c->ops || !c->ops->enable) {
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c->refcnt++;
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c->set = true;
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if (c->parent)
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c->state = c->parent->state;
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else
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c->state = ON;
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}
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mutex_lock(&clock_list_lock);
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list_add(&c->node, &clocks);
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mutex_unlock(&clock_list_lock);
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}
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int clk_enable(struct clk *c)
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{
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&c->spinlock, flags);
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if (c->refcnt == 0) {
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if (c->parent) {
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ret = clk_enable(c->parent);
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if (ret)
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goto out;
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}
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if (c->ops && c->ops->enable) {
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ret = c->ops->enable(c);
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if (ret) {
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if (c->parent)
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clk_disable(c->parent);
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goto out;
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}
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c->state = ON;
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c->set = true;
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}
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}
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c->refcnt++;
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out:
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spin_unlock_irqrestore(&c->spinlock, flags);
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return ret;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *c)
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{
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unsigned long flags;
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spin_lock_irqsave(&c->spinlock, flags);
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if (c->refcnt == 0) {
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WARN(1, "Attempting to disable clock %s with refcnt 0", c->name);
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spin_unlock_irqrestore(&c->spinlock, flags);
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return;
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}
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if (c->refcnt == 1) {
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if (c->ops && c->ops->disable)
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c->ops->disable(c);
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if (c->parent)
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clk_disable(c->parent);
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c->state = OFF;
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}
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c->refcnt--;
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spin_unlock_irqrestore(&c->spinlock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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int clk_set_parent(struct clk *c, struct clk *parent)
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{
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int ret;
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unsigned long flags;
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unsigned long new_rate;
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unsigned long old_rate;
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spin_lock_irqsave(&c->spinlock, flags);
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if (!c->ops || !c->ops->set_parent) {
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ret = -ENOSYS;
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goto out;
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}
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new_rate = clk_predict_rate_from_parent(c, parent);
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old_rate = clk_get_rate_locked(c);
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ret = c->ops->set_parent(c, parent);
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if (ret)
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goto out;
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out:
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spin_unlock_irqrestore(&c->spinlock, flags);
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return ret;
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}
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EXPORT_SYMBOL(clk_set_parent);
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struct clk *clk_get_parent(struct clk *c)
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{
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return c->parent;
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}
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EXPORT_SYMBOL(clk_get_parent);
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int clk_set_rate_locked(struct clk *c, unsigned long rate)
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{
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long new_rate;
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if (!c->ops || !c->ops->set_rate)
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return -ENOSYS;
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if (rate > c->max_rate)
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rate = c->max_rate;
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if (c->ops && c->ops->round_rate) {
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new_rate = c->ops->round_rate(c, rate);
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if (new_rate < 0)
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return new_rate;
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rate = new_rate;
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}
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return c->ops->set_rate(c, rate);
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}
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int clk_set_rate(struct clk *c, unsigned long rate)
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{
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int ret;
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unsigned long flags;
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spin_lock_irqsave(&c->spinlock, flags);
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ret = clk_set_rate_locked(c, rate);
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spin_unlock_irqrestore(&c->spinlock, flags);
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return ret;
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}
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EXPORT_SYMBOL(clk_set_rate);
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/* Must be called with clocks lock and all indvidual clock locks held */
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unsigned long clk_get_rate_all_locked(struct clk *c)
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{
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u64 rate;
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int mul = 1;
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int div = 1;
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struct clk *p = c;
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while (p) {
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c = p;
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if (c->mul != 0 && c->div != 0) {
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mul *= c->mul;
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div *= c->div;
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}
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p = c->parent;
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}
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rate = c->rate;
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rate *= mul;
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do_div(rate, div);
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return rate;
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}
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long clk_round_rate(struct clk *c, unsigned long rate)
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{
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unsigned long flags;
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long ret;
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spin_lock_irqsave(&c->spinlock, flags);
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if (!c->ops || !c->ops->round_rate) {
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ret = -ENOSYS;
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goto out;
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}
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if (rate > c->max_rate)
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rate = c->max_rate;
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ret = c->ops->round_rate(c, rate);
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out:
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spin_unlock_irqrestore(&c->spinlock, flags);
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return ret;
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}
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EXPORT_SYMBOL(clk_round_rate);
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static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
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{
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struct clk *c;
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struct clk *p;
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int ret = 0;
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c = tegra_get_clock_by_name(table->name);
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if (!c) {
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pr_warning("Unable to initialize clock %s\n",
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table->name);
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return -ENODEV;
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}
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if (table->parent) {
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p = tegra_get_clock_by_name(table->parent);
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if (!p) {
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pr_warning("Unable to find parent %s of clock %s\n",
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table->parent, table->name);
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return -ENODEV;
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}
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if (c->parent != p) {
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ret = clk_set_parent(c, p);
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if (ret) {
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pr_warning("Unable to set parent %s of clock %s: %d\n",
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table->parent, table->name, ret);
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return -EINVAL;
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}
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}
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}
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if (table->rate && table->rate != clk_get_rate(c)) {
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ret = clk_set_rate(c, table->rate);
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if (ret) {
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pr_warning("Unable to set clock %s to rate %lu: %d\n",
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table->name, table->rate, ret);
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return -EINVAL;
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}
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}
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if (table->enabled) {
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ret = clk_enable(c);
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if (ret) {
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pr_warning("Unable to enable clock %s: %d\n",
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table->name, ret);
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return -EINVAL;
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}
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}
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return 0;
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}
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void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
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{
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for (; table->name; table++)
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tegra_clk_init_one_from_table(table);
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}
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EXPORT_SYMBOL(tegra_clk_init_from_table);
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void tegra_periph_reset_deassert(struct clk *c)
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{
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BUG_ON(!c->ops->reset);
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c->ops->reset(c, false);
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}
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EXPORT_SYMBOL(tegra_periph_reset_deassert);
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void tegra_periph_reset_assert(struct clk *c)
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{
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BUG_ON(!c->ops->reset);
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c->ops->reset(c, true);
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}
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EXPORT_SYMBOL(tegra_periph_reset_assert);
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/* Several extended clock configuration bits (e.g., clock routing, clock
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* phase control) are included in PLL and peripheral clock source
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* registers. */
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int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
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{
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&c->spinlock, flags);
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if (!c->ops || !c->ops->clk_cfg_ex) {
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ret = -ENOSYS;
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goto out;
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}
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ret = c->ops->clk_cfg_ex(c, p, setting);
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out:
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spin_unlock_irqrestore(&c->spinlock, flags);
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return ret;
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}
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#ifdef CONFIG_DEBUG_FS
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static int __clk_lock_all_spinlocks(void)
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{
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struct clk *c;
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list_for_each_entry(c, &clocks, node)
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if (!spin_trylock(&c->spinlock))
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goto unlock_spinlocks;
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return 0;
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unlock_spinlocks:
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list_for_each_entry_continue_reverse(c, &clocks, node)
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spin_unlock(&c->spinlock);
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return -EAGAIN;
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}
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static void __clk_unlock_all_spinlocks(void)
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{
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struct clk *c;
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list_for_each_entry_reverse(c, &clocks, node)
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spin_unlock(&c->spinlock);
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}
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/*
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* This function retries until it can take all locks, and may take
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* an arbitrarily long time to complete.
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* Must be called with irqs enabled, returns with irqs disabled
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* Must be called with clock_list_lock held
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*/
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static void clk_lock_all(void)
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{
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int ret;
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retry:
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local_irq_disable();
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ret = __clk_lock_all_spinlocks();
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if (ret)
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goto failed_spinlocks;
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/* All locks taken successfully, return */
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return;
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failed_spinlocks:
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local_irq_enable();
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yield();
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goto retry;
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}
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/*
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* Unlocks all clocks after a clk_lock_all
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* Must be called with irqs disabled, returns with irqs enabled
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* Must be called with clock_list_lock held
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*/
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static void clk_unlock_all(void)
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{
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__clk_unlock_all_spinlocks();
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local_irq_enable();
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}
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static struct dentry *clk_debugfs_root;
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static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
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{
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struct clk *child;
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const char *state = "uninit";
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char div[8] = {0};
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if (c->state == ON)
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state = "on";
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else if (c->state == OFF)
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state = "off";
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if (c->mul != 0 && c->div != 0) {
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if (c->mul > c->div) {
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int mul = c->mul / c->div;
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int mul2 = (c->mul * 10 / c->div) % 10;
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int mul3 = (c->mul * 10) % c->div;
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if (mul2 == 0 && mul3 == 0)
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snprintf(div, sizeof(div), "x%d", mul);
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else if (mul3 == 0)
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snprintf(div, sizeof(div), "x%d.%d", mul, mul2);
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else
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snprintf(div, sizeof(div), "x%d.%d..", mul, mul2);
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} else {
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snprintf(div, sizeof(div), "%d%s", c->div / c->mul,
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(c->div % c->mul) ? ".5" : "");
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}
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}
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seq_printf(s, "%*s%c%c%-*s %-6s %-3d %-8s %-10lu\n",
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level * 3 + 1, "",
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c->rate > c->max_rate ? '!' : ' ',
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!c->set ? '*' : ' ',
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30 - level * 3, c->name,
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state, c->refcnt, div, clk_get_rate_all_locked(c));
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list_for_each_entry(child, &clocks, node) {
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if (child->parent != c)
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continue;
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clock_tree_show_one(s, child, level + 1);
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}
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}
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static int clock_tree_show(struct seq_file *s, void *data)
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{
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struct clk *c;
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seq_printf(s, " clock state ref div rate\n");
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seq_printf(s, "--------------------------------------------------------------\n");
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mutex_lock(&clock_list_lock);
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clk_lock_all();
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list_for_each_entry(c, &clocks, node)
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if (c->parent == NULL)
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clock_tree_show_one(s, c, 0);
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clk_unlock_all();
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mutex_unlock(&clock_list_lock);
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return 0;
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}
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static int clock_tree_open(struct inode *inode, struct file *file)
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{
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return single_open(file, clock_tree_show, inode->i_private);
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}
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static const struct file_operations clock_tree_fops = {
|
||||
.open = clock_tree_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static int possible_parents_show(struct seq_file *s, void *data)
|
||||
{
|
||||
struct clk *c = s->private;
|
||||
int i;
|
||||
|
||||
for (i = 0; c->inputs[i].input; i++) {
|
||||
char *first = (i == 0) ? "" : " ";
|
||||
seq_printf(s, "%s%s", first, c->inputs[i].input->name);
|
||||
}
|
||||
seq_printf(s, "\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int possible_parents_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, possible_parents_show, inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations possible_parents_fops = {
|
||||
.open = possible_parents_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static int clk_debugfs_register_one(struct clk *c)
|
||||
{
|
||||
struct dentry *d;
|
||||
|
||||
d = debugfs_create_dir(c->name, clk_debugfs_root);
|
||||
if (!d)
|
||||
return -ENOMEM;
|
||||
c->dent = d;
|
||||
|
||||
d = debugfs_create_u8("refcnt", S_IRUGO, c->dent, (u8 *)&c->refcnt);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
|
||||
d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
|
||||
d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
|
||||
if (c->inputs) {
|
||||
d = debugfs_create_file("possible_parents", S_IRUGO, c->dent,
|
||||
c, &possible_parents_fops);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_out:
|
||||
debugfs_remove_recursive(c->dent);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static int clk_debugfs_register(struct clk *c)
|
||||
{
|
||||
int err;
|
||||
struct clk *pa = c->parent;
|
||||
|
||||
if (pa && !pa->dent) {
|
||||
err = clk_debugfs_register(pa);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
if (!c->dent) {
|
||||
err = clk_debugfs_register_one(c);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init tegra_clk_debugfs_init(void)
|
||||
{
|
||||
struct clk *c;
|
||||
struct dentry *d;
|
||||
int err = -ENOMEM;
|
||||
|
||||
d = debugfs_create_dir("clock", NULL);
|
||||
if (!d)
|
||||
return -ENOMEM;
|
||||
clk_debugfs_root = d;
|
||||
|
||||
d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
|
||||
&clock_tree_fops);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
|
||||
list_for_each_entry(c, &clocks, node) {
|
||||
err = clk_debugfs_register(c);
|
||||
if (err)
|
||||
goto err_out;
|
||||
}
|
||||
return 0;
|
||||
err_out:
|
||||
debugfs_remove_recursive(clk_debugfs_root);
|
||||
return err;
|
||||
}
|
||||
#endif
|
||||
#else
|
||||
|
||||
void tegra_clk_add(struct clk *clk)
|
||||
{
|
||||
struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
|
||||
|
|
@ -793,4 +162,3 @@ int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
|
|||
out:
|
||||
return ret;
|
||||
}
|
||||
#endif /* !CONFIG_COMMON_CLK */
|
||||
|
|
|
|||
|
|
@ -24,7 +24,6 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <mach/clk.h>
|
||||
|
||||
|
|
@ -54,12 +53,8 @@
|
|||
#define ENABLE_ON_INIT (1 << 28)
|
||||
#define PERIPH_ON_APB (1 << 29)
|
||||
|
||||
struct clk;
|
||||
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
struct clk_tegra;
|
||||
#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
|
||||
#endif
|
||||
|
||||
struct clk_mux_sel {
|
||||
struct clk *input;
|
||||
|
|
@ -81,82 +76,6 @@ enum clk_state {
|
|||
OFF,
|
||||
};
|
||||
|
||||
#ifndef CONFIG_COMMON_CLK
|
||||
struct clk_ops {
|
||||
void (*init)(struct clk *);
|
||||
int (*enable)(struct clk *);
|
||||
void (*disable)(struct clk *);
|
||||
int (*set_parent)(struct clk *, struct clk *);
|
||||
int (*set_rate)(struct clk *, unsigned long);
|
||||
long (*round_rate)(struct clk *, unsigned long);
|
||||
void (*reset)(struct clk *, bool);
|
||||
int (*clk_cfg_ex)(struct clk *,
|
||||
enum tegra_clk_ex_param, u32);
|
||||
};
|
||||
|
||||
struct clk {
|
||||
/* node for master clocks list */
|
||||
struct list_head node; /* node for list of all clocks */
|
||||
struct clk_lookup lookup;
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
struct dentry *dent;
|
||||
#endif
|
||||
bool set;
|
||||
struct clk_ops *ops;
|
||||
unsigned long rate;
|
||||
unsigned long max_rate;
|
||||
unsigned long min_rate;
|
||||
u32 flags;
|
||||
const char *name;
|
||||
|
||||
u32 refcnt;
|
||||
enum clk_state state;
|
||||
struct clk *parent;
|
||||
u32 div;
|
||||
u32 mul;
|
||||
|
||||
const struct clk_mux_sel *inputs;
|
||||
u32 reg;
|
||||
u32 reg_shift;
|
||||
|
||||
struct list_head shared_bus_list;
|
||||
|
||||
union {
|
||||
struct {
|
||||
unsigned int clk_num;
|
||||
} periph;
|
||||
struct {
|
||||
unsigned long input_min;
|
||||
unsigned long input_max;
|
||||
unsigned long cf_min;
|
||||
unsigned long cf_max;
|
||||
unsigned long vco_min;
|
||||
unsigned long vco_max;
|
||||
const struct clk_pll_freq_table *freq_table;
|
||||
int lock_delay;
|
||||
unsigned long fixed_rate;
|
||||
} pll;
|
||||
struct {
|
||||
u32 sel;
|
||||
u32 reg_mask;
|
||||
} mux;
|
||||
struct {
|
||||
struct clk *main;
|
||||
struct clk *backup;
|
||||
} cpu;
|
||||
struct {
|
||||
struct list_head node;
|
||||
bool enabled;
|
||||
unsigned long rate;
|
||||
} shared_bus_user;
|
||||
} u;
|
||||
|
||||
spinlock_t spinlock;
|
||||
};
|
||||
|
||||
#else
|
||||
|
||||
struct clk_tegra {
|
||||
/* node for master clocks list */
|
||||
struct list_head node; /* node for list of all clocks */
|
||||
|
|
@ -212,7 +131,6 @@ struct clk_tegra {
|
|||
void (*reset)(struct clk_hw *, bool);
|
||||
int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
|
||||
};
|
||||
#endif /* !CONFIG_COMMON_CLK */
|
||||
|
||||
struct clk_duplicate {
|
||||
const char *name;
|
||||
|
|
@ -226,13 +144,6 @@ struct tegra_clk_init_table {
|
|||
bool enabled;
|
||||
};
|
||||
|
||||
#ifndef CONFIG_COMMON_CLK
|
||||
void clk_init(struct clk *clk);
|
||||
unsigned long clk_get_rate_locked(struct clk *c);
|
||||
int clk_set_rate_locked(struct clk *c, unsigned long rate);
|
||||
int clk_reparent(struct clk *c, struct clk *parent);
|
||||
#endif /* !CONFIG_COMMON_CLK */
|
||||
|
||||
void tegra_clk_add(struct clk *c);
|
||||
void tegra2_init_clocks(void);
|
||||
void tegra30_init_clocks(void);
|
||||
|
|
|
|||
|
|
@ -152,8 +152,5 @@ void __init tegra30_init_early(void)
|
|||
|
||||
void __init tegra_init_late(void)
|
||||
{
|
||||
#ifndef CONFIG_COMMON_CLK
|
||||
tegra_clk_debugfs_init();
|
||||
#endif
|
||||
tegra_powergate_debugfs_init();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue