UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

ARM: dts: STi: Add fake reg property for usb2_picophyX nodes 

Add fake reg property for usb2_picophy nodes.
This allows to fix the following warning when compiling dtb
with W=1 option :

arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /soc/phy2 missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /soc/phy3 missing or empty reg/ranges property

arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /soc/phy2 missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /soc/phy3 missing or empty reg/ranges property

arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /soc/phy2 missing or empty reg/ranges property
arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /soc/phy3 missing or empty reg/ranges property

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrice Chotard 2018-01-19 11:18:19 +01:00
parent a388871750
commit 1d91958fbe
5 changed files with 14 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/stih407-family.dtsi
View File

@ -385,8 +385,9 @@
status = "disabled";
};
usb2_picophy0: phy1 {
usb2_picophy0: phy1@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0x100 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,

4
arch/arm/boot/dts/stih410-b2120.dts
View File

@ -37,11 +37,11 @@
sd-uhs-ddr50;
};
usb2_picophy1: phy2 {
usb2_picophy1: phy2@0 {
status = "okay";
};
usb2_picophy2: phy3 {
usb2_picophy2: phy3@0 {
status = "okay";
};

4
arch/arm/boot/dts/stih410-b2260.dts
View File

@ -127,11 +127,11 @@
status = "okay";
};
usb2_picophy1: phy2 {
usb2_picophy1: phy2@0 {
status = "okay";
};
usb2_picophy2: phy3 {
usb2_picophy2: phy3@0 {
status = "okay";
};

6
arch/arm/boot/dts/stih410.dtsi
View File

@ -16,8 +16,9 @@
};
soc {
usb2_picophy1: phy2 {
usb2_picophy1: phy2@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xf8 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@ -27,8 +28,9 @@
status = "disabled";
};
usb2_picophy2: phy3 {
usb2_picophy2: phy3@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xfc 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,

6
arch/arm/boot/dts/stih418.dtsi
View File

@ -30,8 +30,9 @@
};
soc {
usb2_picophy1: phy2 {
usb2_picophy1: phy2@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xf8 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@ -39,8 +40,9 @@
reset-names = "global", "port";
};
usb2_picophy2: phy3 {
usb2_picophy2: phy3@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xfc 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,