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ARM: SoC fixes for v5.14 

Here are the patches for this week that came as the fallout of
 the merge window:
 
  - Two fixes for the NVidia memory controller driver
 
  - multiple defconfig files get patched to turn CONFIG_FB back on
    after that is no longer selected by CONFIG_DRM
 
  - ffa and scmpi firmware drivers fixes, mostly addressing compiler
    and documentation warnings
 
  - Platform specific fixes for device tree files on ASpeed,
    Renesas and NVidia SoC, mostly for recent regressions.
 
  - A workaround for a regression on the USB PHY with devlink when
    the usb-nop-xceiv driver is not available until the rootfs is
    mounted.
 
  - Device tree compiler warnings in Arm Versatile-AB
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'soc-fixes-5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
 "Here are the patches for this week that came as the fallout of the
  merge window:

   - Two fixes for the NVidia memory controller driver

   - multiple defconfig files get patched to turn CONFIG_FB back on
     after that is no longer selected by CONFIG_DRM

   - ffa and scmpi firmware drivers fixes, mostly addressing compiler
     and documentation warnings

   - Platform specific fixes for device tree files on ASpeed, Renesas
     and NVidia SoC, mostly for recent regressions.

   - A workaround for a regression on the USB PHY with devlink when the
     usb-nop-xceiv driver is not available until the rootfs is mounted.

   - Device tree compiler warnings in Arm Versatile-AB"

* tag 'soc-fixes-5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (35 commits)
  ARM: dts: versatile: Fix up interrupt controller node names
  ARM: multi_v7_defconfig: Make NOP_USB_XCEIV driver built-in
  ARM: configs: Update u8500_defconfig
  ARM: configs: Update Vexpress defconfig
  ARM: configs: Update Versatile defconfig
  ARM: configs: Update RealView defconfig
  ARM: configs: Update Integrator defconfig
  arm: Typo s/PCI_IXP4XX_LEGACY/IXP4XX_PCI_LEGACY/
  firmware: arm_scmi: Fix range check for the maximum number of pending messages
  firmware: arm_scmi: Avoid padding in sensor message structure
  firmware: arm_scmi: Fix kernel doc warnings about return values
  firmware: arm_scpi: Fix kernel doc warnings
  firmware: arm_scmi: Fix kernel doc warnings
  ARM: shmobile: defconfig: Restore graphical consoles
  firmware: arm_ffa: Fix a possible ffa_linux_errmap buffer overflow
  firmware: arm_ffa: Fix the comment style
  firmware: arm_ffa: Simplify probe function
  firmware: arm_ffa: Ensure drivers provide a probe function
  firmware: arm_scmi: Fix possible scmi_linux_errmap buffer overflow
  firmware: arm_scmi: Ensure drivers provide a probe function
  ...
This commit is contained in:
Linus Torvalds 2021-07-17 15:58:24 -07:00
parent ae14c63a9f 82a1c67554
commit 1d67c8d993
30 changed files with 418 additions and 215 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/iommu/arm,smmu.yaml
View File

@ -52,16 +52,14 @@ properties:
items:
- const: marvell,ap806-smmu-500
- const: arm,mmu-500
- description: NVIDIA SoCs that program two ARM MMU-500s identically
items:
- description: NVIDIA SoCs that require memory controller interaction
and may program multiple ARM MMU-500s identically with the memory
controller interleaving translations between multiple instances
for improved performance.
items:
- enum:
- const: nvidia,tegra194-smmu
- const: nvidia,tegra186-smmu
- nvidia,tegra194-smmu
- nvidia,tegra186-smmu
- const: nvidia,smmu-500
- items:
- const: arm,mmu-500

2
arch/arm/Kconfig
View File

@ -395,7 +395,7 @@ config ARCH_IXP4XX
select IXP4XX_IRQ
select IXP4XX_TIMER
# With the new PCI driver this is not needed
select NEED_MACH_IO_H if PCI_IXP4XX_LEGACY
select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY
select USB_EHCI_BIG_ENDIAN_DESC
select USB_EHCI_BIG_ENDIAN_MMIO
help

4
arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
View File

@ -4,6 +4,7 @@
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/interrupt-controller/irq.h>
/{
model = "ASRock E3C246D4I BMC";
@ -73,7 +74,8 @@
&vuart {
status = "okay";
aspeed,sirq-active-high;
aspeed,lpc-io-reg = <0x2f8>;
aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
};
&mac0 {

11
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
View File

@ -406,15 +406,15 @@
reg = <0x69>;
};
power-supply@6a {
compatible = "ibm,cffps";
reg = <0x6a>;
};
power-supply@6b {
compatible = "ibm,cffps";
reg = <0x6b>;
};
power-supply@6d {
compatible = "ibm,cffps";
reg = <0x6d>;
};
};
&i2c4 {
@ -2832,6 +2832,7 @@
&emmc {
status = "okay";
clk-phase-mmc-hs200 = <180>, <180>;
};
&fsim0 {

5
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
View File

@ -280,10 +280,7 @@
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z7*/ "","","","","","","","",
/*AA0-AA7*/ "","","","","","","","",
/*AB0-AB7*/ "","","","","","","","",
/*AC0-AC7*/ "","","","","","","","";
/*Z0-Z7*/ "","","","","","","","";
pin_mclr_vpp {
gpio-hog;

6
arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
View File

@ -136,10 +136,7 @@
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z7*/ "","","","","","","","",
/*AA0-AA7*/ "","","","","","","","",
/*AB0-AB7*/ "","","","","","","","",
/*AC0-AC7*/ "","","","","","","","";
/*Z0-Z7*/ "","","","","","","","";
};
&fmc {
@ -189,6 +186,7 @@
&emmc {
status = "okay";
clk-phase-mmc-hs200 = <36>, <270>;
};
&fsim0 {

5
arch/arm/boot/dts/versatile-ab.dts
View File

@ -195,16 +195,15 @@
#size-cells = <1>;
ranges;
vic: intc@10140000 {
vic: interrupt-controller@10140000 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x10140000 0x1000>;
clear-mask = <0xffffffff>;
valid-mask = <0xffffffff>;
};
sic: intc@10003000 {
sic: interrupt-controller@10003000 {
compatible = "arm,versatile-sic";
interrupt-controller;
#interrupt-cells = <1>;

2
arch/arm/boot/dts/versatile-pb.dts
View File

@ -7,7 +7,7 @@
amba {
/* The Versatile PB is using more SIC IRQ lines than the AB */
sic: intc@10003000 {
sic: interrupt-controller@10003000 {
clear-mask = <0xffffffff>;
/*
* Valid interrupt lines mask according to

5
arch/arm/configs/integrator_defconfig
View File

@ -57,10 +57,7 @@ CONFIG_DRM=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_PL111=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_MATROX=y
CONFIG_FB_MATROX_MILLENIUM=y
CONFIG_FB_MATROX_MYSTIQUE=y
CONFIG_FB=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_LOGO=y

2
arch/arm/configs/multi_v7_defconfig
View File

@ -821,7 +821,7 @@ CONFIG_USB_ISP1760=y
CONFIG_USB_HSIC_USB3503=y
CONFIG_AB8500_USB=y
CONFIG_KEYSTONE_USB_PHY=m
CONFIG_NOP_USB_XCEIV=m
CONFIG_NOP_USB_XCEIV=y
CONFIG_AM335X_PHY_USB=m
CONFIG_TWL6030_USB=m
CONFIG_USB_GPIO_VBUS=y

4
arch/arm/configs/realview_defconfig
View File

@ -64,11 +64,9 @@ CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_PL111=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_DRIVERS is not set

1
arch/arm/configs/shmobile_defconfig
View File

@ -135,6 +135,7 @@ CONFIG_DRM_SII902X=y
CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_I2C_ADV7511=y
CONFIG_DRM_I2C_ADV7511_AUDIO=y
CONFIG_FB=y
CONFIG_FB_SH_MOBILE_LCDC=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_AS3711=y

5
arch/arm/configs/u8500_defconfig
View File

@ -61,6 +61,10 @@ CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
CONFIG_TOUCHSCREEN_BU21013=y
CONFIG_TOUCHSCREEN_CY8CTMA140=y
CONFIG_TOUCHSCREEN_CYTTSP_CORE=y
CONFIG_TOUCHSCREEN_CYTTSP_SPI=y
CONFIG_TOUCHSCREEN_MMS114=y
CONFIG_TOUCHSCREEN_ZINITIX=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_AB8500_PONKEY=y
CONFIG_INPUT_GPIO_VIBRA=y
@ -100,6 +104,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=y
CONFIG_DRM_PANEL_SONY_ACX424AKP=y
CONFIG_DRM_LIMA=y
CONFIG_DRM_MCDE=y
CONFIG_FB=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_KTD253=y
CONFIG_BACKLIGHT_GPIO=y

4
arch/arm/configs/versatile_defconfig
View File

@ -60,7 +60,7 @@ CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_PL111=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_LOGO=y
CONFIG_SOUND=y
@ -88,8 +88,6 @@ CONFIG_NFSD=y
CONFIG_NFSD_V3=y
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_ISO8859_1=m
CONFIG_FONTS=y
CONFIG_FONT_ACORN_8x8=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y

17
arch/arm/configs/vexpress_defconfig
View File

@ -11,9 +11,6 @@ CONFIG_CPUSETS=y
# CONFIG_NET_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_PROFILING=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_VEXPRESS_DCSCB=y
CONFIG_ARCH_VEXPRESS_TC2_PM=y
@ -23,14 +20,17 @@ CONFIG_MCPM=y
CONFIG_VMSPLIT_2G=y
CONFIG_NR_CPUS=8
CONFIG_ARM_PSCI=y
CONFIG_CMA=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyAMA0"
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@ -43,7 +43,6 @@ CONFIG_IP_PNP_BOOTP=y
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_DEVTMPFS=y
CONFIG_DMA_CMA=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
@ -59,7 +58,6 @@ CONFIG_VIRTIO_BLK=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_VIRTIO=y
CONFIG_ATA=y
# CONFIG_SATA_PMP is not set
CONFIG_NETDEVICES=y
CONFIG_VIRTIO_NET=y
CONFIG_SMC91X=y
@ -81,11 +79,9 @@ CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_SII902X=y
CONFIG_DRM_PL111=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_DRIVERS is not set
@ -136,10 +132,11 @@ CONFIG_ROOT_NFS=y
CONFIG_9P_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_CRYPTO_HW is not set
CONFIG_DMA_CMA=y
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_DEBUG_USER=y
# CONFIG_CRYPTO_HW is not set

13
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View File

@ -948,6 +948,10 @@
<&bpmp TEGRA194_CLK_XUSB_SS>,
<&bpmp TEGRA194_CLK_XUSB_FS>;
clock-names = "dev", "ss", "ss_src", "fs_src";
interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
power-domain-names = "dev", "ss";
@ -977,6 +981,10 @@
"xusb_ss", "xusb_ss_src", "xusb_hs_src",
"xusb_fs_src", "pll_u_480m", "clk_m",
"pll_e";
interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
@ -2469,6 +2477,11 @@
* for 8x and 11.025x sample rate streams.
*/
assigned-clock-rates = <258000000>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_APE>;
};
tcu: tcu {

4
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@ -82,10 +82,10 @@
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>;
clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_CLK_SCIF0>;
resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
status = "disabled";
};

79
drivers/clk/renesas/r9a07g044-cpg.c
View File

@ -30,8 +30,9 @@ enum clk_ids {
CLK_PLL2_DIV20,
CLK_PLL3,
CLK_PLL3_DIV2,
CLK_PLL3_DIV2_4,
CLK_PLL3_DIV2_4_2,
CLK_PLL3_DIV4,
CLK_PLL3_DIV8,
CLK_PLL4,
CLK_PLL5,
CLK_PLL5_DIV2,
@ -42,12 +43,13 @@ enum clk_ids {
};
/* Divider tables */
static const struct clk_div_table dtable_3b[] = {
static const struct clk_div_table dtable_1_32[] = {
{0, 1},
{1, 2},
{2, 4},
{3, 8},
{4, 32},
{0, 0},
};
static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
@ -66,47 +68,56 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8),
/* Core output clk */
DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
dtable_3b, CLK_DIVIDER_HIWORD_MASK),
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK),
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
};
static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
DEF_MOD("gic", R9A07G044_CLK_GIC600,
R9A07G044_CLK_P1,
0x514, BIT(0), (BIT(0) | BIT(1))),
DEF_MOD("ia55", R9A07G044_CLK_IA55,
R9A07G044_CLK_P1,
0x518, (BIT(0) | BIT(1)), BIT(0)),
DEF_MOD("scif0", R9A07G044_CLK_SCIF0,
R9A07G044_CLK_P0,
0x584, BIT(0), BIT(0)),
DEF_MOD("scif1", R9A07G044_CLK_SCIF1,
R9A07G044_CLK_P0,
0x584, BIT(1), BIT(1)),
DEF_MOD("scif2", R9A07G044_CLK_SCIF2,
R9A07G044_CLK_P0,
0x584, BIT(2), BIT(2)),
DEF_MOD("scif3", R9A07G044_CLK_SCIF3,
R9A07G044_CLK_P0,
0x584, BIT(3), BIT(3)),
DEF_MOD("scif4", R9A07G044_CLK_SCIF4,
R9A07G044_CLK_P0,
0x584, BIT(4), BIT(4)),
DEF_MOD("sci0", R9A07G044_CLK_SCI0,
R9A07G044_CLK_P0,
0x588, BIT(0), BIT(0)),
DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
0x514, 0),
DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
0x518, 0),
DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
0x518, 1),
DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
0x584, 0),
DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
0x584, 1),
DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
0x584, 2),
DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
0x584, 3),
DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
0x584, 4),
DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
0x588, 0),
};
static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
};
static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A07G044_CLK_GIC600,
MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
};
const struct rzg2l_cpg_info r9a07g044_cpg_info = {
@ -123,5 +134,9 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
/* Module Clocks */
.mod_clks = r9a07g044_mod_clks,
.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
.num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1,
.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
/* Resets */
.resets = r9a07g044_resets,
.num_resets = ARRAY_SIZE(r9a07g044_resets),
};

108
drivers/clk/renesas/renesas-rzg2l-cpg.c
View File

@ -47,9 +47,9 @@
#define SDIV(val) DIV_RSMASK(val, 0, 0x7)
#define CLK_ON_R(reg) (reg)
#define CLK_MON_R(reg) (0x680 - 0x500 + (reg))
#define CLK_RST_R(reg) (0x800 - 0x500 + (reg))
#define CLK_MRST_R(reg) (0x980 - 0x500 + (reg))
#define CLK_MON_R(reg) (0x180 + (reg))
#define CLK_RST_R(reg) (reg)
#define CLK_MRST_R(reg) (0x180 + (reg))
#define GET_REG_OFFSET(val) ((val >> 20) & 0xfff)
#define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff)
@ -78,6 +78,7 @@ struct rzg2l_cpg_priv {
struct clk **clks;
unsigned int num_core_clks;
unsigned int num_mod_clks;
unsigned int num_resets;
unsigned int last_dt_core_clk;
struct raw_notifier_head notifiers;
@ -315,15 +316,13 @@ fail:
*
* @hw: handle between common and hardware-specific interfaces
* @off: register offset
* @onoff: ON/MON bits
* @reset: reset bits
* @bit: ON/MON bit
* @priv: CPG/MSTP private data
*/
struct mstp_clock {
struct clk_hw hw;
u16 off;
u8 onoff;
u8 reset;
u8 bit;
struct rzg2l_cpg_priv *priv;
};
@ -337,6 +336,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
struct device *dev = priv->dev;
unsigned long flags;
unsigned int i;
u32 bitmask = BIT(clock->bit);
u32 value;
if (!clock->off) {
@ -349,9 +349,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
spin_lock_irqsave(&priv->rmw_lock, flags);
if (enable)
value = (clock->onoff << 16) | clock->onoff;
value = (bitmask << 16) | bitmask;
else
value = clock->onoff << 16;
value = bitmask << 16;
writel(value, priv->base + CLK_ON_R(reg));
spin_unlock_irqrestore(&priv->rmw_lock, flags);
@ -360,7 +360,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
return 0;
for (i = 1000; i > 0; --i) {
if (((readl(priv->base + CLK_MON_R(reg))) & clock->onoff))
if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
break;
cpu_relax();
}
@ -388,6 +388,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
{
struct mstp_clock *clock = to_mod_clock(hw);
struct rzg2l_cpg_priv *priv = clock->priv;
u32 bitmask = BIT(clock->bit);
u32 value;
if (!clock->off) {
@ -397,7 +398,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
value = readl(priv->base + CLK_MON_R(clock->off));
return !(value & clock->onoff);
return !(value & bitmask);
}
static const struct clk_ops rzg2l_mod_clock_ops = {
@ -457,8 +458,7 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
init.num_parents = 1;
clock->off = mod->off;
clock->onoff = mod->onoff;
clock->reset = mod->reset;
clock->bit = mod->bit;
clock->priv = priv;
clock->hw.init = &init;
@ -483,12 +483,11 @@ static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->mod_clks[id].off;
u32 dis = info->mod_clks[id].reset;
unsigned int reg = info->resets[id].off;
u32 dis = BIT(info->resets[id].bit);
u32 we = dis << 16;
dev_dbg(rcdev->dev, "reset name:%s id:%ld offset:0x%x\n",
info->mod_clks[id].name, id, CLK_RST_R(reg));
dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
/* Reset module */
writel(we, priv->base + CLK_RST_R(reg));
@ -507,11 +506,10 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->mod_clks[id].off;
u32 value = info->mod_clks[id].reset << 16;
unsigned int reg = info->resets[id].off;
u32 value = BIT(info->resets[id].bit) << 16;
dev_dbg(rcdev->dev, "assert name:%s id:%ld offset:0x%x\n",
info->mod_clks[id].name, id, CLK_RST_R(reg));
dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
writel(value, priv->base + CLK_RST_R(reg));
return 0;
@ -522,12 +520,12 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->mod_clks[id].off;
u32 dis = info->mod_clks[id].reset;
unsigned int reg = info->resets[id].off;
u32 dis = BIT(info->resets[id].bit);
u32 value = (dis << 16) | dis;
dev_dbg(rcdev->dev, "deassert name:%s id:%ld offset:0x%x\n",
info->mod_clks[id].name, id, CLK_RST_R(reg));
dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id,
CLK_RST_R(reg));
writel(value, priv->base + CLK_RST_R(reg));
return 0;
@ -538,8 +536,8 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->mod_clks[id].off;
u32 bitmask = info->mod_clks[id].reset;
unsigned int reg = info->resets[id].off;
u32 bitmask = BIT(info->resets[id].bit);
return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
}
@ -554,9 +552,11 @@ static const struct reset_control_ops rzg2l_cpg_reset_ops = {
static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev,
const struct of_phandle_args *reset_spec)
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int id = reset_spec->args[0];
if (id >= rcdev->nr_resets) {
if (id >= rcdev->nr_resets || !info->resets[id].off) {
dev_err(rcdev->dev, "Invalid reset index %u\n", id);
return -EINVAL;
}
@ -571,7 +571,7 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
priv->rcdev.dev = priv->dev;
priv->rcdev.of_reset_n_cells = 1;
priv->rcdev.of_xlate = rzg2l_cpg_reset_xlate;
priv->rcdev.nr_resets = priv->num_mod_clks;
priv->rcdev.nr_resets = priv->num_resets;
return devm_reset_controller_register(priv->dev, &priv->rcdev);
}
@ -594,42 +594,49 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device
{
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
bool once = true;
struct clk *clk;
int error;
int i = 0;
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
&clkspec)) {
if (rzg2l_cpg_is_pm_clk(&clkspec))
goto found;
if (rzg2l_cpg_is_pm_clk(&clkspec)) {
if (once) {
once = false;
error = pm_clk_create(dev);
if (error) {
of_node_put(clkspec.np);
goto err;
}
}
clk = of_clk_get_from_provider(&clkspec);
of_node_put(clkspec.np);
if (IS_ERR(clk)) {
error = PTR_ERR(clk);
goto fail_destroy;
}
of_node_put(clkspec.np);
error = pm_clk_add_clk(dev, clk);
if (error) {
dev_err(dev, "pm_clk_add_clk failed %d\n",
error);
goto fail_put;
}
} else {
of_node_put(clkspec.np);
}
i++;
}
return 0;
found:
clk = of_clk_get_from_provider(&clkspec);
of_node_put(clkspec.np);
if (IS_ERR(clk))
return PTR_ERR(clk);
error = pm_clk_create(dev);
if (error)
goto fail_put;
error = pm_clk_add_clk(dev, clk);
if (error)
goto fail_destroy;
return 0;
fail_put:
clk_put(clk);
fail_destroy:
pm_clk_destroy(dev);
fail_put:
clk_put(clk);
err:
return error;
}
@ -692,6 +699,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
priv->clks = clks;
priv->num_core_clks = info->num_total_core_clks;
priv->num_mod_clks = info->num_hw_mod_clks;
priv->num_resets = info->num_resets;
priv->last_dt_core_clk = info->last_dt_core_clk;
for (i = 0; i < nclks; i++)

37
drivers/clk/renesas/renesas-rzg2l-cpg.h
View File

@ -21,6 +21,7 @@
#define DDIV_PACK(offset, bitpos, size) \
(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
/**
@ -76,26 +77,40 @@ enum clk_types {
* @id: clock index in array containing all Core and Module Clocks
* @parent: id of parent clock
* @off: register offset
* @onoff: ON/MON bits
* @reset: reset bits
* @bit: ON/MON bit
*/
struct rzg2l_mod_clk {
const char *name;
unsigned int id;
unsigned int parent;
u16 off;
u8 onoff;
u8 reset;
u8 bit;
};
#define DEF_MOD(_name, _id, _parent, _off, _onoff, _reset) \
[_id] = { \
#define DEF_MOD(_name, _id, _parent, _off, _bit) \
{ \
.name = _name, \
.id = MOD_CLK_BASE + _id, \
.id = MOD_CLK_BASE + (_id), \
.parent = (_parent), \
.off = (_off), \
.onoff = (_onoff), \
.reset = (_reset) \
.bit = (_bit), \
}
/**
* struct rzg2l_reset - Reset definitions
*
* @off: register offset
* @bit: reset bit
*/
struct rzg2l_reset {
u16 off;
u8 bit;
};
#define DEF_RST(_id, _off, _bit) \
[_id] = { \
.off = (_off), \
.bit = (_bit) \
}
/**
@ -126,6 +141,10 @@ struct rzg2l_cpg_info {
unsigned int num_mod_clks;
unsigned int num_hw_mod_clks;
/* Resets */
const struct rzg2l_reset *resets;
unsigned int num_resets;
/* Critical Module Clocks that should not be disabled */
const unsigned int *crit_mod_clks;
unsigned int num_crit_mod_clks;

6
drivers/firmware/arm_ffa/bus.c
View File

@ -46,9 +46,6 @@ static int ffa_device_probe(struct device *dev)
struct ffa_driver *ffa_drv = to_ffa_driver(dev->driver);
struct ffa_device *ffa_dev = to_ffa_dev(dev);
if (!ffa_device_match(dev, dev->driver))
return -ENODEV;
return ffa_drv->probe(ffa_dev);
}
@ -99,6 +96,9 @@ int ffa_driver_register(struct ffa_driver *driver, struct module *owner,
{
int ret;
if (!driver->probe)
return -EINVAL;
driver->driver.bus = &ffa_bus_type;
driver->driver.name = driver->name;
driver->driver.owner = owner;

8
drivers/firmware/arm_ffa/driver.c
View File

@ -120,7 +120,7 @@
#define PACK_TARGET_INFO(s, r) \
(FIELD_PREP(SENDER_ID_MASK, (s)) | FIELD_PREP(RECEIVER_ID_MASK, (r)))
/**
/*
* FF-A specification mentions explicitly about '4K pages'. This should
* not be confused with the kernel PAGE_SIZE, which is the translation
* granule kernel is configured and may be one among 4K, 16K and 64K.
@ -149,8 +149,10 @@ static const int ffa_linux_errmap[] = {
static inline int ffa_to_linux_errno(int errno)
{
if (errno < FFA_RET_SUCCESS && errno >= -ARRAY_SIZE(ffa_linux_errmap))
return ffa_linux_errmap[-errno];
int err_idx = -errno;
if (err_idx >= 0 && err_idx < ARRAY_SIZE(ffa_linux_errmap))
return ffa_linux_errmap[err_idx];
return -EINVAL;
}

8
drivers/firmware/arm_scmi/bus.c
View File

@ -104,11 +104,6 @@ static int scmi_dev_probe(struct device *dev)
{
struct scmi_driver *scmi_drv = to_scmi_driver(dev->driver);
struct scmi_device *scmi_dev = to_scmi_dev(dev);
const struct scmi_device_id *id;
id = scmi_dev_match_id(scmi_dev, scmi_drv);
if (!id)
return -ENODEV;
if (!scmi_dev->handle)
return -EPROBE_DEFER;
@ -139,6 +134,9 @@ int scmi_driver_register(struct scmi_driver *driver, struct module *owner,
{
int retval;
if (!driver->probe)
return -EINVAL;
retval = scmi_protocol_device_request(driver->id_table);
if (retval)
return retval;

14
drivers/firmware/arm_scmi/driver.c
View File

@ -47,7 +47,6 @@ enum scmi_error_codes {
SCMI_ERR_GENERIC = -8, /* Generic Error */
SCMI_ERR_HARDWARE = -9, /* Hardware Error */
SCMI_ERR_PROTOCOL = -10,/* Protocol Error */
SCMI_ERR_MAX
};
/* List of all SCMI devices active in system */
@ -166,8 +165,10 @@ static const int scmi_linux_errmap[] = {
static inline int scmi_to_linux_errno(int errno)
{
if (errno < SCMI_SUCCESS && errno > SCMI_ERR_MAX)
return scmi_linux_errmap[-errno];
int err_idx = -errno;
if (err_idx >= SCMI_SUCCESS && err_idx < ARRAY_SIZE(scmi_linux_errmap))
return scmi_linux_errmap[err_idx];
return -EIO;
}
@ -1025,8 +1026,9 @@ static int __scmi_xfer_info_init(struct scmi_info *sinfo,
const struct scmi_desc *desc = sinfo->desc;
/* Pre-allocated messages, no more than what hdr.seq can support */
if (WARN_ON(desc->max_msg >= MSG_TOKEN_MAX)) {
dev_err(dev, "Maximum message of %d exceeds supported %ld\n",
if (WARN_ON(!desc->max_msg || desc->max_msg > MSG_TOKEN_MAX)) {
dev_err(dev,
"Invalid maximum messages %d, not in range [1 - %lu]\n",
desc->max_msg, MSG_TOKEN_MAX);
return -EINVAL;
}
@ -1137,6 +1139,8 @@ scmi_txrx_setup(struct scmi_info *info, struct device *dev, int prot_id)
* @proto_id and @name: if device was still not existent it is created as a
* child of the specified SCMI instance @info and its transport properly
* initialized as usual.
*
* Return: A properly initialized scmi device, NULL otherwise.
*/
static inline struct scmi_device *
scmi_get_protocol_device(struct device_node *np, struct scmi_info *info,

4
drivers/firmware/arm_scmi/notify.c
View File

@ -1457,6 +1457,8 @@ static void scmi_devm_release_notifier(struct device *dev, void *res)
*
* Generic devres managed helper to register a notifier_block against a
* protocol event.
*
* Return: 0 on Success
*/
static int scmi_devm_notifier_register(struct scmi_device *sdev,
u8 proto_id, u8 evt_id,
@ -1523,6 +1525,8 @@ static int scmi_devm_notifier_match(struct device *dev, void *res, void *data)
* Generic devres managed helper to explicitly un-register a notifier_block
* against a protocol event, which was previously registered using the above
* @scmi_devm_notifier_register.
*
* Return: 0 on Success
*/
static int scmi_devm_notifier_unregister(struct scmi_device *sdev,
u8 proto_id, u8 evt_id,

6
drivers/firmware/arm_scmi/sensors.c
View File

@ -166,7 +166,8 @@ struct scmi_msg_sensor_reading_get {
struct scmi_resp_sensor_reading_complete {
__le32 id;
__le64 readings;
__le32 readings_low;
__le32 readings_high;
};
struct scmi_sensor_reading_resp {
@ -717,7 +718,8 @@ static int scmi_sensor_reading_get(const struct scmi_protocol_handle *ph,
resp = t->rx.buf;
if (le32_to_cpu(resp->id) == sensor_id)
*value = get_unaligned_le64(&resp->readings);
*value =
get_unaligned_le64(&resp->readings_low);
else
ret = -EPROTO;
}

236
include/dt-bindings/clock/r9a07g044-cpg.h
View File

@ -32,58 +32,188 @@
#define R9A07G044_OSCCLK 21
/* R9A07G044 Module Clocks */
#define R9A07G044_CLK_GIC600 0
#define R9A07G044_CLK_IA55 1
#define R9A07G044_CLK_SYC 2
#define R9A07G044_CLK_DMAC 3
#define R9A07G044_CLK_SYSC 4
#define R9A07G044_CLK_MTU 5
#define R9A07G044_CLK_GPT 6
#define R9A07G044_CLK_ETH0 7
#define R9A07G044_CLK_ETH1 8
#define R9A07G044_CLK_I2C0 9
#define R9A07G044_CLK_I2C1 10
#define R9A07G044_CLK_I2C2 11
#define R9A07G044_CLK_I2C3 12
#define R9A07G044_CLK_SCIF0 13
#define R9A07G044_CLK_SCIF1 14
#define R9A07G044_CLK_SCIF2 15
#define R9A07G044_CLK_SCIF3 16
#define R9A07G044_CLK_SCIF4 17
#define R9A07G044_CLK_SCI0 18
#define R9A07G044_CLK_SCI1 19
#define R9A07G044_CLK_GPIO 20
#define R9A07G044_CLK_SDHI0 21
#define R9A07G044_CLK_SDHI1 22
#define R9A07G044_CLK_USB0 23
#define R9A07G044_CLK_USB1 24
#define R9A07G044_CLK_CANFD 25
#define R9A07G044_CLK_SSI0 26
#define R9A07G044_CLK_SSI1 27
#define R9A07G044_CLK_SSI2 28
#define R9A07G044_CLK_SSI3 29
#define R9A07G044_CLK_MHU 30
#define R9A07G044_CLK_OSTM0 31
#define R9A07G044_CLK_OSTM1 32
#define R9A07G044_CLK_OSTM2 33
#define R9A07G044_CLK_WDT0 34
#define R9A07G044_CLK_WDT1 35
#define R9A07G044_CLK_WDT2 36
#define R9A07G044_CLK_WDT_PON 37
#define R9A07G044_CLK_GPU 38
#define R9A07G044_CLK_ISU 39
#define R9A07G044_CLK_H264 40
#define R9A07G044_CLK_CRU 41
#define R9A07G044_CLK_MIPI_DSI 42
#define R9A07G044_CLK_LCDC 43
#define R9A07G044_CLK_SRC 44
#define R9A07G044_CLK_RSPI0 45
#define R9A07G044_CLK_RSPI1 46
#define R9A07G044_CLK_RSPI2 47
#define R9A07G044_CLK_ADC 48
#define R9A07G044_CLK_TSU_PCLK 49
#define R9A07G044_CLK_SPI 50
#define R9A07G044_CLK_MIPI_DSI_V 51
#define R9A07G044_CLK_MIPI_DSI_PIN 52
#define R9A07G044_CA55_SCLK 0
#define R9A07G044_CA55_PCLK 1
#define R9A07G044_CA55_ATCLK 2
#define R9A07G044_CA55_GICCLK 3
#define R9A07G044_CA55_PERICLK 4
#define R9A07G044_CA55_ACLK 5
#define R9A07G044_CA55_TSCLK 6
#define R9A07G044_GIC600_GICCLK 7
#define R9A07G044_IA55_CLK 8
#define R9A07G044_IA55_PCLK 9
#define R9A07G044_MHU_PCLK 10
#define R9A07G044_SYC_CNT_CLK 11
#define R9A07G044_DMAC_ACLK 12
#define R9A07G044_DMAC_PCLK 13
#define R9A07G044_OSTM0_PCLK 14
#define R9A07G044_OSTM1_PCLK 15
#define R9A07G044_OSTM2_PCLK 16
#define R9A07G044_MTU_X_MCK_MTU3 17
#define R9A07G044_POE3_CLKM_POE 18
#define R9A07G044_GPT_PCLK 19
#define R9A07G044_POEG_A_CLKP 20
#define R9A07G044_POEG_B_CLKP 21
#define R9A07G044_POEG_C_CLKP 22
#define R9A07G044_POEG_D_CLKP 23
#define R9A07G044_WDT0_PCLK 24
#define R9A07G044_WDT0_CLK 25
#define R9A07G044_WDT1_PCLK 26
#define R9A07G044_WDT1_CLK 27
#define R9A07G044_WDT2_PCLK 28
#define R9A07G044_WDT2_CLK 29
#define R9A07G044_SPI_CLK2 30
#define R9A07G044_SPI_CLK 31
#define R9A07G044_SDHI0_IMCLK 32
#define R9A07G044_SDHI0_IMCLK2 33
#define R9A07G044_SDHI0_CLK_HS 34
#define R9A07G044_SDHI0_ACLK 35
#define R9A07G044_SDHI1_IMCLK 36
#define R9A07G044_SDHI1_IMCLK2 37
#define R9A07G044_SDHI1_CLK_HS 38
#define R9A07G044_SDHI1_ACLK 39
#define R9A07G044_GPU_CLK 40
#define R9A07G044_GPU_AXI_CLK 41
#define R9A07G044_GPU_ACE_CLK 42
#define R9A07G044_ISU_ACLK 43
#define R9A07G044_ISU_PCLK 44
#define R9A07G044_H264_CLK_A 45
#define R9A07G044_H264_CLK_P 46
#define R9A07G044_CRU_SYSCLK 47
#define R9A07G044_CRU_VCLK 48
#define R9A07G044_CRU_PCLK 49
#define R9A07G044_CRU_ACLK 50
#define R9A07G044_MIPI_DSI_PLLCLK 51
#define R9A07G044_MIPI_DSI_SYSCLK 52
#define R9A07G044_MIPI_DSI_ACLK 53
#define R9A07G044_MIPI_DSI_PCLK 54
#define R9A07G044_MIPI_DSI_VCLK 55
#define R9A07G044_MIPI_DSI_LPCLK 56
#define R9A07G044_LCDC_CLK_A 57
#define R9A07G044_LCDC_CLK_P 58
#define R9A07G044_LCDC_CLK_D 59
#define R9A07G044_SSI0_PCLK2 60
#define R9A07G044_SSI0_PCLK_SFR 61
#define R9A07G044_SSI1_PCLK2 62
#define R9A07G044_SSI1_PCLK_SFR 63
#define R9A07G044_SSI2_PCLK2 64
#define R9A07G044_SSI2_PCLK_SFR 65
#define R9A07G044_SSI3_PCLK2 66
#define R9A07G044_SSI3_PCLK_SFR 67
#define R9A07G044_SRC_CLKP 68
#define R9A07G044_USB_U2H0_HCLK 69
#define R9A07G044_USB_U2H1_HCLK 70
#define R9A07G044_USB_U2P_EXR_CPUCLK 71
#define R9A07G044_USB_PCLK 72
#define R9A07G044_ETH0_CLK_AXI 73
#define R9A07G044_ETH0_CLK_CHI 74
#define R9A07G044_ETH1_CLK_AXI 75
#define R9A07G044_ETH1_CLK_CHI 76
#define R9A07G044_I2C0_PCLK 77
#define R9A07G044_I2C1_PCLK 78
#define R9A07G044_I2C2_PCLK 79
#define R9A07G044_I2C3_PCLK 80
#define R9A07G044_SCIF0_CLK_PCK 81
#define R9A07G044_SCIF1_CLK_PCK 82
#define R9A07G044_SCIF2_CLK_PCK 83
#define R9A07G044_SCIF3_CLK_PCK 84
#define R9A07G044_SCIF4_CLK_PCK 85
#define R9A07G044_SCI0_CLKP 86
#define R9A07G044_SCI1_CLKP 87
#define R9A07G044_IRDA_CLKP 88
#define R9A07G044_RSPI0_CLKB 89
#define R9A07G044_RSPI1_CLKB 90
#define R9A07G044_RSPI2_CLKB 91
#define R9A07G044_CANFD_PCLK 92
#define R9A07G044_GPIO_HCLK 93
#define R9A07G044_ADC_ADCLK 94
#define R9A07G044_ADC_PCLK 95
#define R9A07G044_TSU_PCLK 96
/* R9A07G044 Resets */
#define R9A07G044_CA55_RST_1_0 0
#define R9A07G044_CA55_RST_1_1 1
#define R9A07G044_CA55_RST_3_0 2
#define R9A07G044_CA55_RST_3_1 3
#define R9A07G044_CA55_RST_4 4
#define R9A07G044_CA55_RST_5 5
#define R9A07G044_CA55_RST_6 6
#define R9A07G044_CA55_RST_7 7
#define R9A07G044_CA55_RST_8 8
#define R9A07G044_CA55_RST_9 9
#define R9A07G044_CA55_RST_10 10
#define R9A07G044_CA55_RST_11 11
#define R9A07G044_CA55_RST_12 12
#define R9A07G044_GIC600_GICRESET_N 13
#define R9A07G044_GIC600_DBG_GICRESET_N 14
#define R9A07G044_IA55_RESETN 15
#define R9A07G044_MHU_RESETN 16
#define R9A07G044_DMAC_ARESETN 17
#define R9A07G044_DMAC_RST_ASYNC 18
#define R9A07G044_SYC_RESETN 19
#define R9A07G044_OSTM0_PRESETZ 20
#define R9A07G044_OSTM1_PRESETZ 21
#define R9A07G044_OSTM2_PRESETZ 22
#define R9A07G044_MTU_X_PRESET_MTU3 23
#define R9A07G044_POE3_RST_M_REG 24
#define R9A07G044_GPT_RST_C 25
#define R9A07G044_POEG_A_RST 26
#define R9A07G044_POEG_B_RST 27
#define R9A07G044_POEG_C_RST 28
#define R9A07G044_POEG_D_RST 29
#define R9A07G044_WDT0_PRESETN 30
#define R9A07G044_WDT1_PRESETN 31
#define R9A07G044_WDT2_PRESETN 32
#define R9A07G044_SPI_RST 33
#define R9A07G044_SDHI0_IXRST 34
#define R9A07G044_SDHI1_IXRST 35
#define R9A07G044_GPU_RESETN 36
#define R9A07G044_GPU_AXI_RESETN 37
#define R9A07G044_GPU_ACE_RESETN 38
#define R9A07G044_ISU_ARESETN 39
#define R9A07G044_ISU_PRESETN 40
#define R9A07G044_H264_X_RESET_VCP 41
#define R9A07G044_H264_CP_PRESET_P 42
#define R9A07G044_CRU_CMN_RSTB 43
#define R9A07G044_CRU_PRESETN 44
#define R9A07G044_CRU_ARESETN 45
#define R9A07G044_MIPI_DSI_CMN_RSTB 46
#define R9A07G044_MIPI_DSI_ARESET_N 47
#define R9A07G044_MIPI_DSI_PRESET_N 48
#define R9A07G044_LCDC_RESET_N 49
#define R9A07G044_SSI0_RST_M2_REG 50
#define R9A07G044_SSI1_RST_M2_REG 51
#define R9A07G044_SSI2_RST_M2_REG 52
#define R9A07G044_SSI3_RST_M2_REG 53
#define R9A07G044_SRC_RST 54
#define R9A07G044_USB_U2H0_HRESETN 55
#define R9A07G044_USB_U2H1_HRESETN 56
#define R9A07G044_USB_U2P_EXL_SYSRST 57
#define R9A07G044_USB_PRESETN 58
#define R9A07G044_ETH0_RST_HW_N 59
#define R9A07G044_ETH1_RST_HW_N 60
#define R9A07G044_I2C0_MRST 61
#define R9A07G044_I2C1_MRST 62
#define R9A07G044_I2C2_MRST 63
#define R9A07G044_I2C3_MRST 64
#define R9A07G044_SCIF0_RST_SYSTEM_N 65
#define R9A07G044_SCIF1_RST_SYSTEM_N 66
#define R9A07G044_SCIF2_RST_SYSTEM_N 67
#define R9A07G044_SCIF3_RST_SYSTEM_N 68
#define R9A07G044_SCIF4_RST_SYSTEM_N 69
#define R9A07G044_SCI0_RST 70
#define R9A07G044_SCI1_RST 71
#define R9A07G044_IRDA_RST 72
#define R9A07G044_RSPI0_RST 73
#define R9A07G044_RSPI1_RST 74
#define R9A07G044_RSPI2_RST 75
#define R9A07G044_CANFD_RSTP_N 76
#define R9A07G044_CANFD_RSTC_N 77
#define R9A07G044_GPIO_RSTN 78
#define R9A07G044_GPIO_PORT_RESETN 79
#define R9A07G044_GPIO_SPARE_RESETN 80
#define R9A07G044_ADC_PRESETN 81
#define R9A07G044_ADC_ADRST_N 82
#define R9A07G044_TSU_PRESETN 83
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */

14
include/linux/scmi_protocol.h
View File

@ -101,6 +101,10 @@ struct scmi_clk_proto_ops {
* to sustained performance level mapping
* @est_power_get: gets the estimated power cost for a given performance domain
* at a given frequency
* @fast_switch_possible: indicates if fast DVFS switching is possible or not
* for a given device
* @power_scale_mw_get: indicates if the power values provided are in milliWatts
* or in some other (abstract) scale
*/
struct scmi_perf_proto_ops {
int (*limits_set)(const struct scmi_protocol_handle *ph, u32 domain,
@ -153,7 +157,7 @@ struct scmi_power_proto_ops {
};
/**
* scmi_sensor_reading - represent a timestamped read
* struct scmi_sensor_reading - represent a timestamped read
*
* Used by @reading_get_timestamped method.
*
@ -167,7 +171,7 @@ struct scmi_sensor_reading {
};
/**
* scmi_range_attrs - specifies a sensor or axis values' range
* struct scmi_range_attrs - specifies a sensor or axis values' range
* @min_range: The minimum value which can be represented by the sensor/axis.
* @max_range: The maximum value which can be represented by the sensor/axis.
*/
@ -177,7 +181,7 @@ struct scmi_range_attrs {
};
/**
* scmi_sensor_axis_info - describes one sensor axes
* struct scmi_sensor_axis_info - describes one sensor axes
* @id: The axes ID.
* @type: Axes type. Chosen amongst one of @enum scmi_sensor_class.
* @scale: Power-of-10 multiplier applied to the axis unit.
@ -205,8 +209,8 @@ struct scmi_sensor_axis_info {
};
/**
* scmi_sensor_intervals_info - describes number and type of available update
* intervals
* struct scmi_sensor_intervals_info - describes number and type of available
* update intervals
* @segmented: Flag for segmented intervals' representation. When True there
* will be exactly 3 intervals in @desc, with each entry
* representing a member of a segment in this order:

8
include/linux/scpi_protocol.h
View File

@ -51,6 +51,14 @@ struct scpi_sensor_info {
* OPP is an index to the list return by @dvfs_get_info
* @dvfs_get_info: returns the DVFS capabilities of the given power
* domain. It includes the OPP list and the latency information
* @device_domain_id: gets the scpi domain id for a given device
* @get_transition_latency: gets the DVFS transition latency for a given device
* @add_opps_to_device: adds all the OPPs for a given device
* @sensor_get_capability: get the list of capabilities for the sensors
* @sensor_get_info: get the information of the specified sensor
* @sensor_get_value: gets the current value of the sensor
* @device_get_power_state: gets the power state of a power domain
* @device_set_power_state: sets the power state of a power domain
*/
struct scpi_ops {
u32 (*get_version)(void);

9
include/soc/tegra/mc.h
View File

@ -237,14 +237,19 @@ unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
#ifdef CONFIG_TEGRA_MC
struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev);
int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev);
#else
static inline struct tegra_mc *
devm_tegra_memory_controller_get(struct device *dev)
{
return ERR_PTR(-ENODEV);
}
static inline int
tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev)
{
return -ENODEV;
}
#endif
int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev);
#endif /* __SOC_TEGRA_MC_H__ */