ALSA: asihpi - Cosmetic + a minor comments.
Signed-off-by: Eliot Blennerhassett <eblennerhassett@audioscience.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
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4b60221c04
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1d595d2a21
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@ -957,8 +957,7 @@ enum HPI_ERROR_CODES {
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/** Reserved for OEMs. */
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HPI_ERROR_RESERVED_1 = 290,
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/* HPI_ERROR_INVALID_STREAM = 300,
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use HPI_ERROR_INVALID_OBJ_INDEX */
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/* HPI_ERROR_INVALID_STREAM = 300 use HPI_ERROR_INVALID_OBJ_INDEX */
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/** Invalid compression format. */
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HPI_ERROR_INVALID_FORMAT = 301,
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/** Invalid format samplerate */
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@ -969,12 +968,8 @@ enum HPI_ERROR_CODES {
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HPI_ERROR_INVALID_BITRATE = 304,
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/** Invalid datasize used for stream read/write. */
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HPI_ERROR_INVALID_DATASIZE = 305,
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/* Stream buffer is full during stream write.
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HPI_ERROR_BUFFER_FULL = 306,
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Stream buffer is empty during stream read.
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HPI_ERROR_BUFFER_EMPTY = 307,
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Use HPI_ERROR_INVALID_DATASIZE
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*/
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/* HPI_ERROR_BUFFER_FULL = 306 use HPI_ERROR_INVALID_DATASIZE */
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/* HPI_ERROR_BUFFER_EMPTY = 307 use HPI_ERROR_INVALID_DATASIZE */
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/** Null data pointer used for stream read/write. */
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HPI_ERROR_INVALID_DATA_POINTER = 308,
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/** Packet ordering error for stream read/write. */
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@ -1098,16 +1093,16 @@ struct hpi_anc_frame {
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*/
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struct hpi_async_event {
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u16 event_type; /**< type of event. \sa async_event */
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u16 sequence; /**< Sequence number, allows lost event detection */
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u32 state; /**< New state */
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u32 h_object; /**< handle to the object returning the event. */
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u16 sequence; /**< Sequence number, allows lost event detection */
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u32 state; /**< New state */
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u32 h_object; /**< handle to the object returning the event. */
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union {
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struct {
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u16 index; /**< GPIO bit index. */
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} gpio;
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struct {
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u16 node_index; /**< what node is the control on ? */
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u16 node_type; /**< what type of node is the control on ? */
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u16 node_type; /**< what type of node is the control on ? */
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} control;
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} u;
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};
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@ -1635,8 +1630,8 @@ u16 hpi_cobranet_get_static_ip_address(u32 h_control, u32 *pdw_ip_address);
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u16 hpi_cobranet_set_static_ip_address(u32 h_control, u32 dw_ip_address);
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u16 hpi_cobranet_get_macaddress(u32 h_control, u32 *pmAC_MS_bs,
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u32 *pmAC_LS_bs);
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u16 hpi_cobranet_get_macaddress(u32 h_control, u32 *p_mac_msbs,
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u32 *p_mac_lsbs);
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/*************************/
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/* Tone Detector control */
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@ -751,6 +751,9 @@ static void delete_adapter_obj(struct hpi_adapter_obj *pao)
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kfree(phw);
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}
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/*****************************************************************************/
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/* Adapter functions */
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/*****************************************************************************/
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/* OutStream Host buffer functions */
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@ -1781,12 +1784,66 @@ static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index)
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BAR1 via BootLoader_WriteMem32) */
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boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL,
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0x000034A8);
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/* EMIF CE0 setup - 2Mx32 Sync DRAM
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31..28 Wr setup
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27..22 Wr strobe
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21..20 Wr hold
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19..16 Rd setup
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15..14 -
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13..8 Rd strobe
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7..4 MTYPE 0011 Sync DRAM 32bits
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3 Wr hold MSB
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2..0 Rd hold
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*/
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boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0,
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0x00000030);
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/* EMIF SDRAM Extension
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0x00
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31-21 0000b 0000b 000b
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20 WR2RD = 2cycles-1 = 1b
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19-18 WR2DEAC = 3cycle-1 = 10b
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17 WR2WR = 2cycle-1 = 1b
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16-15 R2WDQM = 4cycle-1 = 11b
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14-12 RD2WR = 6cycles-1 = 101b
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11-10 RD2DEAC = 4cycle-1 = 11b
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9 RD2RD = 2cycle-1 = 1b
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8-7 THZP = 3cycle-1 = 10b
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6-5 TWR = 2cycle-1 = 01b (tWR = 17ns)
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4 TRRD = 2cycle = 0b (tRRD = 14ns)
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3-1 TRAS = 5cycle-1 = 100b (Tras=42ns)
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1 CAS latency = 3cyc = 1b
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(for Micron 2M32-7 operating at 100MHz)
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*/
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boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT,
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0x001BDF29);
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/* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
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31 - 0b -
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30 SDBSZ 1b 4 bank
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29..28 SDRSZ 00b 11 row address pins
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27..26 SDCSZ 01b 8 column address pins
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25 RFEN 1b refersh enabled
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24 INIT 1b init SDRAM!
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23..20 TRCD 0001b (Trcd/Tcyc)-1 = (20/10)-1 = 1
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19..16 TRP 0001b (Trp/Tcyc)-1 = (20/10)-1 = 1
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15..12 TRC 0110b (Trc/Tcyc)-1 = (70/10)-1 = 6
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11..0 - 0000b 0000b 0000b
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*/
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boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL,
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0x47117000);
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0x47116000);
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/* SDRAM refresh timing
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Need 4,096 refresh cycles every 64ms = 15.625us = 1562cycles of 100MHz = 0x61A
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*/
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boot_loader_write_mem32(pao, dsp_index,
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C6713_EMIF_SDRAMTIMING, 0x00000410);
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@ -553,12 +553,10 @@ struct hpi_resource {
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/** Format info used inside struct hpi_message
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Not the same as public API struct hpi_format */
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struct hpi_msg_format {
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u32 sample_rate;
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/**< 11025, 32000, 44100 ... */
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u32 bit_rate; /**< for MPEG */
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u32 attributes;
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/**< Stereo/JointStereo/Mono */
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u16 channels; /**< 1,2..., (or ancillary mode or idle bit */
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u32 sample_rate; /**< 11025, 32000, 44100 etc. */
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u32 bit_rate; /**< for MPEG */
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u32 attributes; /**< stereo/joint_stereo/mono */
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u16 channels; /**< 1,2..., (or ancillary mode or idle bit */
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u16 format; /**< HPI_FORMAT_PCM16, _MPEG etc. see \ref HPI_FORMATS. */
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};
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@ -593,7 +591,7 @@ struct hpi_data_compat32 {
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struct hpi_buffer {
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/** placehoder for backward compatability (see dwBufferSize) */
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struct hpi_msg_format reserved;
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u32 command; /**< HPI_BUFFER_CMD_xxx*/
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u32 command; /**< HPI_BUFFER_CMD_xxx*/
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u32 pci_address; /**< PCI physical address of buffer for DSP DMA */
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u32 buffer_size; /**< must line up with data_size of HPI_DATA*/
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};
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@ -1125,6 +1123,11 @@ struct hpi_message {
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sizeof(struct hpi_message_header) + sizeof(struct hpi_async_msg) \
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}
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/*
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Note that the wSpecificError error field should be inspected and potentially
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reported whenever HPI_ERROR_DSP_COMMUNICATION or HPI_ERROR_DSP_BOOTLOAD is
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returned in wError.
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*/
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struct hpi_response_header {
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u16 size;
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u8 type; /* HPI_TYPE_RESPONSE */
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@ -45,6 +45,7 @@ struct hpi_control_cache {
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};
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struct hpi_adapter_obj *hpi_find_adapter(u16 adapter_index);
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u16 hpi_add_adapter(struct hpi_adapter_obj *pao);
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void hpi_delete_adapter(struct hpi_adapter_obj *pao);
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@ -87,7 +87,7 @@ void hpi_dsp_code_rewind(struct dsp_code *ps_dsp_code);
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*/
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short hpi_dsp_code_read_word(struct dsp_code *ps_dsp_code,
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/**< DSP code descriptor */
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u32 *pword /**< where to store the read word */
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u32 *pword /**< Where to store the read word */
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);
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/** Get a block of dsp code into an internal buffer, and provide a pointer to
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@ -230,7 +230,7 @@ static void subsys_message(struct hpi_message *phm, struct hpi_response *phr,
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break;
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default:
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/* Must explicitly send subsys messages to individual backends */
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/* Must explicitly handle every subsys message in this switch */
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hpi_init_response(phr, HPI_OBJ_SUBSYSTEM, phm->function,
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HPI_ERROR_INVALID_FUNC);
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break;
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