Renesas ARM Based SoC DT PM Domain Updates for v4.7
* Add SYSC PM Domains to DT for R-Car Gen 1 and 2 SoCs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXID1CAAoJENfPZGlqN0++6t4P/A7Mb9W3qeJ13yG4CcDg93MM kQ94tuhNtvpsgRPPlSvXr9htg9YyWk/gInR/LFRXxaVBjBbJQXiXzwGJlgtd/MQX g+McpJfZT88i87tXlM7jLGoEvoZ7/H6VphlQMneC9XOqd3abvlyoCUxJNFTDDMt3 1JGNsHbVnZoUXIuAYeFEv9F7VAO6fsbZ0jcml++kgghutuqaAeAYbVDvo8+yIKwt ytq/OUUZfM8LbNUybEHhmyxL2eUEAGwkdqgyiCtf5Kh72nr3fklKRW1icv+V6mb1 MoZ675XebEOsNWz7D56qbxiyu0BXd2dxFI2q7z/vs8dluLIdkOl7y4bqh81crH/s Ox3d3UlKKo9pUOYFMNwBakJAhVOXO/zIjeYmMDP8WypgeYNspD4mQHNvPDpYcu52 vTcJojI3gV00l7tuPZA7vk+x4xH5WeBxS0Ti0fsQSkmFVnU/BFQfDOwTpHh9oa00 ea4Uh99JV4ypQ/LQ3Z8IsoXYsVAzRCfk14j0itld/DhTbeoEHIYGGxS0ILCDyB0G VLwbPjNgAN/PzkfUhhxYYab3gleg2ElYGoSZE4s/lEUnxF7pK/A2NwhMwh7+/BGP 5pDHNOoc+RxTOSXk98CApC/quhbwlALfJ01cpAxP8j7/3G57uvUJg9dOP2++cOGr FMUaS/ILk2YknrJkD+kO =DcHM -----END PGP SIGNATURE----- Merge tag 'renesas-dt-pm-domain-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late Merge "Renesas ARM Based SoC DT PM Domain Updates for v4.7" into next/late * Add SYSC PM Domains to DT for R-Car Gen 1 and 2 SoCs This pull requests is based on a merge of: * "[GIT PULL] Second Round of Renesas ARM Based SoC R-Car SYSC Updates for v4.7", tagged as renesas-rcar-sysc2-for-v4.7, which you have already pulled. * "[GIT PULL v2] Renesas ARM Based SoC DT Updates for v4.7", tagged as renesas-dt-for-v4.7, which you have also already pulled. The reason for the somewhat tedious base on renesas-rcar-sysc2-for-v4.7, which provides driver changes, is a hard run-time dependency. I also have a similar set of changes for arm64 which I will send separately. * tag 'renesas-dt-pm-domain-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (88 commits) ARM: dts: r8a7794: Use SYSC "always-on" PM Domain ARM: dts: r8a7793: Use SYSC "always-on" PM Domain ARM: dts: r8a7791: Use SYSC "always-on" PM Domain ARM: dts: r8a7790: Use SYSC "always-on" PM Domain ARM: dts: r8a7779: Use SYSC "always-on" PM Domain ARM: dts: r8a7794: Add SYSC PM Domains ARM: dts: r8a7793: Add SYSC PM Domains ARM: dts: r8a7791: Add SYSC PM Domains ARM: dts: r8a7790: Add SYSC PM Domains ARM: dts: r8a7779: Add SYSC PM Domains soc: renesas: rcar-sysc: Add support for R-Car H3 power areas soc: renesas: rcar-sysc: Add support for R-Car E2 power areas soc: renesas: rcar-sysc: Add support for R-Car M2-N power areas soc: renesas: rcar-sysc: Add support for R-Car M2-W power areas soc: renesas: rcar-sysc: Add support for R-Car H2 power areas soc: renesas: rcar-sysc: Add support for R-Car H1 power areas soc: renesas: rcar-sysc: Enable Clock Domain for I/O devices ARM: dts: gose: Enable SDHI controllers ARM: dts: r8a7793: Add SDHI controllers ARM: dts: r8a7790: fix max-frequency for SDHI ...
This commit is contained in:
Arnd Bergmann
commit
1cf257ab03
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@ -0,0 +1,48 @@
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DT bindings for the Renesas R-Car System Controller
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== System Controller Node ==
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The R-Car System Controller provides power management for the CPU cores and
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various coprocessors.
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Required properties:
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- compatible: Must contain exactly one of the following:
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- "renesas,r8a7779-sysc" (R-Car H1)
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- "renesas,r8a7790-sysc" (R-Car H2)
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- "renesas,r8a7791-sysc" (R-Car M2-W)
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- "renesas,r8a7792-sysc" (R-Car V2H)
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- "renesas,r8a7793-sysc" (R-Car M2-N)
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- "renesas,r8a7794-sysc" (R-Car E2)
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- "renesas,r8a7795-sysc" (R-Car H3)
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- reg: Address start and address range for the device.
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- #power-domain-cells: Must be 1.
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Example:
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7791-sysc";
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reg = <0 0xe6180000 0 0x0200>;
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#power-domain-cells = <1>;
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};
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== PM Domain Consumers ==
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Devices residing in a power area must refer to that power area, as documented
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by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Required properties:
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- power-domains: A phandle and symbolic PM domain specifier, as defined in
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<dt-bindings/power/r8a77*-sysc.h>.
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Example:
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L2_CA15: cache-controller@0 {
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compatible = "cache";
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power-domains = <&sysc R8A7791_PD_CA15_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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@ -1491,6 +1491,8 @@ Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
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S: Supported
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F: arch/arm64/boot/dts/renesas/
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F: drivers/soc/renesas/
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F: include/linux/soc/renesas/
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ARM/RISCPC ARCHITECTURE
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M: Russell King <linux@arm.linux.org.uk>
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@ -1604,6 +1606,8 @@ F: arch/arm/configs/shmobile_defconfig
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F: arch/arm/include/debug/renesas-scif.S
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F: arch/arm/mach-shmobile/
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F: drivers/sh/
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F: drivers/soc/renesas/
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F: include/linux/soc/renesas/
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ARM/SOCFPGA ARCHITECTURE
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M: Dinh Nguyen <dinguyen@opensource.altera.com>
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@ -105,8 +105,8 @@
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&pfc {
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uart1_pins: serial@e1030000 {
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renesas,groups = "uart1_ctrl", "uart1_data";
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renesas,function = "uart1";
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groups = "uart1_ctrl", "uart1_data";
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function = "uart1";
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};
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};
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@ -37,46 +37,41 @@
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#size-cells = <1>;
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/* External clocks */
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extal_clk: extal_clk {
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extal_clk: extal {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* If clk present, value must be set by board */
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clock-frequency = <0>;
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clock-output-names = "extal";
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};
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usb_x1_clk: usb_x1_clk {
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usb_x1_clk: usb_x1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* If clk present, value must be set by board */
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clock-frequency = <0>;
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clock-output-names = "usb_x1";
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};
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/* Fixed factor clocks */
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b_clk: b_clk {
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b_clk: b {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R7S72100_CLK_PLL>;
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clock-mult = <1>;
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clock-div = <3>;
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clock-output-names = "b";
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};
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p1_clk: p1_clk {
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p1_clk: p1 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R7S72100_CLK_PLL>;
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clock-mult = <1>;
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clock-div = <6>;
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clock-output-names = "p1";
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};
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p0_clk: p0_clk {
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p0_clk: p0 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R7S72100_CLK_PLL>;
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clock-mult = <1>;
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clock-div = <12>;
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clock-output-names = "p0";
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};
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/* Special CPG clocks */
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@ -189,28 +189,28 @@
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&pfc {
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scifa0_pins: serial0 {
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renesas,groups = "scifa0_data";
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renesas,function = "scifa0";
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groups = "scifa0_data";
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function = "scifa0";
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};
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mmc0_pins: mmc {
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renesas,groups = "mmc0_data8", "mmc0_ctrl";
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renesas,function = "mmc0";
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groups = "mmc0_data8", "mmc0_ctrl";
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function = "mmc0";
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};
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sdhi0_pins: sd0 {
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renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
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renesas,function = "sdhi0";
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groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
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function = "sdhi0";
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};
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sdhi1_pins: sd1 {
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renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
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renesas,function = "sdhi1";
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groups = "sdhi1_data4", "sdhi1_ctrl";
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function = "sdhi1";
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};
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keyboard_pins: keyboard {
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renesas,pins = "PORT324", "PORT325", "PORT326", "PORT327",
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"PORT328", "PORT329";
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pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328",
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"PORT329";
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bias-pull-up;
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};
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};
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@ -486,37 +486,32 @@
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ranges;
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/* External root clocks */
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extalr_clk: extalr_clk {
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "extalr";
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};
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extal1_clk: extal1_clk {
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extal1_clk: extal1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "extal1";
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};
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extal2_clk: extal2_clk {
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extal2_clk: extal2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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clock-output-names = "extal2";
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};
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fsiack_clk: fsiack_clk {
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fsiack_clk: fsiack {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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clock-output-names = "fsiack";
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};
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fsibck_clk: fsibck_clk {
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fsibck_clk: fsibck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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clock-output-names = "fsibck";
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};
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/* Special CPG clocks */
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@ -540,171 +535,151 @@
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#clock-cells = <0>;
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clock-output-names = "zb";
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};
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sdhi0_clk: sdhi0_clk@e6150074 {
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sdhi0_clk: sdhi0ck@e6150074 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150074 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi0ck";
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};
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sdhi1_clk: sdhi1_clk@e6150078 {
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sdhi1_clk: sdhi1ck@e6150078 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150078 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi1ck";
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};
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sdhi2_clk: sdhi2_clk@e615007c {
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sdhi2_clk: sdhi2ck@e615007c {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe615007c 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi2ck";
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};
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mmc0_clk: mmc0_clk@e6150240 {
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mmc0_clk: mmc0@e6150240 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150240 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "mmc0";
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};
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mmc1_clk: mmc1_clk@e6150244 {
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mmc1_clk: mmc1@e6150244 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150244 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "mmc1";
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};
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vclk1_clk: vclk1_clk@e6150008 {
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vclk1_clk: vclk1@e6150008 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150008 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>, <&main_div2_clk>,
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<&extalr_clk>, <0>, <0>;
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#clock-cells = <0>;
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clock-output-names = "vclk1";
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};
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vclk2_clk: vclk2_clk@e615000c {
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vclk2_clk: vclk2@e615000c {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe615000c 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>, <&main_div2_clk>,
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<&extalr_clk>, <0>, <0>;
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#clock-cells = <0>;
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clock-output-names = "vclk2";
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};
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vclk3_clk: vclk3_clk@e615001c {
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vclk3_clk: vclk3@e615001c {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe615001c 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>, <&main_div2_clk>,
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<&extalr_clk>, <0>, <0>;
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#clock-cells = <0>;
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clock-output-names = "vclk3";
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};
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vclk4_clk: vclk4_clk@e6150014 {
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vclk4_clk: vclk4@e6150014 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150014 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>, <&main_div2_clk>,
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<&extalr_clk>, <0>, <0>;
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#clock-cells = <0>;
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clock-output-names = "vclk4";
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};
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vclk5_clk: vclk5_clk@e6150034 {
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vclk5_clk: vclk5@e6150034 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150034 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>, <&main_div2_clk>,
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<&extalr_clk>, <0>, <0>;
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#clock-cells = <0>;
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clock-output-names = "vclk5";
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};
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fsia_clk: fsia_clk@e6150018 {
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fsia_clk: fsia@e6150018 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150018 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<&fsiack_clk>, <0>;
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#clock-cells = <0>;
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clock-output-names = "fsia";
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};
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fsib_clk: fsib_clk@e6150090 {
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fsib_clk: fsib@e6150090 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150090 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<&fsibck_clk>, <0>;
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#clock-cells = <0>;
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clock-output-names = "fsib";
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};
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mp_clk: mp_clk@e6150080 {
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mp_clk: mp@e6150080 {
|
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150080 0 4>;
|
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<&extal2_clk>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "mp";
|
||||
};
|
||||
m4_clk: m4_clk@e6150098 {
|
||||
m4_clk: m4@e6150098 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150098 0 4>;
|
||||
clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "m4";
|
||||
};
|
||||
hsi_clk: hsi_clk@e615026c {
|
||||
hsi_clk: hsi@e615026c {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615026c 0 4>;
|
||||
clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
|
||||
<&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "hsi";
|
||||
};
|
||||
spuv_clk: spuv_clk@e6150094 {
|
||||
spuv_clk: spuv@e6150094 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150094 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<&extal2_clk>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "spuv";
|
||||
};
|
||||
|
||||
/* Fixed factor clocks */
|
||||
main_div2_clk: main_div2_clk {
|
||||
main_div2_clk: main_div2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "main_div2";
|
||||
};
|
||||
pll0_div2_clk: pll0_div2_clk {
|
||||
pll0_div2_clk: pll0_div2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll0_div2";
|
||||
};
|
||||
pll1_div2_clk: pll1_div2_clk {
|
||||
pll1_div2_clk: pll1_div2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll1_div2";
|
||||
};
|
||||
extal1_div2_clk: extal1_div2_clk {
|
||||
extal1_div2_clk: extal1_div2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&extal1_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "extal1_div2";
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
|
|
|
|||
|
|
@ -228,44 +228,44 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
ether_pins: ether {
|
||||
renesas,groups = "gether_mii", "gether_int";
|
||||
renesas,function = "gether";
|
||||
groups = "gether_mii", "gether_int";
|
||||
function = "gether";
|
||||
};
|
||||
|
||||
scifa1_pins: serial1 {
|
||||
renesas,groups = "scifa1_data";
|
||||
renesas,function = "scifa1";
|
||||
groups = "scifa1_data";
|
||||
function = "scifa1";
|
||||
};
|
||||
|
||||
st1232_pins: touchscreen {
|
||||
renesas,groups = "intc_irq10";
|
||||
renesas,function = "intc";
|
||||
groups = "intc_irq10";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
backlight_pins: backlight {
|
||||
renesas,groups = "tpu0_to2_1";
|
||||
renesas,function = "tpu0";
|
||||
groups = "tpu0_to2_1";
|
||||
function = "tpu0";
|
||||
};
|
||||
|
||||
mmc0_pins: mmc0 {
|
||||
renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";
|
||||
renesas,function = "mmc0";
|
||||
groups = "mmc0_data8_1", "mmc0_ctrl_1";
|
||||
function = "mmc0";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
|
||||
renesas,function = "sdhi0";
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
|
||||
function = "sdhi0";
|
||||
};
|
||||
|
||||
fsia_pins: sounda {
|
||||
renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
|
||||
"fsia_data_in_1", "fsia_data_out_0";
|
||||
renesas,function = "fsia";
|
||||
groups = "fsia_sclk_in", "fsia_mclk_out",
|
||||
"fsia_data_in_1", "fsia_data_out_0";
|
||||
function = "fsia";
|
||||
};
|
||||
|
||||
lcd0_pins: lcd0 {
|
||||
renesas,groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";
|
||||
renesas,function = "lcd0";
|
||||
groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";
|
||||
function = "lcd0";
|
||||
|
||||
/* DBGMD/LCDC0/FSIA MUX */
|
||||
gpio-hog;
|
||||
|
|
|
|||
|
|
@ -422,53 +422,45 @@
|
|||
ranges;
|
||||
|
||||
/* External root clock */
|
||||
extalr_clk: extalr_clk {
|
||||
extalr_clk: extalr {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "extalr";
|
||||
};
|
||||
extal1_clk: extal1_clk {
|
||||
extal1_clk: extal1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "extal1";
|
||||
};
|
||||
extal2_clk: extal2_clk {
|
||||
extal2_clk: extal2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "extal2";
|
||||
};
|
||||
dv_clk: dv_clk {
|
||||
dv_clk: dv {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
clock-output-names = "dv";
|
||||
};
|
||||
fmsick_clk: fmsick_clk {
|
||||
fmsick_clk: fmsick {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "fmsick";
|
||||
};
|
||||
fmsock_clk: fmsock_clk {
|
||||
fmsock_clk: fmsock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "fmsock";
|
||||
};
|
||||
fsiack_clk: fsiack_clk {
|
||||
fsiack_clk: fsiack {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "fsiack";
|
||||
};
|
||||
fsibck_clk: fsibck_clk {
|
||||
fsibck_clk: fsibck {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "fsibck";
|
||||
};
|
||||
|
||||
/* Special CPG clocks */
|
||||
|
|
@ -486,7 +478,7 @@
|
|||
};
|
||||
|
||||
/* Variable factor clocks (DIV6) */
|
||||
vclk1_clk: vclk1_clk@e6150008 {
|
||||
vclk1_clk: vclk1@e6150008 {
|
||||
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150008 4>;
|
||||
clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
|
||||
|
|
@ -494,9 +486,8 @@
|
|||
<&extal1_div2_clk>, <&extalr_clk>, <0>,
|
||||
<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "vclk1";
|
||||
};
|
||||
vclk2_clk: vclk2_clk@e615000c {
|
||||
vclk2_clk: vclk2@e615000c {
|
||||
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe615000c 4>;
|
||||
clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
|
||||
|
|
@ -504,77 +495,67 @@
|
|||
<&extal1_div2_clk>, <&extalr_clk>, <0>,
|
||||
<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "vclk2";
|
||||
};
|
||||
fmsi_clk: fmsi_clk@e6150010 {
|
||||
fmsi_clk: fmsi@e6150010 {
|
||||
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150010 4>;
|
||||
clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "fmsi";
|
||||
};
|
||||
fmso_clk: fmso_clk@e6150014 {
|
||||
fmso_clk: fmso@e6150014 {
|
||||
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150014 4>;
|
||||
clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "fmso";
|
||||
};
|
||||
fsia_clk: fsia_clk@e6150018 {
|
||||
fsia_clk: fsia@e6150018 {
|
||||
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150018 4>;
|
||||
clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "fsia";
|
||||
};
|
||||
sub_clk: sub_clk@e6150080 {
|
||||
sub_clk: sub@e6150080 {
|
||||
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150080 4>;
|
||||
clocks = <&pllc1_div2_clk>,
|
||||
<&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sub";
|
||||
};
|
||||
spu_clk: spu_clk@e6150084 {
|
||||
spu_clk: spu@e6150084 {
|
||||
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150084 4>;
|
||||
clocks = <&pllc1_div2_clk>,
|
||||
<&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "spu";
|
||||
};
|
||||
vou_clk: vou_clk@e6150088 {
|
||||
vou_clk: vou@e6150088 {
|
||||
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150088 4>;
|
||||
clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
|
||||
<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "vou";
|
||||
};
|
||||
stpro_clk: stpro_clk@e615009c {
|
||||
stpro_clk: stpro@e615009c {
|
||||
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe615009c 4>;
|
||||
clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "stpro";
|
||||
};
|
||||
|
||||
/* Fixed factor clocks */
|
||||
pllc1_div2_clk: pllc1_div2_clk {
|
||||
pllc1_div2_clk: pllc1_div2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pllc1_div2";
|
||||
};
|
||||
extal1_div2_clk: extal1_div2_clk {
|
||||
extal1_div2_clk: extal1_div2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&extal1_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "extal1_div2";
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
|
|
|
|||
|
|
@ -130,53 +130,53 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
scif0_pins: serial0 {
|
||||
renesas,groups = "scif0_data_a", "scif0_ctrl";
|
||||
renesas,function = "scif0";
|
||||
groups = "scif0_data_a", "scif0_ctrl";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
renesas,groups = "scif_clk";
|
||||
renesas,function = "scif_clk";
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
mmc_pins: mmc {
|
||||
renesas,groups = "mmc_data8", "mmc_ctrl";
|
||||
renesas,function = "mmc";
|
||||
groups = "mmc_data8", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,function = "sdhi0";
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
};
|
||||
sdhi0_pup_pins: sd0_pup {
|
||||
renesas,groups = "sdhi0_cd", "sdhi0_wp";
|
||||
renesas,function = "sdhi0";
|
||||
groups = "sdhi0_cd", "sdhi0_wp";
|
||||
function = "sdhi0";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
hspi0_pins: hspi0 {
|
||||
renesas,groups = "hspi0_a";
|
||||
renesas,function = "hspi0";
|
||||
groups = "hspi0_a";
|
||||
function = "hspi0";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
renesas,groups = "usb0";
|
||||
renesas,function = "usb0";
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
renesas,groups = "usb1";
|
||||
renesas,function = "usb1";
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
renesas,groups = "vin0_data8", "vin0_clk";
|
||||
renesas,function = "vin0";
|
||||
groups = "vin0_data8", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
vin1_pins: vin1 {
|
||||
renesas,groups = "vin1_data8", "vin1_clk";
|
||||
renesas,function = "vin1";
|
||||
groups = "vin1_data8", "vin1_clk";
|
||||
function = "vin1";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -443,11 +443,10 @@
|
|||
ranges;
|
||||
|
||||
/* External input clock */
|
||||
extal_clk: extal_clk {
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "extal";
|
||||
};
|
||||
|
||||
/* External SCIF clock */
|
||||
|
|
@ -474,59 +473,51 @@
|
|||
audio_clk_a: audio_clk_a {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "audio_clk_a";
|
||||
};
|
||||
audio_clk_b: audio_clk_b {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "audio_clk_b";
|
||||
};
|
||||
audio_clk_c: audio_clk_c {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "audio_clk_c";
|
||||
};
|
||||
|
||||
/* Fixed ratio clocks */
|
||||
g_clk: g_clk {
|
||||
g_clk: g {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <12>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "g";
|
||||
};
|
||||
i_clk: i_clk {
|
||||
i_clk: i {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "i";
|
||||
};
|
||||
s3_clk: s3_clk {
|
||||
s3_clk: s3 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "s3";
|
||||
};
|
||||
s4_clk: s4_clk {
|
||||
s4_clk: s4 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "s4";
|
||||
};
|
||||
z_clk: z_clk {
|
||||
z_clk: z {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "z";
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
|
|
|
|||
|
|
@ -170,49 +170,49 @@
|
|||
|
||||
du_pins: du {
|
||||
du0 {
|
||||
renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
|
||||
renesas,function = "du0";
|
||||
groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
|
||||
function = "du0";
|
||||
};
|
||||
du1 {
|
||||
renesas,groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
|
||||
renesas,function = "du1";
|
||||
groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
|
||||
function = "du1";
|
||||
};
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
renesas,groups = "scif_clk_b";
|
||||
renesas,function = "scif_clk";
|
||||
groups = "scif_clk_b";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ethernet_pins: ethernet {
|
||||
intc {
|
||||
renesas,groups = "intc_irq1_b";
|
||||
renesas,function = "intc";
|
||||
groups = "intc_irq1_b";
|
||||
function = "intc";
|
||||
};
|
||||
lbsc {
|
||||
renesas,groups = "lbsc_ex_cs0";
|
||||
renesas,function = "lbsc";
|
||||
groups = "lbsc_ex_cs0";
|
||||
function = "lbsc";
|
||||
};
|
||||
};
|
||||
|
||||
scif2_pins: serial2 {
|
||||
renesas,groups = "scif2_data_c";
|
||||
renesas,function = "scif2";
|
||||
groups = "scif2_data_c";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
scif4_pins: serial4 {
|
||||
renesas,groups = "scif4_data";
|
||||
renesas,function = "scif4";
|
||||
groups = "scif4_data";
|
||||
function = "scif4";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
|
||||
renesas,function = "sdhi0";
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
|
||||
function = "sdhi0";
|
||||
};
|
||||
|
||||
hspi0_pins: hspi0 {
|
||||
renesas,groups = "hspi0";
|
||||
renesas,function = "hspi0";
|
||||
groups = "hspi0";
|
||||
function = "hspi0";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <dt-bindings/clock/r8a7779-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/r8a7779-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7779";
|
||||
|
|
@ -34,18 +35,21 @@
|
|||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000000>;
|
||||
power-domains = <&sysc R8A7779_PD_ARM1>;
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
clock-frequency = <1000000000>;
|
||||
power-domains = <&sysc R8A7779_PD_ARM2>;
|
||||
};
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
clock-frequency = <1000000000>;
|
||||
power-domains = <&sysc R8A7779_PD_ARM3>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -67,7 +71,7 @@
|
|||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xf0000600 0x20>;
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
|
||||
clocks = <&cpg_clocks R8A7779_CLK_ZS>;
|
||||
};
|
||||
|
||||
|
|
@ -173,7 +177,7 @@
|
|||
reg = <0xffc70000 0x1000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -184,7 +188,7 @@
|
|||
reg = <0xffc71000 0x1000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -195,7 +199,7 @@
|
|||
reg = <0xffc72000 0x1000>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -206,7 +210,7 @@
|
|||
reg = <0xffc73000 0x1000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -218,7 +222,7 @@
|
|||
clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -230,7 +234,7 @@
|
|||
clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -242,7 +246,7 @@
|
|||
clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -254,7 +258,7 @@
|
|||
clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -266,7 +270,7 @@
|
|||
clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -278,7 +282,7 @@
|
|||
clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -300,7 +304,7 @@
|
|||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
|
|
@ -315,7 +319,7 @@
|
|||
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
|
|
@ -330,7 +334,7 @@
|
|||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
|
|
@ -342,7 +346,7 @@
|
|||
reg = <0xfc600000 0x2000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
sdhi0: sd@ffe4c000 {
|
||||
|
|
@ -350,7 +354,7 @@
|
|||
reg = <0xffe4c000 0x100>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -359,7 +363,7 @@
|
|||
reg = <0xffe4d000 0x100>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -368,7 +372,7 @@
|
|||
reg = <0xffe4e000 0x100>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -377,7 +381,7 @@
|
|||
reg = <0xffe4f000 0x100>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -388,7 +392,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -399,7 +403,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -410,7 +414,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -419,7 +423,7 @@
|
|||
reg = <0 0xfff80000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7779_CLK_DU>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
|
@ -445,12 +449,11 @@
|
|||
ranges;
|
||||
|
||||
/* External root clock */
|
||||
extal_clk: extal_clk {
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overriden by the board. */
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "extal";
|
||||
};
|
||||
|
||||
/* External SCIF clock */
|
||||
|
|
@ -474,37 +477,33 @@
|
|||
};
|
||||
|
||||
/* Fixed factor clocks */
|
||||
i_clk: i_clk {
|
||||
i_clk: i {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "i";
|
||||
};
|
||||
s3_clk: s3_clk {
|
||||
s3_clk: s3 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "s3";
|
||||
};
|
||||
s4_clk: s4_clk {
|
||||
s4_clk: s4 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <16>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "s4";
|
||||
};
|
||||
g_clk: g_clk {
|
||||
g_clk: g {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <24>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "g";
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
|
|
@ -591,4 +590,10 @@
|
|||
"mmc1", "mmc0";
|
||||
};
|
||||
};
|
||||
|
||||
sysc: system-controller@ffd85000 {
|
||||
compatible = "renesas,r8a7779-sysc";
|
||||
reg = <0xffd85000 0x0200>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -176,11 +176,10 @@
|
|||
1800000 0>;
|
||||
};
|
||||
|
||||
audio_clock: clock {
|
||||
audio_clock: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
clock-output-names = "audio_clock";
|
||||
};
|
||||
|
||||
rsnd_ak4643: sound {
|
||||
|
|
@ -314,119 +313,133 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
du_pins: du {
|
||||
renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
|
||||
renesas,function = "du";
|
||||
groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
scif0_pins: serial0 {
|
||||
renesas,groups = "scif0_data";
|
||||
renesas,function = "scif0";
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
renesas,groups = "scif_clk";
|
||||
renesas,function = "scif_clk";
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
renesas,function = "eth";
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
renesas,groups = "intc_irq0";
|
||||
renesas,function = "intc";
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
scifa1_pins: serial1 {
|
||||
renesas,groups = "scifa1_data";
|
||||
renesas,function = "scifa1";
|
||||
groups = "scifa1_data";
|
||||
function = "scifa1";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,function = "sdhi0";
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,function = "sdhi2";
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi2_pins_uhs: sd2_uhs {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
mmc1_pins: mmc1 {
|
||||
renesas,groups = "mmc1_data8", "mmc1_ctrl";
|
||||
renesas,function = "mmc1";
|
||||
groups = "mmc1_data8", "mmc1_ctrl";
|
||||
function = "mmc1";
|
||||
};
|
||||
|
||||
qspi_pins: spi0 {
|
||||
renesas,groups = "qspi_ctrl", "qspi_data4";
|
||||
renesas,function = "qspi";
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
msiof1_pins: spi2 {
|
||||
renesas,groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
|
||||
groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
|
||||
"msiof1_tx";
|
||||
renesas,function = "msiof1";
|
||||
function = "msiof1";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
renesas,groups = "i2c0";
|
||||
renesas,function = "i2c0";
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
iic0_pins: iic0 {
|
||||
renesas,groups = "iic0";
|
||||
renesas,function = "iic0";
|
||||
groups = "iic0";
|
||||
function = "iic0";
|
||||
};
|
||||
|
||||
iic1_pins: iic1 {
|
||||
renesas,groups = "iic1";
|
||||
renesas,function = "iic1";
|
||||
groups = "iic1";
|
||||
function = "iic1";
|
||||
};
|
||||
|
||||
iic2_pins: iic2 {
|
||||
renesas,groups = "iic2";
|
||||
renesas,function = "iic2";
|
||||
groups = "iic2";
|
||||
function = "iic2";
|
||||
};
|
||||
|
||||
iic3_pins: iic3 {
|
||||
renesas,groups = "iic3";
|
||||
renesas,function = "iic3";
|
||||
groups = "iic3";
|
||||
function = "iic3";
|
||||
};
|
||||
|
||||
hsusb_pins: hsusb {
|
||||
renesas,groups = "usb0_ovc_vbus";
|
||||
renesas,function = "usb0";
|
||||
groups = "usb0_ovc_vbus";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
renesas,groups = "usb0";
|
||||
renesas,function = "usb0";
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
renesas,groups = "usb1";
|
||||
renesas,function = "usb1";
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
usb2_pins: usb2 {
|
||||
renesas,groups = "usb2";
|
||||
renesas,function = "usb2";
|
||||
groups = "usb2";
|
||||
function = "usb2";
|
||||
};
|
||||
|
||||
vin1_pins: vin {
|
||||
renesas,groups = "vin1_data8", "vin1_clk";
|
||||
renesas,function = "vin1";
|
||||
groups = "vin1_data8", "vin1_clk";
|
||||
function = "vin1";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
renesas,function = "ssi";
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
renesas,groups = "audio_clk_a";
|
||||
renesas,function = "audio_clk";
|
||||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -539,21 +552,25 @@
|
|||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-1 = <&sdhi2_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi2>;
|
||||
vqmmc-supply = <&vccq_sdhi2>;
|
||||
cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include <dt-bindings/clock/r8a7790-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/r8a7790-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7790";
|
||||
|
|
@ -52,6 +53,7 @@
|
|||
voltage-tolerance = <1>; /* 1% */
|
||||
clocks = <&cpg_clocks R8A7790_CLK_Z>;
|
||||
clock-latency = <300000>; /* 300 us */
|
||||
power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
|
||||
/* kHz - uV - OPPs unknown yet */
|
||||
|
|
@ -68,6 +70,7 @@
|
|||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
clock-frequency = <1300000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
|
||||
|
|
@ -76,6 +79,7 @@
|
|||
compatible = "arm,cortex-a15";
|
||||
reg = <2>;
|
||||
clock-frequency = <1300000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
|
||||
|
|
@ -84,6 +88,7 @@
|
|||
compatible = "arm,cortex-a15";
|
||||
reg = <3>;
|
||||
clock-frequency = <1300000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
|
||||
|
|
@ -92,6 +97,7 @@
|
|||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
clock-frequency = <780000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
|
||||
|
|
@ -100,6 +106,7 @@
|
|||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
clock-frequency = <780000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
|
||||
|
|
@ -108,6 +115,7 @@
|
|||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
clock-frequency = <780000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
|
||||
|
|
@ -116,6 +124,7 @@
|
|||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
clock-frequency = <780000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
};
|
||||
|
|
@ -141,12 +150,14 @@
|
|||
|
||||
L2_CA15: cache-controller@0 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7790_PD_CA15_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
L2_CA7: cache-controller@1 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7790_PD_CA7_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
|
@ -173,7 +184,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
|
|
@ -186,7 +197,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
|
|
@ -199,7 +210,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
|
|
@ -212,7 +223,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
|
|
@ -225,7 +236,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
|
|
@ -238,7 +249,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
thermal: thermal@e61f0000 {
|
||||
|
|
@ -248,7 +259,7 @@
|
|||
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
|
|
@ -267,7 +278,7 @@
|
|||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0x60>;
|
||||
|
||||
|
|
@ -287,7 +298,7 @@
|
|||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0xff>;
|
||||
|
||||
|
|
@ -304,7 +315,7 @@
|
|||
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
|
|
@ -333,7 +344,7 @@
|
|||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
|
@ -364,7 +375,7 @@
|
|||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
|
@ -393,7 +404,7 @@
|
|||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
|
|
@ -422,7 +433,7 @@
|
|||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
|
|
@ -434,7 +445,7 @@
|
|||
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
|
@ -446,7 +457,7 @@
|
|||
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
|
@ -458,7 +469,7 @@
|
|||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -470,7 +481,7 @@
|
|||
reg = <0 0xe6518000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -482,7 +493,7 @@
|
|||
reg = <0 0xe6530000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -494,7 +505,7 @@
|
|||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -508,7 +519,7 @@
|
|||
clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
|
||||
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -521,7 +532,7 @@
|
|||
clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
|
||||
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -534,7 +545,7 @@
|
|||
clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
|
||||
dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -547,7 +558,7 @@
|
|||
clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
|
||||
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -558,7 +569,7 @@
|
|||
clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
|
||||
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
max-frequency = <97500000>;
|
||||
|
|
@ -571,7 +582,7 @@
|
|||
clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
|
||||
dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
max-frequency = <97500000>;
|
||||
|
|
@ -589,7 +600,8 @@
|
|||
clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
|
||||
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
max-frequency = <195000000>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -600,7 +612,8 @@
|
|||
clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
|
||||
dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
max-frequency = <195000000>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -611,7 +624,8 @@
|
|||
clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
|
||||
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
max-frequency = <97500000>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -622,7 +636,8 @@
|
|||
clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
|
||||
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
max-frequency = <97500000>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -635,7 +650,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -648,7 +663,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -661,7 +676,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -674,7 +689,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -687,7 +702,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -700,7 +715,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -714,7 +729,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -728,7 +743,21 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif2: serial@e6e56000 {
|
||||
compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
|
||||
"renesas,scif";
|
||||
reg = <0 0xe6e56000 0 64>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -742,7 +771,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -756,7 +785,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -765,7 +794,7 @@
|
|||
reg = <0 0xee700000 0 0x400>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
phy-mode = "rmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -778,7 +807,7 @@
|
|||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
|
@ -789,7 +818,7 @@
|
|||
reg = <0 0xee300000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -798,7 +827,7 @@
|
|||
reg = <0 0xee500000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -810,7 +839,7 @@
|
|||
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
||||
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
renesas,buswait = <4>;
|
||||
phys = <&usb0 1>;
|
||||
phy-names = "usb";
|
||||
|
|
@ -824,7 +853,7 @@
|
|||
#size-cells = <0>;
|
||||
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
|
||||
clock-names = "usbhs";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
usb0: usb-channel@0 {
|
||||
|
|
@ -842,7 +871,7 @@
|
|||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -851,7 +880,7 @@
|
|||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -860,7 +889,7 @@
|
|||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -869,7 +898,7 @@
|
|||
reg = <0 0xe6ef3000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -878,7 +907,7 @@
|
|||
reg = <0 0xfe920000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-sru;
|
||||
renesas,#rpf = <5>;
|
||||
|
|
@ -891,7 +920,7 @@
|
|||
reg = <0 0xfe928000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-lut;
|
||||
renesas,has-sru;
|
||||
|
|
@ -905,7 +934,7 @@
|
|||
reg = <0 0xfe930000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-lif;
|
||||
renesas,has-lut;
|
||||
|
|
@ -919,7 +948,7 @@
|
|||
reg = <0 0xfe938000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-lif;
|
||||
renesas,has-lut;
|
||||
|
|
@ -968,33 +997,33 @@
|
|||
};
|
||||
|
||||
can0: can@e6e80000 {
|
||||
compatible = "renesas,can-r8a7790";
|
||||
compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e80000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
|
||||
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6e88000 {
|
||||
compatible = "renesas,can-r8a7790";
|
||||
compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e88000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
|
||||
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
jpu: jpeg-codec@fe980000 {
|
||||
compatible = "renesas,jpu-r8a7790";
|
||||
compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
|
||||
reg = <0 0xfe980000 0 0x10300>;
|
||||
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_JPU>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
|
|
@ -1003,20 +1032,18 @@
|
|||
ranges;
|
||||
|
||||
/* External root clock */
|
||||
extal_clk: extal_clk {
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overriden by the board. */
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "extal";
|
||||
};
|
||||
|
||||
/* External PCIe clock - can be overridden by the board */
|
||||
pcie_bus_clk: pcie_bus_clk {
|
||||
pcie_bus_clk: pcie_bus {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "pcie_bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1028,19 +1055,16 @@
|
|||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "audio_clk_a";
|
||||
};
|
||||
audio_clk_b: audio_clk_b {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "audio_clk_b";
|
||||
};
|
||||
audio_clk_c: audio_clk_c {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "audio_clk_c";
|
||||
};
|
||||
|
||||
/* External SCIF clock */
|
||||
|
|
@ -1053,11 +1077,10 @@
|
|||
};
|
||||
|
||||
/* External USB clock - can be overridden by the board */
|
||||
usb_extal_clk: usb_extal_clk {
|
||||
usb_extal_clk: usb_extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
clock-output-names = "usb_extal";
|
||||
};
|
||||
|
||||
/* External CAN clock */
|
||||
|
|
@ -1066,7 +1089,6 @@
|
|||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "can_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1084,201 +1106,176 @@
|
|||
};
|
||||
|
||||
/* Variable factor clocks */
|
||||
sd2_clk: sd2_clk@e6150078 {
|
||||
sd2_clk: sd2@e6150078 {
|
||||
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150078 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd2";
|
||||
};
|
||||
sd3_clk: sd3_clk@e615026c {
|
||||
sd3_clk: sd3@e615026c {
|
||||
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615026c 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd3";
|
||||
};
|
||||
mmc0_clk: mmc0_clk@e6150240 {
|
||||
mmc0_clk: mmc0@e6150240 {
|
||||
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150240 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mmc0";
|
||||
};
|
||||
mmc1_clk: mmc1_clk@e6150244 {
|
||||
mmc1_clk: mmc1@e6150244 {
|
||||
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150244 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mmc1";
|
||||
};
|
||||
ssp_clk: ssp_clk@e6150248 {
|
||||
ssp_clk: ssp@e6150248 {
|
||||
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150248 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "ssp";
|
||||
};
|
||||
ssprs_clk: ssprs_clk@e615024c {
|
||||
ssprs_clk: ssprs@e615024c {
|
||||
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615024c 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "ssprs";
|
||||
};
|
||||
|
||||
/* Fixed factor clocks */
|
||||
pll1_div2_clk: pll1_div2_clk {
|
||||
pll1_div2_clk: pll1_div2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll1_div2";
|
||||
};
|
||||
z2_clk: z2_clk {
|
||||
z2_clk: z2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "z2";
|
||||
};
|
||||
zg_clk: zg_clk {
|
||||
zg_clk: zg {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <3>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zg";
|
||||
};
|
||||
zx_clk: zx_clk {
|
||||
zx_clk: zx {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <3>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zx";
|
||||
};
|
||||
zs_clk: zs_clk {
|
||||
zs_clk: zs {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <6>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zs";
|
||||
};
|
||||
hp_clk: hp_clk {
|
||||
hp_clk: hp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <12>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "hp";
|
||||
};
|
||||
i_clk: i_clk {
|
||||
i_clk: i {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "i";
|
||||
};
|
||||
b_clk: b_clk {
|
||||
b_clk: b {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <12>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "b";
|
||||
};
|
||||
p_clk: p_clk {
|
||||
p_clk: p {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <24>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "p";
|
||||
};
|
||||
cl_clk: cl_clk {
|
||||
cl_clk: cl {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <48>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "cl";
|
||||
};
|
||||
m2_clk: m2_clk {
|
||||
m2_clk: m2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "m2";
|
||||
};
|
||||
imp_clk: imp_clk {
|
||||
imp_clk: imp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "imp";
|
||||
};
|
||||
rclk_clk: rclk_clk {
|
||||
rclk_clk: rclk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <(48 * 1024)>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "rclk";
|
||||
};
|
||||
oscclk_clk: oscclk_clk {
|
||||
oscclk_clk: oscclk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <(12 * 1024)>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "oscclk";
|
||||
};
|
||||
zb3_clk: zb3_clk {
|
||||
zb3_clk: zb3 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zb3";
|
||||
};
|
||||
zb3d2_clk: zb3d2_clk {
|
||||
zb3d2_clk: zb3d2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zb3d2";
|
||||
};
|
||||
ddr_clk: ddr_clk {
|
||||
ddr_clk: ddr {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "ddr";
|
||||
};
|
||||
mp_clk: mp_clk {
|
||||
mp_clk: mp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <15>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "mp";
|
||||
};
|
||||
cp_clk: cp_clk {
|
||||
cp_clk: cp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&extal_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "cp";
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
|
|
@ -1334,19 +1331,19 @@
|
|||
mstp3_clks: mstp3_clks@e615013c {
|
||||
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
||||
clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
|
||||
clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
|
||||
<&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
|
||||
<&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
|
||||
<&hp_clk>, <&hp_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
|
||||
R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
|
||||
R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
|
||||
R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
|
||||
R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
|
||||
>;
|
||||
clock-output-names =
|
||||
"iic2", "tpu0", "mmcif1", "sdhi3",
|
||||
"iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
|
||||
"sdhi2", "sdhi1", "sdhi0", "mmcif0",
|
||||
"iic0", "pciec", "iic1", "ssusb", "cmt1",
|
||||
"usbdmac0", "usbdmac1";
|
||||
|
|
@ -1464,6 +1461,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a7790-sysc";
|
||||
reg = <0 0xe6180000 0 0x0200>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
qspi: spi@e6b10000 {
|
||||
compatible = "renesas,qspi-r8a7790", "renesas,qspi";
|
||||
reg = <0 0xe6b10000 0 0x2c>;
|
||||
|
|
@ -1471,7 +1474,7 @@
|
|||
clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1485,7 +1488,7 @@
|
|||
clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
|
||||
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
|
@ -1498,7 +1501,7 @@
|
|||
clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
|
||||
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
|
@ -1511,7 +1514,7 @@
|
|||
clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
|
||||
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
|
@ -1524,18 +1527,18 @@
|
|||
clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
|
||||
dmas = <&dmac0 0x45>, <&dmac0 0x46>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xhci: usb@ee000000 {
|
||||
compatible = "renesas,xhci-r8a7790";
|
||||
compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
|
||||
reg = <0 0xee000000 0 0xc00>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
phys = <&usb2 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
|
|
@ -1548,7 +1551,7 @@
|
|||
<0 0xee080000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <0 0>;
|
||||
|
|
@ -1583,7 +1586,7 @@
|
|||
<0 0xee0a0000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <1 1>;
|
||||
|
|
@ -1601,7 +1604,7 @@
|
|||
compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
|
||||
device_type = "pci";
|
||||
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
reg = <0 0xee0d0000 0 0xc00>,
|
||||
<0 0xee0c0000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -1654,7 +1657,7 @@
|
|||
interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1697,7 +1700,7 @@
|
|||
"mix.0", "mix.1",
|
||||
"dvc.0", "dvc.1",
|
||||
"clk_a", "clk_b", "clk_c", "clk_i";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
|
|||
|
|
@ -242,11 +242,10 @@
|
|||
1800000 0>;
|
||||
};
|
||||
|
||||
audio_clock: clock {
|
||||
audio_clock: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
clock-output-names = "audio_clock";
|
||||
};
|
||||
|
||||
rsnd_ak4643: sound {
|
||||
|
|
@ -324,89 +323,89 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
renesas,groups = "i2c2";
|
||||
renesas,function = "i2c2";
|
||||
groups = "i2c2";
|
||||
function = "i2c2";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
renesas,function = "du";
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
scif0_pins: serial0 {
|
||||
renesas,groups = "scif0_data_d";
|
||||
renesas,function = "scif0";
|
||||
groups = "scif0_data_d";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif1_pins: serial1 {
|
||||
renesas,groups = "scif1_data_d";
|
||||
renesas,function = "scif1";
|
||||
groups = "scif1_data_d";
|
||||
function = "scif1";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
renesas,groups = "scif_clk";
|
||||
renesas,function = "scif_clk";
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
renesas,function = "eth";
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
renesas,groups = "intc_irq0";
|
||||
renesas,function = "intc";
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,function = "sdhi0";
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
renesas,function = "sdhi1";
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,function = "sdhi2";
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
};
|
||||
|
||||
qspi_pins: spi0 {
|
||||
renesas,groups = "qspi_ctrl", "qspi_data4";
|
||||
renesas,function = "qspi";
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
msiof0_pins: spi1 {
|
||||
renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
|
||||
groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
|
||||
"msiof0_tx";
|
||||
renesas,function = "msiof0";
|
||||
function = "msiof0";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
renesas,groups = "usb0";
|
||||
renesas,function = "usb0";
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
renesas,groups = "usb1";
|
||||
renesas,function = "usb1";
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
vin1_pins: vin1 {
|
||||
renesas,groups = "vin1_data8", "vin1_clk";
|
||||
renesas,function = "vin1";
|
||||
groups = "vin1_data8", "vin1_clk";
|
||||
function = "vin1";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
renesas,function = "ssi";
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
renesas,groups = "audio_clk_a";
|
||||
renesas,function = "audio_clk";
|
||||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -113,11 +113,10 @@
|
|||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x14_clk: x14-clock {
|
||||
x14_clk: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
clock-output-names = "audio_clock";
|
||||
};
|
||||
|
||||
sound {
|
||||
|
|
@ -147,78 +146,78 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
scif0_pins: serial0 {
|
||||
renesas,groups = "scif0_data_d";
|
||||
renesas,function = "scif0";
|
||||
groups = "scif0_data_d";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
renesas,groups = "scif_clk";
|
||||
renesas,function = "scif_clk";
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
renesas,function = "eth";
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
renesas,groups = "intc_irq0";
|
||||
renesas,function = "intc";
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,function = "sdhi0";
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,function = "sdhi2";
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
};
|
||||
|
||||
qspi_pins: spi0 {
|
||||
renesas,groups = "qspi_ctrl", "qspi_data4";
|
||||
renesas,function = "qspi";
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
renesas,groups = "i2c2";
|
||||
renesas,function = "i2c2";
|
||||
groups = "i2c2";
|
||||
function = "i2c2";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
renesas,groups = "usb0";
|
||||
renesas,function = "usb0";
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
renesas,groups = "usb1";
|
||||
renesas,function = "usb1";
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
renesas,groups = "vin0_data8", "vin0_clk";
|
||||
renesas,function = "vin0";
|
||||
groups = "vin0_data8", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
can0_pins: can0 {
|
||||
renesas,groups = "can0_data";
|
||||
renesas,function = "can0";
|
||||
groups = "can0_data";
|
||||
function = "can0";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
renesas,function = "du";
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
ssi_pins: sound {
|
||||
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
renesas,function = "ssi";
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
audio_clk_pins: audio_clk {
|
||||
renesas,groups = "audio_clk_a";
|
||||
renesas,function = "audio_clk";
|
||||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include <dt-bindings/clock/r8a7791-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/r8a7791-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7791";
|
||||
|
|
@ -51,6 +52,7 @@
|
|||
voltage-tolerance = <1>; /* 1% */
|
||||
clocks = <&cpg_clocks R8A7791_CLK_Z>;
|
||||
clock-latency = <300000>; /* 300 us */
|
||||
power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
|
||||
/* kHz - uV - OPPs unknown yet */
|
||||
|
|
@ -67,6 +69,7 @@
|
|||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
clock-frequency = <1500000000>;
|
||||
power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
};
|
||||
|
|
@ -92,6 +95,7 @@
|
|||
|
||||
L2_CA15: cache-controller@0 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7791_PD_CA15_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
|
@ -118,7 +122,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
|
|
@ -131,7 +135,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
|
|
@ -144,7 +148,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
|
|
@ -157,7 +161,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
|
|
@ -170,7 +174,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
|
|
@ -183,7 +187,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055400 {
|
||||
|
|
@ -196,7 +200,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio7: gpio@e6055800 {
|
||||
|
|
@ -209,7 +213,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
thermal: thermal@e61f0000 {
|
||||
|
|
@ -219,7 +223,7 @@
|
|||
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
|
|
@ -238,7 +242,7 @@
|
|||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0x60>;
|
||||
|
||||
|
|
@ -258,7 +262,7 @@
|
|||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0xff>;
|
||||
|
||||
|
|
@ -281,7 +285,7 @@
|
|||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
|
|
@ -310,7 +314,7 @@
|
|||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
|
@ -341,7 +345,7 @@
|
|||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
|
@ -370,7 +374,7 @@
|
|||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
|
|
@ -399,7 +403,7 @@
|
|||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
|
|
@ -411,7 +415,7 @@
|
|||
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
|
@ -423,7 +427,7 @@
|
|||
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
|
@ -436,7 +440,7 @@
|
|||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -448,7 +452,7 @@
|
|||
reg = <0 0xe6518000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -460,7 +464,7 @@
|
|||
reg = <0 0xe6530000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -472,7 +476,7 @@
|
|||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -484,7 +488,7 @@
|
|||
reg = <0 0xe6520000 0 0x40>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -497,7 +501,7 @@
|
|||
reg = <0 0xe6528000 0 0x40>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -512,7 +516,7 @@
|
|||
clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
|
||||
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -525,7 +529,7 @@
|
|||
clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
|
||||
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -538,7 +542,7 @@
|
|||
clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
|
||||
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -554,7 +558,7 @@
|
|||
clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
|
||||
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
max-frequency = <97500000>;
|
||||
|
|
@ -567,7 +571,7 @@
|
|||
clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
|
||||
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -578,7 +582,7 @@
|
|||
clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
|
||||
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -589,7 +593,7 @@
|
|||
clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
|
||||
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -602,7 +606,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -615,7 +619,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -628,7 +632,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -641,7 +645,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -654,7 +658,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -667,7 +671,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -680,7 +684,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -693,7 +697,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -706,7 +710,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -720,7 +724,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -734,7 +738,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -748,7 +752,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -762,7 +766,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -776,7 +780,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -790,7 +794,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -804,7 +808,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -818,7 +822,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -832,7 +836,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -841,7 +845,7 @@
|
|||
reg = <0 0xee700000 0 0x400>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
phy-mode = "rmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -854,7 +858,7 @@
|
|||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
|
@ -865,7 +869,7 @@
|
|||
reg = <0 0xee300000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -874,7 +878,7 @@
|
|||
reg = <0 0xee500000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -886,7 +890,7 @@
|
|||
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
||||
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
renesas,buswait = <4>;
|
||||
phys = <&usb0 1>;
|
||||
phy-names = "usb";
|
||||
|
|
@ -900,7 +904,7 @@
|
|||
#size-cells = <0>;
|
||||
clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
|
||||
clock-names = "usbhs";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
usb0: usb-channel@0 {
|
||||
|
|
@ -918,7 +922,7 @@
|
|||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -927,7 +931,7 @@
|
|||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -936,7 +940,7 @@
|
|||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -945,7 +949,7 @@
|
|||
reg = <0 0xfe928000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-lut;
|
||||
renesas,has-sru;
|
||||
|
|
@ -959,7 +963,7 @@
|
|||
reg = <0 0xfe930000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-lif;
|
||||
renesas,has-lut;
|
||||
|
|
@ -973,7 +977,7 @@
|
|||
reg = <0 0xfe938000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-lif;
|
||||
renesas,has-lut;
|
||||
|
|
@ -1013,33 +1017,33 @@
|
|||
};
|
||||
|
||||
can0: can@e6e80000 {
|
||||
compatible = "renesas,can-r8a7791";
|
||||
compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e80000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
|
||||
<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6e88000 {
|
||||
compatible = "renesas,can-r8a7791";
|
||||
compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e88000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
|
||||
<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
jpu: jpeg-codec@fe980000 {
|
||||
compatible = "renesas,jpu-r8a7791";
|
||||
compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
|
||||
reg = <0 0xfe980000 0 0x10300>;
|
||||
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_JPU>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
|
|
@ -1048,12 +1052,11 @@
|
|||
ranges;
|
||||
|
||||
/* External root clock */
|
||||
extal_clk: extal_clk {
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overriden by the board. */
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "extal";
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -1064,27 +1067,23 @@
|
|||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "audio_clk_a";
|
||||
};
|
||||
audio_clk_b: audio_clk_b {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "audio_clk_b";
|
||||
};
|
||||
audio_clk_c: audio_clk_c {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "audio_clk_c";
|
||||
};
|
||||
|
||||
/* External PCIe clock - can be overridden by the board */
|
||||
pcie_bus_clk: pcie_bus_clk {
|
||||
pcie_bus_clk: pcie_bus {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "pcie_bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1098,11 +1097,10 @@
|
|||
};
|
||||
|
||||
/* External USB clock - can be overridden by the board */
|
||||
usb_extal_clk: usb_extal_clk {
|
||||
usb_extal_clk: usb_extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
clock-output-names = "usb_extal";
|
||||
};
|
||||
|
||||
/* External CAN clock */
|
||||
|
|
@ -1111,7 +1109,6 @@
|
|||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "can_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1129,178 +1126,156 @@
|
|||
};
|
||||
|
||||
/* Variable factor clocks */
|
||||
sd2_clk: sd2_clk@e6150078 {
|
||||
sd2_clk: sd2@e6150078 {
|
||||
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150078 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd2";
|
||||
};
|
||||
sd3_clk: sd3_clk@e615026c {
|
||||
sd3_clk: sd3@e615026c {
|
||||
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615026c 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd3";
|
||||
};
|
||||
mmc0_clk: mmc0_clk@e6150240 {
|
||||
mmc0_clk: mmc0@e6150240 {
|
||||
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150240 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mmc0";
|
||||
};
|
||||
ssp_clk: ssp_clk@e6150248 {
|
||||
ssp_clk: ssp@e6150248 {
|
||||
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150248 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "ssp";
|
||||
};
|
||||
ssprs_clk: ssprs_clk@e615024c {
|
||||
ssprs_clk: ssprs@e615024c {
|
||||
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615024c 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "ssprs";
|
||||
};
|
||||
|
||||
/* Fixed factor clocks */
|
||||
pll1_div2_clk: pll1_div2_clk {
|
||||
pll1_div2_clk: pll1_div2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll1_div2";
|
||||
};
|
||||
zg_clk: zg_clk {
|
||||
zg_clk: zg {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <3>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zg";
|
||||
};
|
||||
zx_clk: zx_clk {
|
||||
zx_clk: zx {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <3>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zx";
|
||||
};
|
||||
zs_clk: zs_clk {
|
||||
zs_clk: zs {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <6>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zs";
|
||||
};
|
||||
hp_clk: hp_clk {
|
||||
hp_clk: hp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <12>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "hp";
|
||||
};
|
||||
i_clk: i_clk {
|
||||
i_clk: i {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "i";
|
||||
};
|
||||
b_clk: b_clk {
|
||||
b_clk: b {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <12>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "b";
|
||||
};
|
||||
p_clk: p_clk {
|
||||
p_clk: p {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <24>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "p";
|
||||
};
|
||||
cl_clk: cl_clk {
|
||||
cl_clk: cl {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <48>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "cl";
|
||||
};
|
||||
m2_clk: m2_clk {
|
||||
m2_clk: m2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "m2";
|
||||
};
|
||||
rclk_clk: rclk_clk {
|
||||
rclk_clk: rclk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <(48 * 1024)>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "rclk";
|
||||
};
|
||||
oscclk_clk: oscclk_clk {
|
||||
oscclk_clk: oscclk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <(12 * 1024)>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "oscclk";
|
||||
};
|
||||
zb3_clk: zb3_clk {
|
||||
zb3_clk: zb3 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zb3";
|
||||
};
|
||||
zb3d2_clk: zb3d2_clk {
|
||||
zb3d2_clk: zb3d2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zb3d2";
|
||||
};
|
||||
ddr_clk: ddr_clk {
|
||||
ddr_clk: ddr {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "ddr";
|
||||
};
|
||||
mp_clk: mp_clk {
|
||||
mp_clk: mp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <15>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "mp";
|
||||
};
|
||||
cp_clk: cp_clk {
|
||||
cp_clk: cp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&extal_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "cp";
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
|
|
@ -1495,6 +1470,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a7791-sysc";
|
||||
reg = <0 0xe6180000 0 0x0200>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
qspi: spi@e6b10000 {
|
||||
compatible = "renesas,qspi-r8a7791", "renesas,qspi";
|
||||
reg = <0 0xe6b10000 0 0x2c>;
|
||||
|
|
@ -1502,7 +1483,7 @@
|
|||
clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1516,7 +1497,7 @@
|
|||
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
|
||||
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
|
@ -1529,7 +1510,7 @@
|
|||
clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
|
||||
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
|
@ -1542,18 +1523,18 @@
|
|||
clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
|
||||
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xhci: usb@ee000000 {
|
||||
compatible = "renesas,xhci-r8a7791";
|
||||
compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
|
||||
reg = <0 0xee000000 0 0xc00>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
phys = <&usb2 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
|
|
@ -1566,7 +1547,7 @@
|
|||
<0 0xee080000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <0 0>;
|
||||
|
|
@ -1601,7 +1582,7 @@
|
|||
<0 0xee0c0000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <1 1>;
|
||||
|
|
@ -1651,7 +1632,7 @@
|
|||
interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1754,7 +1735,7 @@
|
|||
"mix.0", "mix.1",
|
||||
"dvc.0", "dvc.1",
|
||||
"clk_a", "clk_b", "clk_c", "clk_i";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
|
|||
|
|
@ -158,11 +158,82 @@
|
|||
};
|
||||
};
|
||||
|
||||
audio_clock: clock {
|
||||
vcc_sdhi0: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator@1 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi1: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI1 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator@3 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi2: regulator@4 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI2 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi2: regulator@5 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI2 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
audio_clock: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
clock-output-names = "audio_clock";
|
||||
};
|
||||
|
||||
rsnd_ak4643: sound {
|
||||
|
|
@ -240,53 +311,68 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
renesas,groups = "i2c2";
|
||||
renesas,function = "i2c2";
|
||||
groups = "i2c2";
|
||||
function = "i2c2";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
renesas,function = "du";
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
scif0_pins: serial0 {
|
||||
renesas,groups = "scif0_data_d";
|
||||
renesas,function = "scif0";
|
||||
groups = "scif0_data_d";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif1_pins: serial1 {
|
||||
renesas,groups = "scif1_data_d";
|
||||
renesas,function = "scif1";
|
||||
groups = "scif1_data_d";
|
||||
function = "scif1";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
renesas,groups = "scif_clk";
|
||||
renesas,function = "scif_clk";
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
renesas,function = "eth";
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
renesas,groups = "intc_irq0";
|
||||
renesas,function = "intc";
|
||||
groups = "intc_irq0";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,function = "sdhi0";
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
renesas,function = "sdhi1";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,function = "sdhi2";
|
||||
};
|
||||
|
||||
qspi_pins: spi0 {
|
||||
renesas,groups = "qspi_ctrl", "qspi_data4";
|
||||
renesas,function = "qspi";
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
renesas,function = "ssi";
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
renesas,groups = "audio_clk_a";
|
||||
renesas,function = "audio_clk";
|
||||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -329,6 +415,38 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi2>;
|
||||
vqmmc-supply = <&vccq_sdhi2>;
|
||||
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#include <dt-bindings/clock/r8a7793-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/r8a7793-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7793";
|
||||
|
|
@ -43,6 +44,7 @@
|
|||
voltage-tolerance = <1>; /* 1% */
|
||||
clocks = <&cpg_clocks R8A7793_CLK_Z>;
|
||||
clock-latency = <300000>; /* 300 us */
|
||||
power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
|
||||
|
||||
/* kHz - uV - OPPs unknown yet */
|
||||
operating-points = <1500000 1000000>,
|
||||
|
|
@ -76,6 +78,7 @@
|
|||
|
||||
L2_CA15: cache-controller@0 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7793_PD_CA15_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
|
@ -102,7 +105,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
|
|
@ -115,7 +118,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
|
|
@ -128,7 +131,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
|
|
@ -141,7 +144,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
|
|
@ -154,7 +157,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
|
|
@ -167,7 +170,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055400 {
|
||||
|
|
@ -180,7 +183,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio7: gpio@e6055800 {
|
||||
|
|
@ -193,7 +196,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
thermal: thermal@e61f0000 {
|
||||
|
|
@ -203,7 +206,7 @@
|
|||
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
|
|
@ -222,7 +225,7 @@
|
|||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0x60>;
|
||||
|
||||
|
|
@ -242,7 +245,7 @@
|
|||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0xff>;
|
||||
|
||||
|
|
@ -265,7 +268,7 @@
|
|||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
|
|
@ -294,7 +297,7 @@
|
|||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
|
@ -325,7 +328,7 @@
|
|||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
|
@ -354,7 +357,7 @@
|
|||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
|
|
@ -383,7 +386,7 @@
|
|||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
|
|
@ -396,7 +399,7 @@
|
|||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -408,7 +411,7 @@
|
|||
reg = <0 0xe6518000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -420,7 +423,7 @@
|
|||
reg = <0 0xe6530000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -432,7 +435,7 @@
|
|||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -444,7 +447,7 @@
|
|||
reg = <0 0xe6520000 0 0x40>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -457,7 +460,7 @@
|
|||
reg = <0 0xe6528000 0 0x40>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -472,7 +475,7 @@
|
|||
clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
|
||||
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -485,7 +488,7 @@
|
|||
clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
|
||||
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -498,7 +501,7 @@
|
|||
clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
|
||||
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -507,6 +510,39 @@
|
|||
reg = <0 0xe6060000 0 0x250>;
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7793";
|
||||
reg = <0 0xee100000 0 0x328>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
|
||||
dmas = <&dmac0 0xcd>, <&dmac0 0xce>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a7793";
|
||||
reg = <0 0xee140000 0 0x100>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
|
||||
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a7793";
|
||||
reg = <0 0xee160000 0 0x100>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
|
||||
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scifa0: serial@e6c40000 {
|
||||
compatible = "renesas,scifa-r8a7793",
|
||||
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||
|
|
@ -516,7 +552,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -529,7 +565,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -542,7 +578,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -555,7 +591,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -568,7 +604,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -581,7 +617,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -594,7 +630,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -607,7 +643,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -620,7 +656,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -634,7 +670,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -648,7 +684,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -662,7 +698,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -676,7 +712,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -690,7 +726,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -704,7 +740,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -718,7 +754,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -732,7 +768,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -746,7 +782,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -755,7 +791,7 @@
|
|||
reg = <0 0xee700000 0 0x400>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
phy-mode = "rmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -769,7 +805,7 @@
|
|||
clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -806,18 +842,39 @@
|
|||
};
|
||||
};
|
||||
|
||||
can0: can@e6e80000 {
|
||||
compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e80000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
|
||||
<&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6e88000 {
|
||||
compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e88000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
|
||||
<&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* External root clock */
|
||||
extal_clk: extal_clk {
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "extal";
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -828,19 +885,32 @@
|
|||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "audio_clk_a";
|
||||
};
|
||||
audio_clk_b: audio_clk_b {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "audio_clk_b";
|
||||
};
|
||||
audio_clk_c: audio_clk_c {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "audio_clk_c";
|
||||
};
|
||||
|
||||
/* External USB clock - can be overridden by the board */
|
||||
usb_extal_clk: usb_extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
/* External CAN clock */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* External SCIF clock */
|
||||
|
|
@ -857,7 +927,7 @@
|
|||
compatible = "renesas,r8a7793-cpg-clocks",
|
||||
"renesas,rcar-gen2-cpg-clocks";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>;
|
||||
clocks = <&extal_clk &usb_extal_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "main", "pll0", "pll1", "pll3",
|
||||
"lb", "qspi", "sdh", "sd0", "z",
|
||||
|
|
@ -866,111 +936,98 @@
|
|||
};
|
||||
|
||||
/* Variable factor clocks */
|
||||
sd2_clk: sd2_clk@e6150078 {
|
||||
sd2_clk: sd2@e6150078 {
|
||||
compatible = "renesas,r8a7793-div6-clock",
|
||||
"renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150078 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd2";
|
||||
};
|
||||
sd3_clk: sd3_clk@e615026c {
|
||||
sd3_clk: sd3@e615026c {
|
||||
compatible = "renesas,r8a7793-div6-clock",
|
||||
"renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615026c 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd3";
|
||||
};
|
||||
mmc0_clk: mmc0_clk@e6150240 {
|
||||
mmc0_clk: mmc0@e6150240 {
|
||||
compatible = "renesas,r8a7793-div6-clock",
|
||||
"renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150240 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mmc0";
|
||||
};
|
||||
|
||||
/* Fixed factor clocks */
|
||||
pll1_div2_clk: pll1_div2_clk {
|
||||
pll1_div2_clk: pll1_div2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll1_div2";
|
||||
};
|
||||
zg_clk: zg_clk {
|
||||
zg_clk: zg {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <5>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zg";
|
||||
};
|
||||
zx_clk: zx_clk {
|
||||
zx_clk: zx {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <3>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zx";
|
||||
};
|
||||
zs_clk: zs_clk {
|
||||
zs_clk: zs {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <6>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zs";
|
||||
};
|
||||
hp_clk: hp_clk {
|
||||
hp_clk: hp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <12>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "hp";
|
||||
};
|
||||
p_clk: p_clk {
|
||||
p_clk: p {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <24>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "p";
|
||||
};
|
||||
m2_clk: m2_clk {
|
||||
m2_clk: m2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "m2";
|
||||
};
|
||||
rclk_clk: rclk_clk {
|
||||
rclk_clk: rclk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <(48 * 1024)>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "rclk";
|
||||
};
|
||||
mp_clk: mp_clk {
|
||||
mp_clk: mp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <15>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "mp";
|
||||
};
|
||||
cp_clk: cp_clk {
|
||||
cp_clk: cp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&extal_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "cp";
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
|
|
@ -1098,6 +1155,7 @@
|
|||
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
|
||||
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
||||
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
||||
<&p_clk>, <&p_clk>,
|
||||
<&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
|
||||
<&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
|
||||
<&hp_clk>, <&hp_clk>;
|
||||
|
|
@ -1107,7 +1165,8 @@
|
|||
R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
|
||||
R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
|
||||
R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
|
||||
R8A7793_CLK_QSPI_MOD R8A7793_CLK_I2C5
|
||||
R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
|
||||
R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
|
||||
R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
|
||||
R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
|
||||
R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
|
||||
|
|
@ -1115,8 +1174,9 @@
|
|||
clock-output-names =
|
||||
"gpio7", "gpio6", "gpio5", "gpio4",
|
||||
"gpio3", "gpio2", "gpio1", "gpio0",
|
||||
"qspi_mod", "i2c5", "i2c6", "i2c4",
|
||||
"i2c3", "i2c2", "i2c1", "i2c0";
|
||||
"rcan1", "rcan0", "qspi_mod", "i2c5",
|
||||
"i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
|
||||
"i2c0";
|
||||
};
|
||||
mstp10_clks: mstp10_clks@e6150998 {
|
||||
compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
|
|
@ -1166,6 +1226,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a7793-sysc";
|
||||
reg = <0 0xe6180000 0 0x0200>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_sy0: mmu@e6280000 {
|
||||
compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6280000 0 0x1000>;
|
||||
|
|
@ -1261,7 +1327,7 @@
|
|||
"src.4", "src.3", "src.2", "src.1", "src.0",
|
||||
"dvc.0", "dvc.1",
|
||||
"clk_a", "clk_b", "clk_c", "clk_i";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
|
|||
|
|
@ -107,38 +107,38 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
du_pins: du {
|
||||
renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
|
||||
renesas,function = "du";
|
||||
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
scif2_pins: serial2 {
|
||||
renesas,groups = "scif2_data";
|
||||
renesas,function = "scif2";
|
||||
groups = "scif2_data";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
renesas,groups = "scif_clk";
|
||||
renesas,function = "scif_clk";
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
renesas,function = "eth";
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
renesas,groups = "intc_irq8";
|
||||
renesas,function = "intc";
|
||||
groups = "intc_irq8";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
renesas,groups = "i2c1";
|
||||
renesas,function = "i2c1";
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
renesas,groups = "vin0_data8", "vin0_clk";
|
||||
renesas,function = "vin0";
|
||||
groups = "vin0_data8", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -148,8 +148,8 @@
|
|||
|
||||
&pfc {
|
||||
qspi_pins: spi0 {
|
||||
renesas,groups = "qspi_ctrl", "qspi_data4";
|
||||
renesas,function = "qspi";
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -130,58 +130,58 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
scif2_pins: serial2 {
|
||||
renesas,groups = "scif2_data";
|
||||
renesas,function = "scif2";
|
||||
groups = "scif2_data";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
renesas,groups = "scif_clk";
|
||||
renesas,function = "scif_clk";
|
||||
groups = "scif_clk";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
renesas,function = "eth";
|
||||
groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
function = "eth";
|
||||
};
|
||||
|
||||
phy1_pins: phy1 {
|
||||
renesas,groups = "intc_irq8";
|
||||
renesas,function = "intc";
|
||||
groups = "intc_irq8";
|
||||
function = "intc";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
renesas,groups = "i2c1";
|
||||
renesas,function = "i2c1";
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
mmcif0_pins: mmcif0 {
|
||||
renesas,groups = "mmc_data8", "mmc_ctrl";
|
||||
renesas,function = "mmc";
|
||||
groups = "mmc_data8", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
renesas,function = "sdhi1";
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
};
|
||||
|
||||
qspi_pins: spi0 {
|
||||
renesas,groups = "qspi_ctrl", "qspi_data4";
|
||||
renesas,function = "qspi";
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
renesas,groups = "vin0_data8", "vin0_clk";
|
||||
renesas,function = "vin0";
|
||||
groups = "vin0_data8", "vin0_clk";
|
||||
function = "vin0";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
renesas,groups = "usb0";
|
||||
renesas,function = "usb0";
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
renesas,groups = "usb1";
|
||||
renesas,function = "usb1";
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <dt-bindings/clock/r8a7794-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/r8a7794-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7794";
|
||||
|
|
@ -26,6 +27,8 @@
|
|||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
i2c7 = &i2c7;
|
||||
spi0 = &qspi;
|
||||
vin0 = &vin0;
|
||||
vin1 = &vin1;
|
||||
|
|
@ -40,6 +43,7 @@
|
|||
compatible = "arm,cortex-a7";
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000000>;
|
||||
power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
|
||||
|
|
@ -48,12 +52,14 @@
|
|||
compatible = "arm,cortex-a7";
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000000>;
|
||||
power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_CA7: cache-controller@1 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7794_PD_CA7_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
|
@ -80,7 +86,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
|
|
@ -93,7 +99,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
|
|
@ -106,7 +112,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
|
|
@ -119,7 +125,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
|
|
@ -132,7 +138,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
|
|
@ -145,7 +151,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055400 {
|
||||
|
|
@ -158,7 +164,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
cmt0: timer@ffca0000 {
|
||||
|
|
@ -168,7 +174,7 @@
|
|||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0x60>;
|
||||
|
||||
|
|
@ -188,7 +194,7 @@
|
|||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0xff>;
|
||||
|
||||
|
|
@ -219,7 +225,7 @@
|
|||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
|
|
@ -253,7 +259,7 @@
|
|||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
|
@ -284,7 +290,7 @@
|
|||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
|
@ -298,7 +304,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -311,7 +317,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -324,7 +330,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -337,7 +343,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -350,7 +356,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -363,7 +369,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -376,7 +382,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -389,7 +395,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -402,7 +408,7 @@
|
|||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -416,7 +422,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -430,7 +436,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -444,7 +450,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -458,7 +464,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -472,7 +478,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -486,7 +492,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -500,7 +506,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -514,7 +520,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -528,7 +534,7 @@
|
|||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -537,7 +543,7 @@
|
|||
reg = <0 0xee700000 0 0x400>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
phy-mode = "rmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -550,7 +556,7 @@
|
|||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
|
@ -562,7 +568,7 @@
|
|||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
|
|
@ -574,7 +580,7 @@
|
|||
reg = <0 0xe6518000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
|
|
@ -586,7 +592,7 @@
|
|||
reg = <0 0xe6530000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
|
|
@ -598,7 +604,7 @@
|
|||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
|
|
@ -610,7 +616,7 @@
|
|||
reg = <0 0xe6520000 0 0x40>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
|
|
@ -622,13 +628,39 @@
|
|||
reg = <0 0xe6528000 0 0x40>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@e6500000 {
|
||||
compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
|
||||
reg = <0 0xe6500000 0 0x425>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
|
||||
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@e6510000 {
|
||||
compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
|
||||
reg = <0 0xe6510000 0 0x425>;
|
||||
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
|
||||
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmcif0: mmc@ee200000 {
|
||||
compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
|
||||
reg = <0 0xee200000 0 0x80>;
|
||||
|
|
@ -636,7 +668,7 @@
|
|||
clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
|
||||
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -646,7 +678,7 @@
|
|||
reg = <0 0xee100000 0 0x200>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -655,7 +687,7 @@
|
|||
reg = <0 0xee140000 0 0x100>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -664,7 +696,7 @@
|
|||
reg = <0 0xee160000 0 0x100>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -675,7 +707,7 @@
|
|||
clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -687,7 +719,7 @@
|
|||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -696,7 +728,7 @@
|
|||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -707,7 +739,7 @@
|
|||
<0 0xee080000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <0 0>;
|
||||
|
|
@ -742,7 +774,7 @@
|
|||
<0 0xee0c0000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <1 1>;
|
||||
|
|
@ -775,7 +807,7 @@
|
|||
reg = <0 0xe6590000 0 0x100>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
renesas,buswait = <4>;
|
||||
phys = <&usb0 1>;
|
||||
phy-names = "usb";
|
||||
|
|
@ -789,7 +821,7 @@
|
|||
#size-cells = <0>;
|
||||
clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
|
||||
clock-names = "usbhs";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
usb0: usb-channel@0 {
|
||||
|
|
@ -830,18 +862,55 @@
|
|||
};
|
||||
};
|
||||
|
||||
can0: can@e6e80000 {
|
||||
compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e80000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
|
||||
<&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6e88000 {
|
||||
compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e88000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
|
||||
<&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* External root clock */
|
||||
extal_clk: extal_clk {
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overriden by the board. */
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "extal";
|
||||
};
|
||||
|
||||
/* External USB clock - can be overridden by the board */
|
||||
usb_extal_clk: usb_extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
/* External CAN clock */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* External SCIF clock */
|
||||
|
|
@ -858,180 +927,160 @@
|
|||
compatible = "renesas,r8a7794-cpg-clocks",
|
||||
"renesas,rcar-gen2-cpg-clocks";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>;
|
||||
clocks = <&extal_clk &usb_extal_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "main", "pll0", "pll1", "pll3",
|
||||
"lb", "qspi", "sdh", "sd0", "z";
|
||||
"lb", "qspi", "sdh", "sd0", "z",
|
||||
"rcan";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
/* Variable factor clocks */
|
||||
sd2_clk: sd2_clk@e6150078 {
|
||||
sd2_clk: sd2@e6150078 {
|
||||
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150078 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd2";
|
||||
};
|
||||
sd3_clk: sd3_clk@e615026c {
|
||||
sd3_clk: sd3@e615026c {
|
||||
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615026c 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd3";
|
||||
};
|
||||
mmc0_clk: mmc0_clk@e6150240 {
|
||||
mmc0_clk: mmc0@e6150240 {
|
||||
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150240 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mmc0";
|
||||
};
|
||||
|
||||
/* Fixed factor clocks */
|
||||
pll1_div2_clk: pll1_div2_clk {
|
||||
pll1_div2_clk: pll1_div2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll1_div2";
|
||||
};
|
||||
zg_clk: zg_clk {
|
||||
zg_clk: zg {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <6>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zg";
|
||||
};
|
||||
zx_clk: zx_clk {
|
||||
zx_clk: zx {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <3>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zx";
|
||||
};
|
||||
zs_clk: zs_clk {
|
||||
zs_clk: zs {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <6>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zs";
|
||||
};
|
||||
hp_clk: hp_clk {
|
||||
hp_clk: hp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <12>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "hp";
|
||||
};
|
||||
i_clk: i_clk {
|
||||
i_clk: i {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "i";
|
||||
};
|
||||
b_clk: b_clk {
|
||||
b_clk: b {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <12>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "b";
|
||||
};
|
||||
p_clk: p_clk {
|
||||
p_clk: p {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <24>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "p";
|
||||
};
|
||||
cl_clk: cl_clk {
|
||||
cl_clk: cl {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <48>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "cl";
|
||||
};
|
||||
m2_clk: m2_clk {
|
||||
m2_clk: m2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "m2";
|
||||
};
|
||||
rclk_clk: rclk_clk {
|
||||
rclk_clk: rclk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <(48 * 1024)>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "rclk";
|
||||
};
|
||||
oscclk_clk: oscclk_clk {
|
||||
oscclk_clk: oscclk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <(12 * 1024)>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "oscclk";
|
||||
};
|
||||
zb3_clk: zb3_clk {
|
||||
zb3_clk: zb3 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zb3";
|
||||
};
|
||||
zb3d2_clk: zb3d2_clk {
|
||||
zb3d2_clk: zb3d2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "zb3d2";
|
||||
};
|
||||
ddr_clk: ddr_clk {
|
||||
ddr_clk: ddr {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "ddr";
|
||||
};
|
||||
mp_clk: mp_clk {
|
||||
mp_clk: mp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <15>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "mp";
|
||||
};
|
||||
cp_clk: cp_clk {
|
||||
cp_clk: cp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <48>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "cp";
|
||||
};
|
||||
|
||||
acp_clk: acp_clk {
|
||||
acp_clk: acp {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&extal_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "acp";
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
|
|
@ -1082,16 +1131,19 @@
|
|||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
||||
clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
|
||||
<&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
|
||||
<&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
|
||||
<&hp_clk>, <&hp_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
|
||||
R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
|
||||
R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
|
||||
R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
|
||||
R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
|
||||
>;
|
||||
clock-output-names =
|
||||
"sdhi2", "sdhi1", "sdhi0",
|
||||
"mmcif0", "cmt1", "usbdmac0", "usbdmac1";
|
||||
"mmcif0", "i2c6", "i2c7",
|
||||
"cmt1", "usbdmac0", "usbdmac1";
|
||||
};
|
||||
mstp4_clks: mstp4_clks@e6150140 {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
|
|
@ -1137,20 +1189,22 @@
|
|||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
|
||||
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
||||
<&cp_clk>, <&cp_clk>, <&cp_clk>,
|
||||
<&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
|
||||
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
|
||||
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
|
||||
<&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
|
||||
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
|
||||
<&hp_clk>, <&hp_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
|
||||
R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
|
||||
R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
|
||||
R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD
|
||||
R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
|
||||
R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
|
||||
R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
|
||||
R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
|
||||
R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
|
||||
clock-output-names =
|
||||
"gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
|
||||
"gpio1", "gpio0", "qspi_mod",
|
||||
"gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
|
||||
"i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
|
||||
};
|
||||
mstp11_clks: mstp11_clks@e615099c {
|
||||
|
|
@ -1165,6 +1219,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a7794-sysc";
|
||||
reg = <0 0xe6180000 0 0x0200>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_sy0: mmu@e6280000 {
|
||||
compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6280000 0 0x1000>;
|
||||
|
|
|
|||
|
|
@ -149,6 +149,13 @@
|
|||
label = "SW1";
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
wakeup-key {
|
||||
gpios = <&pfc 159 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WAKEUP>;
|
||||
label = "NMI";
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
|
|
@ -329,41 +336,41 @@
|
|||
|
||||
&pfc {
|
||||
i2c3_pins: i2c3 {
|
||||
renesas,groups = "i2c3_1";
|
||||
renesas,function = "i2c3";
|
||||
groups = "i2c3_1";
|
||||
function = "i2c3";
|
||||
};
|
||||
|
||||
mmcif_pins: mmc {
|
||||
mux {
|
||||
renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
|
||||
renesas,function = "mmc0";
|
||||
groups = "mmc0_data8_0", "mmc0_ctrl_0";
|
||||
function = "mmc0";
|
||||
};
|
||||
cfg {
|
||||
renesas,groups = "mmc0_data8_0";
|
||||
renesas,pins = "PORT279";
|
||||
groups = "mmc0_data8_0";
|
||||
pins = "PORT279";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
scifa4_pins: serial4 {
|
||||
renesas,groups = "scifa4_data", "scifa4_ctrl";
|
||||
renesas,function = "scifa4";
|
||||
groups = "scifa4_data", "scifa4_ctrl";
|
||||
function = "scifa4";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
|
||||
renesas,function = "sdhi0";
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
|
||||
function = "sdhi0";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,function = "sdhi2";
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
};
|
||||
|
||||
fsia_pins: sounda {
|
||||
renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
|
||||
"fsia_data_in", "fsia_data_out";
|
||||
renesas,function = "fsia";
|
||||
groups = "fsia_mclk_in", "fsia_sclk_in",
|
||||
"fsia_data_in", "fsia_data_out";
|
||||
function = "fsia";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@
|
|||
timer@f0000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xf0000600 0x20>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
|
||||
clocks = <&twd_clk>;
|
||||
};
|
||||
|
||||
|
|
@ -602,39 +602,33 @@
|
|||
ranges;
|
||||
|
||||
/* External root clocks */
|
||||
extalr_clk: extalr_clk {
|
||||
extalr_clk: extalr {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "extalr";
|
||||
};
|
||||
extal1_clk: extal1_clk {
|
||||
extal1_clk: extal1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
clock-output-names = "extal1";
|
||||
};
|
||||
extal2_clk: extal2_clk {
|
||||
extal2_clk: extal2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "extal2";
|
||||
};
|
||||
extcki_clk: extcki_clk {
|
||||
extcki_clk: extcki {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "extcki";
|
||||
};
|
||||
fsiack_clk: fsiack_clk {
|
||||
fsiack_clk: fsiack {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "fsiack";
|
||||
};
|
||||
fsibck_clk: fsibck_clk {
|
||||
fsibck_clk: fsibck {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "fsibck";
|
||||
};
|
||||
|
||||
/* Special CPG clocks */
|
||||
|
|
@ -650,7 +644,7 @@
|
|||
};
|
||||
|
||||
/* Variable factor clocks (DIV6) */
|
||||
vclk1_clk: vclk1_clk@e6150008 {
|
||||
vclk1_clk: vclk1@e6150008 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150008 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
||||
|
|
@ -658,9 +652,8 @@
|
|||
<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
|
||||
<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "vclk1";
|
||||
};
|
||||
vclk2_clk: vclk2_clk@e615000c {
|
||||
vclk2_clk: vclk2@e615000c {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe615000c 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
||||
|
|
@ -668,9 +661,8 @@
|
|||
<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
|
||||
<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "vclk2";
|
||||
};
|
||||
vclk3_clk: vclk3_clk@e615001c {
|
||||
vclk3_clk: vclk3@e615001c {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe615001c 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
||||
|
|
@ -678,7 +670,6 @@
|
|||
<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
|
||||
<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "vclk3";
|
||||
};
|
||||
zb_clk: zb_clk@e6150010 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
|
|
@ -688,168 +679,148 @@
|
|||
#clock-cells = <0>;
|
||||
clock-output-names = "zb";
|
||||
};
|
||||
flctl_clk: flctl_clk@e6150014 {
|
||||
flctl_clk: flctlck@e6150014 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150014 4>;
|
||||
clocks = <&pll1_div2_clk>, <0>,
|
||||
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "flctlck";
|
||||
};
|
||||
sdhi0_clk: sdhi0_clk@e6150074 {
|
||||
sdhi0_clk: sdhi0ck@e6150074 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150074 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
||||
<&pll1_div13_clk>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sdhi0ck";
|
||||
};
|
||||
sdhi1_clk: sdhi1_clk@e6150078 {
|
||||
sdhi1_clk: sdhi1ck@e6150078 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150078 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
||||
<&pll1_div13_clk>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sdhi1ck";
|
||||
};
|
||||
sdhi2_clk: sdhi2_clk@e615007c {
|
||||
sdhi2_clk: sdhi2ck@e615007c {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe615007c 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
||||
<&pll1_div13_clk>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sdhi2ck";
|
||||
};
|
||||
fsia_clk: fsia_clk@e6150018 {
|
||||
fsia_clk: fsia@e6150018 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150018 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
||||
<&fsiack_clk>, <&fsiack_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "fsia";
|
||||
};
|
||||
fsib_clk: fsib_clk@e6150090 {
|
||||
fsib_clk: fsib@e6150090 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150090 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
||||
<&fsibck_clk>, <&fsibck_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "fsib";
|
||||
};
|
||||
sub_clk: sub_clk@e6150080 {
|
||||
sub_clk: sub@e6150080 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150080 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
||||
<&extal2_clk>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sub";
|
||||
};
|
||||
spua_clk: spua_clk@e6150084 {
|
||||
spua_clk: spua@e6150084 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150084 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
||||
<&extal2_clk>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "spua";
|
||||
};
|
||||
spuv_clk: spuv_clk@e6150094 {
|
||||
spuv_clk: spuv@e6150094 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150094 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
||||
<&extal2_clk>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "spuv";
|
||||
};
|
||||
msu_clk: msu_clk@e6150088 {
|
||||
msu_clk: msu@e6150088 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150088 4>;
|
||||
clocks = <&pll1_div2_clk>, <0>,
|
||||
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "msu";
|
||||
};
|
||||
hsi_clk: hsi_clk@e615008c {
|
||||
hsi_clk: hsi@e615008c {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe615008c 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
||||
<&pll1_div7_clk>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "hsi";
|
||||
};
|
||||
mfg1_clk: mfg1_clk@e6150098 {
|
||||
mfg1_clk: mfg1@e6150098 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150098 4>;
|
||||
clocks = <&pll1_div2_clk>, <0>,
|
||||
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mfg1";
|
||||
};
|
||||
mfg2_clk: mfg2_clk@e615009c {
|
||||
mfg2_clk: mfg2@e615009c {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe615009c 4>;
|
||||
clocks = <&pll1_div2_clk>, <0>,
|
||||
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mfg2";
|
||||
};
|
||||
dsit_clk: dsit_clk@e6150060 {
|
||||
dsit_clk: dsit@e6150060 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150060 4>;
|
||||
clocks = <&pll1_div2_clk>, <0>,
|
||||
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "dsit";
|
||||
};
|
||||
dsi0p_clk: dsi0p_clk@e6150064 {
|
||||
dsi0p_clk: dsi0pck@e6150064 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150064 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
||||
<&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
|
||||
<&extcki_clk>, <0>, <0>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "dsi0pck";
|
||||
};
|
||||
|
||||
/* Fixed factor clocks */
|
||||
main_div2_clk: main_div2_clk {
|
||||
main_div2_clk: main_div2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "main_div2";
|
||||
};
|
||||
pll1_div2_clk: pll1_div2_clk {
|
||||
pll1_div2_clk: pll1_div2 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll1_div2";
|
||||
};
|
||||
pll1_div7_clk: pll1_div7_clk {
|
||||
pll1_div7_clk: pll1_div7 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <7>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll1_div7";
|
||||
};
|
||||
pll1_div13_clk: pll1_div13_clk {
|
||||
pll1_div13_clk: pll1_div13 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <13>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll1_div13";
|
||||
};
|
||||
twd_clk: twd_clk {
|
||||
twd_clk: twd {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks SH73A0_CLK_Z>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "twd";
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
|
|
|
|||
|
|
@ -4,11 +4,6 @@ config ARCH_SHMOBILE
|
|||
config ARCH_SHMOBILE_MULTI
|
||||
bool
|
||||
|
||||
config PM_RCAR
|
||||
bool
|
||||
select PM
|
||||
select PM_GENERIC_DOMAINS
|
||||
|
||||
config PM_RMOBILE
|
||||
bool
|
||||
select PM
|
||||
|
|
@ -16,13 +11,15 @@ config PM_RMOBILE
|
|||
|
||||
config ARCH_RCAR_GEN1
|
||||
bool
|
||||
select PM_RCAR
|
||||
select PM
|
||||
select PM_GENERIC_DOMAINS
|
||||
select RENESAS_INTC_IRQPIN
|
||||
select SYS_SUPPORTS_SH_TMU
|
||||
|
||||
config ARCH_RCAR_GEN2
|
||||
bool
|
||||
select PM_RCAR
|
||||
select PM
|
||||
select PM_GENERIC_DOMAINS
|
||||
select RENESAS_IRQC
|
||||
select SYS_SUPPORTS_SH_CMT
|
||||
select PCI_DOMAINS if PCI
|
||||
|
|
|
|||
|
|
@ -39,7 +39,6 @@ smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o
|
|||
# PM objects
|
||||
obj-$(CONFIG_SUSPEND) += suspend.o
|
||||
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
|
||||
obj-$(CONFIG_PM_RCAR) += pm-rcar.o
|
||||
obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o
|
||||
obj-$(CONFIG_ARCH_RCAR_GEN2) += pm-rcar-gen2.o
|
||||
|
||||
|
|
|
|||
|
|
@ -9,9 +9,10 @@
|
|||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/soc/renesas/rcar-sysc.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#include "pm-rcar.h"
|
||||
#include "r8a7779.h"
|
||||
|
||||
/* SYSC */
|
||||
|
|
|
|||
|
|
@ -13,9 +13,9 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/soc/renesas/rcar-sysc.h>
|
||||
#include <asm/io.h>
|
||||
#include "common.h"
|
||||
#include "pm-rcar.h"
|
||||
#include "rcar-gen2.h"
|
||||
|
||||
/* RST */
|
||||
|
|
|
|||
|
|
@ -1,164 +0,0 @@
|
|||
/*
|
||||
* R-Car SYSC Power management support
|
||||
*
|
||||
* Copyright (C) 2014 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include "pm-rcar.h"
|
||||
|
||||
/* SYSC Common */
|
||||
#define SYSCSR 0x00 /* SYSC Status Register */
|
||||
#define SYSCISR 0x04 /* Interrupt Status Register */
|
||||
#define SYSCISCR 0x08 /* Interrupt Status Clear Register */
|
||||
#define SYSCIER 0x0c /* Interrupt Enable Register */
|
||||
#define SYSCIMR 0x10 /* Interrupt Mask Register */
|
||||
|
||||
/* SYSC Status Register */
|
||||
#define SYSCSR_PONENB 1 /* Ready for power resume requests */
|
||||
#define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
|
||||
|
||||
/*
|
||||
* Power Control Register Offsets inside the register block for each domain
|
||||
* Note: The "CR" registers for ARM cores exist on H1 only
|
||||
* Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
|
||||
*/
|
||||
#define PWRSR_OFFS 0x00 /* Power Status Register */
|
||||
#define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
|
||||
#define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
|
||||
#define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
|
||||
#define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
|
||||
#define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
|
||||
|
||||
|
||||
#define SYSCSR_RETRIES 100
|
||||
#define SYSCSR_DELAY_US 1
|
||||
|
||||
#define PWRER_RETRIES 100
|
||||
#define PWRER_DELAY_US 1
|
||||
|
||||
#define SYSCISR_RETRIES 1000
|
||||
#define SYSCISR_DELAY_US 1
|
||||
|
||||
static void __iomem *rcar_sysc_base;
|
||||
static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
|
||||
|
||||
static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
|
||||
{
|
||||
unsigned int sr_bit, reg_offs;
|
||||
int k;
|
||||
|
||||
if (on) {
|
||||
sr_bit = SYSCSR_PONENB;
|
||||
reg_offs = PWRONCR_OFFS;
|
||||
} else {
|
||||
sr_bit = SYSCSR_POFFENB;
|
||||
reg_offs = PWROFFCR_OFFS;
|
||||
}
|
||||
|
||||
/* Wait until SYSC is ready to accept a power request */
|
||||
for (k = 0; k < SYSCSR_RETRIES; k++) {
|
||||
if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
|
||||
break;
|
||||
udelay(SYSCSR_DELAY_US);
|
||||
}
|
||||
|
||||
if (k == SYSCSR_RETRIES)
|
||||
return -EAGAIN;
|
||||
|
||||
/* Submit power shutoff or power resume request */
|
||||
iowrite32(BIT(sysc_ch->chan_bit),
|
||||
rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
|
||||
{
|
||||
unsigned int isr_mask = BIT(sysc_ch->isr_bit);
|
||||
unsigned int chan_mask = BIT(sysc_ch->chan_bit);
|
||||
unsigned int status;
|
||||
unsigned long flags;
|
||||
int ret = 0;
|
||||
int k;
|
||||
|
||||
spin_lock_irqsave(&rcar_sysc_lock, flags);
|
||||
|
||||
iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
|
||||
|
||||
/* Submit power shutoff or resume request until it was accepted */
|
||||
for (k = 0; k < PWRER_RETRIES; k++) {
|
||||
ret = rcar_sysc_pwr_on_off(sysc_ch, on);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
status = ioread32(rcar_sysc_base +
|
||||
sysc_ch->chan_offs + PWRER_OFFS);
|
||||
if (!(status & chan_mask))
|
||||
break;
|
||||
|
||||
udelay(PWRER_DELAY_US);
|
||||
}
|
||||
|
||||
if (k == PWRER_RETRIES) {
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Wait until the power shutoff or resume request has completed * */
|
||||
for (k = 0; k < SYSCISR_RETRIES; k++) {
|
||||
if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
|
||||
break;
|
||||
udelay(SYSCISR_DELAY_US);
|
||||
}
|
||||
|
||||
if (k == SYSCISR_RETRIES)
|
||||
ret = -EIO;
|
||||
|
||||
iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
|
||||
|
||||
out:
|
||||
spin_unlock_irqrestore(&rcar_sysc_lock, flags);
|
||||
|
||||
pr_debug("sysc power domain %d: %08x -> %d\n",
|
||||
sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch)
|
||||
{
|
||||
return rcar_sysc_power(sysc_ch, false);
|
||||
}
|
||||
|
||||
int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch)
|
||||
{
|
||||
return rcar_sysc_power(sysc_ch, true);
|
||||
}
|
||||
|
||||
bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
|
||||
{
|
||||
unsigned int st;
|
||||
|
||||
st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
|
||||
if (st & BIT(sysc_ch->chan_bit))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void __iomem *rcar_sysc_init(phys_addr_t base)
|
||||
{
|
||||
rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
|
||||
if (!rcar_sysc_base)
|
||||
panic("unable to ioremap R-Car SYSC hardware block\n");
|
||||
|
||||
return rcar_sysc_base;
|
||||
}
|
||||
|
|
@ -19,13 +19,13 @@
|
|||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/soc/renesas/rcar-sysc.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "pm-rcar.h"
|
||||
#include "r8a7779.h"
|
||||
|
||||
#define AVECR IOMEM(0xfe700040)
|
||||
|
|
|
|||
|
|
@ -17,12 +17,12 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/soc/renesas/rcar-sysc.h>
|
||||
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "platsmp-apmu.h"
|
||||
#include "pm-rcar.h"
|
||||
#include "rcar-gen2.h"
|
||||
#include "r8a7790.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -201,6 +201,7 @@ source "drivers/clk/bcm/Kconfig"
|
|||
source "drivers/clk/hisilicon/Kconfig"
|
||||
source "drivers/clk/mvebu/Kconfig"
|
||||
source "drivers/clk/qcom/Kconfig"
|
||||
source "drivers/clk/renesas/Kconfig"
|
||||
source "drivers/clk/samsung/Kconfig"
|
||||
source "drivers/clk/tegra/Kconfig"
|
||||
source "drivers/clk/ti/Kconfig"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
config CLK_RENESAS_CPG_MSSR
|
||||
bool
|
||||
default y if ARCH_R8A7795
|
||||
|
||||
config CLK_RENESAS_CPG_MSTP
|
||||
bool
|
||||
default y if ARCH_R7S72100
|
||||
default y if ARCH_R8A73A4
|
||||
default y if ARCH_R8A7740
|
||||
default y if ARCH_R8A7778
|
||||
default y if ARCH_R8A7779
|
||||
default y if ARCH_R8A7790
|
||||
default y if ARCH_R8A7791
|
||||
default y if ARCH_R8A7793
|
||||
default y if ARCH_R8A7794
|
||||
default y if ARCH_SH73A0
|
||||
|
|
@ -1,13 +1,15 @@
|
|||
obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
|
||||
obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o clk-mstp.o
|
||||
obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-mstp.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-mstp.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o clk-mstp.o
|
||||
obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o clk-mstp.o
|
||||
obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_R8A7795) += renesas-cpg-mssr.o \
|
||||
r8a7795-cpg-mssr.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-mstp.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
|
||||
obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
|
||||
obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
|
||||
obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o
|
||||
obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o
|
||||
obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-div6.o
|
||||
|
||||
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o
|
||||
obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o
|
||||
|
|
|
|||
|
|
@ -243,9 +243,7 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
|
|||
}
|
||||
CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
|
||||
|
||||
|
||||
#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
|
||||
int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
|
||||
int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
|
||||
{
|
||||
struct device_node *np = dev->of_node;
|
||||
struct of_phandle_args clkspec;
|
||||
|
|
@ -297,7 +295,7 @@ fail_put:
|
|||
return error;
|
||||
}
|
||||
|
||||
void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev)
|
||||
void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
|
||||
{
|
||||
if (!list_empty(&dev->power.subsys_data->clock_list))
|
||||
pm_clk_destroy(dev);
|
||||
|
|
@ -326,4 +324,3 @@ void __init cpg_mstp_add_clk_domain(struct device_node *np)
|
|||
|
||||
of_genpd_add_provider_simple(np, pd);
|
||||
}
|
||||
#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
|
|
@ -26,6 +27,7 @@
|
|||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
|
||||
#define CPG_RCKCR 0x240
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
|
|
@ -50,6 +52,7 @@ enum clk_ids {
|
|||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
|
|
@ -63,8 +66,12 @@ enum r8a7795_clk_types {
|
|||
CLK_TYPE_GEN3_PLL3,
|
||||
CLK_TYPE_GEN3_PLL4,
|
||||
CLK_TYPE_GEN3_SD,
|
||||
CLK_TYPE_GEN3_R,
|
||||
};
|
||||
|
||||
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
|
||||
|
||||
static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
|
|
@ -102,10 +109,10 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
|
|||
DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),
|
||||
DEF_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),
|
||||
DEF_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),
|
||||
DEF_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),
|
||||
DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),
|
||||
DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),
|
||||
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),
|
||||
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),
|
||||
|
||||
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
|
@ -113,6 +120,11 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
|
|||
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
|
||||
DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
|
||||
DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
|
||||
|
|
@ -139,6 +151,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
|
|||
DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("rwdt0", 402, R8A7795_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
|
||||
|
|
@ -148,6 +161,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
|
|||
DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("pwm", 523, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1),
|
||||
|
|
@ -578,6 +592,18 @@ struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
|
|||
case CLK_TYPE_GEN3_SD:
|
||||
return cpg_sd_clk_register(core, base, __clk_get_name(parent));
|
||||
|
||||
case CLK_TYPE_GEN3_R:
|
||||
/* RINT is default. Only if EXTALR is populated, we switch to it */
|
||||
value = readl(base + CPG_RCKCR) & 0x3f;
|
||||
|
||||
if (clk_get_rate(clks[CLK_EXTALR])) {
|
||||
parent = clks[CLK_EXTALR];
|
||||
value |= BIT(15);
|
||||
}
|
||||
|
||||
writel(value, base + CPG_RCKCR);
|
||||
break;
|
||||
|
||||
default:
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/renesas.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
|
|
@ -253,7 +254,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
|
|||
{
|
||||
struct clk *clk = NULL, *parent;
|
||||
struct device *dev = priv->dev;
|
||||
unsigned int id = core->id;
|
||||
unsigned int id = core->id, div = core->div;
|
||||
const char *parent_name;
|
||||
|
||||
WARN_DEBUG(id >= priv->num_core_clks);
|
||||
|
|
@ -266,6 +267,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
|
|||
|
||||
case CLK_TYPE_FF:
|
||||
case CLK_TYPE_DIV6P1:
|
||||
case CLK_TYPE_DIV6_RO:
|
||||
WARN_DEBUG(core->parent >= priv->num_core_clks);
|
||||
parent = priv->clks[core->parent];
|
||||
if (IS_ERR(parent)) {
|
||||
|
|
@ -274,13 +276,18 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
|
|||
}
|
||||
|
||||
parent_name = __clk_get_name(parent);
|
||||
if (core->type == CLK_TYPE_FF) {
|
||||
clk = clk_register_fixed_factor(NULL, core->name,
|
||||
parent_name, 0,
|
||||
core->mult, core->div);
|
||||
} else {
|
||||
|
||||
if (core->type == CLK_TYPE_DIV6_RO)
|
||||
/* Multiply with the DIV6 register value */
|
||||
div *= (readl(priv->base + core->offset) & 0x3f) + 1;
|
||||
|
||||
if (core->type == CLK_TYPE_DIV6P1) {
|
||||
clk = cpg_div6_register(core->name, 1, &parent_name,
|
||||
priv->base + core->offset);
|
||||
} else {
|
||||
clk = clk_register_fixed_factor(NULL, core->name,
|
||||
parent_name, 0,
|
||||
core->mult, div);
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -375,8 +382,6 @@ fail:
|
|||
kfree(clock);
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
|
||||
struct cpg_mssr_clk_domain {
|
||||
struct generic_pm_domain genpd;
|
||||
struct device_node *np;
|
||||
|
|
@ -384,6 +389,8 @@ struct cpg_mssr_clk_domain {
|
|||
unsigned int core_pm_clks[0];
|
||||
};
|
||||
|
||||
static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
|
||||
|
||||
static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
|
||||
struct cpg_mssr_clk_domain *pd)
|
||||
{
|
||||
|
|
@ -407,17 +414,20 @@ static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
|
|||
}
|
||||
}
|
||||
|
||||
static int cpg_mssr_attach_dev(struct generic_pm_domain *genpd,
|
||||
struct device *dev)
|
||||
int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
|
||||
{
|
||||
struct cpg_mssr_clk_domain *pd =
|
||||
container_of(genpd, struct cpg_mssr_clk_domain, genpd);
|
||||
struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct of_phandle_args clkspec;
|
||||
struct clk *clk;
|
||||
int i = 0;
|
||||
int error;
|
||||
|
||||
if (!pd) {
|
||||
dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
|
||||
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
|
||||
&clkspec)) {
|
||||
if (cpg_mssr_is_pm_clk(&clkspec, pd))
|
||||
|
|
@ -457,8 +467,7 @@ fail_put:
|
|||
return error;
|
||||
}
|
||||
|
||||
static void cpg_mssr_detach_dev(struct generic_pm_domain *genpd,
|
||||
struct device *dev)
|
||||
void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
|
||||
{
|
||||
if (!list_empty(&dev->power.subsys_data->clock_list))
|
||||
pm_clk_destroy(dev);
|
||||
|
|
@ -487,19 +496,11 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
|
|||
pm_genpd_init(genpd, &simple_qos_governor, false);
|
||||
genpd->attach_dev = cpg_mssr_attach_dev;
|
||||
genpd->detach_dev = cpg_mssr_detach_dev;
|
||||
cpg_mssr_clk_domain = pd;
|
||||
|
||||
of_genpd_add_provider_simple(np, genpd);
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static inline int cpg_mssr_add_clk_domain(struct device *dev,
|
||||
const unsigned int *core_pm_clks,
|
||||
unsigned int num_core_pm_clks)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
|
||||
|
||||
|
||||
static const struct of_device_id cpg_mssr_match[] = {
|
||||
#ifdef CONFIG_ARCH_R8A7795
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@ enum clk_types {
|
|||
CLK_TYPE_IN, /* External Clock Input */
|
||||
CLK_TYPE_FF, /* Fixed Factor Clock */
|
||||
CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
|
||||
CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
|
||||
|
||||
/* Custom definitions start here */
|
||||
CLK_TYPE_CUSTOM,
|
||||
|
|
@ -53,9 +54,8 @@ enum clk_types {
|
|||
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
|
||||
#define DEF_DIV6P1(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
|
||||
#define DEF_SD(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
|
||||
|
||||
/*
|
||||
* Definitions of Module Clocks
|
||||
|
|
|
|||
|
|
@ -9,7 +9,8 @@ obj-$(CONFIG_MACH_DOVE) += dove/
|
|||
obj-y += fsl/
|
||||
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
|
||||
obj-$(CONFIG_ARCH_QCOM) += qcom/
|
||||
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
|
||||
obj-$(CONFIG_ARCH_RENESAS) += renesas/
|
||||
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
|
||||
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
|
||||
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
|
||||
obj-$(CONFIG_ARCH_TEGRA) += tegra/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
obj-$(CONFIG_ARCH_R8A7779) += rcar-sysc.o r8a7779-sysc.o
|
||||
obj-$(CONFIG_ARCH_R8A7790) += rcar-sysc.o r8a7790-sysc.o
|
||||
obj-$(CONFIG_ARCH_R8A7791) += rcar-sysc.o r8a7791-sysc.o
|
||||
# R-Car M2-N is identical to R-Car M2-W w.r.t. power domains.
|
||||
obj-$(CONFIG_ARCH_R8A7793) += rcar-sysc.o r8a7791-sysc.o
|
||||
obj-$(CONFIG_ARCH_R8A7794) += rcar-sysc.o r8a7794-sysc.o
|
||||
obj-$(CONFIG_ARCH_R8A7795) += rcar-sysc.o r8a7795-sysc.o
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Renesas R-Car H1 System Controller
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <dt-bindings/power/r8a7779-sysc.h>
|
||||
|
||||
#include "rcar-sysc.h"
|
||||
|
||||
static const struct rcar_sysc_area r8a7779_areas[] __initconst = {
|
||||
{ "always-on", 0, 0, R8A7779_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
|
||||
{ "arm1", 0x40, 1, R8A7779_PD_ARM1, R8A7779_PD_ALWAYS_ON,
|
||||
PD_CPU_CR },
|
||||
{ "arm2", 0x40, 2, R8A7779_PD_ARM2, R8A7779_PD_ALWAYS_ON,
|
||||
PD_CPU_CR },
|
||||
{ "arm3", 0x40, 3, R8A7779_PD_ARM3, R8A7779_PD_ALWAYS_ON,
|
||||
PD_CPU_CR },
|
||||
{ "sgx", 0xc0, 0, R8A7779_PD_SGX, R8A7779_PD_ALWAYS_ON },
|
||||
{ "vdp", 0x100, 0, R8A7779_PD_VDP, R8A7779_PD_ALWAYS_ON },
|
||||
{ "imp", 0x140, 0, R8A7779_PD_IMP, R8A7779_PD_ALWAYS_ON },
|
||||
};
|
||||
|
||||
const struct rcar_sysc_info r8a7779_sysc_info __initconst = {
|
||||
.areas = r8a7779_areas,
|
||||
.num_areas = ARRAY_SIZE(r8a7779_areas),
|
||||
};
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Renesas R-Car H2 System Controller
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <dt-bindings/power/r8a7790-sysc.h>
|
||||
|
||||
#include "rcar-sysc.h"
|
||||
|
||||
static const struct rcar_sysc_area r8a7790_areas[] __initconst = {
|
||||
{ "always-on", 0, 0, R8A7790_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
|
||||
{ "ca15-scu", 0x180, 0, R8A7790_PD_CA15_SCU, R8A7790_PD_ALWAYS_ON,
|
||||
PD_SCU },
|
||||
{ "ca15-cpu0", 0x40, 0, R8A7790_PD_CA15_CPU0, R8A7790_PD_CA15_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca15-cpu1", 0x40, 1, R8A7790_PD_CA15_CPU1, R8A7790_PD_CA15_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca15-cpu2", 0x40, 2, R8A7790_PD_CA15_CPU2, R8A7790_PD_CA15_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca15-cpu3", 0x40, 3, R8A7790_PD_CA15_CPU3, R8A7790_PD_CA15_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca7-scu", 0x100, 0, R8A7790_PD_CA7_SCU, R8A7790_PD_ALWAYS_ON,
|
||||
PD_SCU },
|
||||
{ "ca7-cpu0", 0x1c0, 0, R8A7790_PD_CA7_CPU0, R8A7790_PD_CA7_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca7-cpu1", 0x1c0, 1, R8A7790_PD_CA7_CPU1, R8A7790_PD_CA7_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca7-cpu2", 0x1c0, 2, R8A7790_PD_CA7_CPU2, R8A7790_PD_CA7_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca7-cpu3", 0x1c0, 3, R8A7790_PD_CA7_CPU3, R8A7790_PD_CA7_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "sh-4a", 0x80, 0, R8A7790_PD_SH_4A, R8A7790_PD_ALWAYS_ON },
|
||||
{ "rgx", 0xc0, 0, R8A7790_PD_RGX, R8A7790_PD_ALWAYS_ON },
|
||||
{ "imp", 0x140, 0, R8A7790_PD_IMP, R8A7790_PD_ALWAYS_ON },
|
||||
};
|
||||
|
||||
const struct rcar_sysc_info r8a7790_sysc_info __initconst = {
|
||||
.areas = r8a7790_areas,
|
||||
.num_areas = ARRAY_SIZE(r8a7790_areas),
|
||||
};
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Renesas R-Car M2-W/N System Controller
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <dt-bindings/power/r8a7791-sysc.h>
|
||||
|
||||
#include "rcar-sysc.h"
|
||||
|
||||
static const struct rcar_sysc_area r8a7791_areas[] __initconst = {
|
||||
{ "always-on", 0, 0, R8A7791_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
|
||||
{ "ca15-scu", 0x180, 0, R8A7791_PD_CA15_SCU, R8A7791_PD_ALWAYS_ON,
|
||||
PD_SCU },
|
||||
{ "ca15-cpu0", 0x40, 0, R8A7791_PD_CA15_CPU0, R8A7791_PD_CA15_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca15-cpu1", 0x40, 1, R8A7791_PD_CA15_CPU1, R8A7791_PD_CA15_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "sh-4a", 0x80, 0, R8A7791_PD_SH_4A, R8A7791_PD_ALWAYS_ON },
|
||||
{ "sgx", 0xc0, 0, R8A7791_PD_SGX, R8A7791_PD_ALWAYS_ON },
|
||||
};
|
||||
|
||||
const struct rcar_sysc_info r8a7791_sysc_info __initconst = {
|
||||
.areas = r8a7791_areas,
|
||||
.num_areas = ARRAY_SIZE(r8a7791_areas),
|
||||
};
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Renesas R-Car E2 System Controller
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <dt-bindings/power/r8a7794-sysc.h>
|
||||
|
||||
#include "rcar-sysc.h"
|
||||
|
||||
static const struct rcar_sysc_area r8a7794_areas[] __initconst = {
|
||||
{ "always-on", 0, 0, R8A7794_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
|
||||
{ "ca7-scu", 0x100, 0, R8A7794_PD_CA7_SCU, R8A7794_PD_ALWAYS_ON,
|
||||
PD_SCU },
|
||||
{ "ca7-cpu0", 0x1c0, 0, R8A7794_PD_CA7_CPU0, R8A7794_PD_CA7_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca7-cpu1", 0x1c0, 1, R8A7794_PD_CA7_CPU1, R8A7794_PD_CA7_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "sh-4a", 0x80, 0, R8A7794_PD_SH_4A, R8A7794_PD_ALWAYS_ON },
|
||||
{ "sgx", 0xc0, 0, R8A7794_PD_SGX, R8A7794_PD_ALWAYS_ON },
|
||||
};
|
||||
|
||||
const struct rcar_sysc_info r8a7794_sysc_info __initconst = {
|
||||
.areas = r8a7794_areas,
|
||||
.num_areas = ARRAY_SIZE(r8a7794_areas),
|
||||
};
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* Renesas R-Car H3 System Controller
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <dt-bindings/power/r8a7795-sysc.h>
|
||||
|
||||
#include "rcar-sysc.h"
|
||||
|
||||
static const struct rcar_sysc_area r8a7795_areas[] __initconst = {
|
||||
{ "always-on", 0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
|
||||
{ "ca57-scu", 0x1c0, 0, R8A7795_PD_CA57_SCU, R8A7795_PD_ALWAYS_ON,
|
||||
PD_SCU },
|
||||
{ "ca57-cpu0", 0x80, 0, R8A7795_PD_CA57_CPU0, R8A7795_PD_CA57_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca57-cpu1", 0x80, 1, R8A7795_PD_CA57_CPU1, R8A7795_PD_CA57_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca57-cpu2", 0x80, 2, R8A7795_PD_CA57_CPU2, R8A7795_PD_CA57_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca57-cpu3", 0x80, 3, R8A7795_PD_CA57_CPU3, R8A7795_PD_CA57_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca53-scu", 0x140, 0, R8A7795_PD_CA53_SCU, R8A7795_PD_ALWAYS_ON,
|
||||
PD_SCU },
|
||||
{ "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "ca53-cpu3", 0x200, 3, R8A7795_PD_CA53_CPU3, R8A7795_PD_CA53_SCU,
|
||||
PD_CPU_NOCR },
|
||||
{ "a3vp", 0x340, 0, R8A7795_PD_A3VP, R8A7795_PD_ALWAYS_ON },
|
||||
{ "cr7", 0x240, 0, R8A7795_PD_CR7, R8A7795_PD_ALWAYS_ON },
|
||||
{ "a3vc", 0x380, 0, R8A7795_PD_A3VC, R8A7795_PD_ALWAYS_ON },
|
||||
{ "a2vc0", 0x3c0, 0, R8A7795_PD_A2VC0, R8A7795_PD_A3VC },
|
||||
{ "a2vc1", 0x3c0, 1, R8A7795_PD_A2VC1, R8A7795_PD_A3VC },
|
||||
{ "3dg-a", 0x100, 0, R8A7795_PD_3DG_A, R8A7795_PD_ALWAYS_ON },
|
||||
{ "3dg-b", 0x100, 1, R8A7795_PD_3DG_B, R8A7795_PD_3DG_A },
|
||||
{ "3dg-c", 0x100, 2, R8A7795_PD_3DG_C, R8A7795_PD_3DG_B },
|
||||
{ "3dg-d", 0x100, 3, R8A7795_PD_3DG_D, R8A7795_PD_3DG_C },
|
||||
{ "3dg-e", 0x100, 4, R8A7795_PD_3DG_E, R8A7795_PD_3DG_D },
|
||||
{ "a3ir", 0x180, 0, R8A7795_PD_A3IR, R8A7795_PD_ALWAYS_ON },
|
||||
};
|
||||
|
||||
const struct rcar_sysc_info r8a7795_sysc_info __initconst = {
|
||||
.areas = r8a7795_areas,
|
||||
.num_areas = ARRAY_SIZE(r8a7795_areas),
|
||||
};
|
||||
|
|
@ -0,0 +1,401 @@
|
|||
/*
|
||||
* R-Car SYSC Power management support
|
||||
*
|
||||
* Copyright (C) 2014 Magnus Damm
|
||||
* Copyright (C) 2015-2016 Glider bvba
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk/renesas.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/soc/renesas/rcar-sysc.h>
|
||||
|
||||
#include "rcar-sysc.h"
|
||||
|
||||
/* SYSC Common */
|
||||
#define SYSCSR 0x00 /* SYSC Status Register */
|
||||
#define SYSCISR 0x04 /* Interrupt Status Register */
|
||||
#define SYSCISCR 0x08 /* Interrupt Status Clear Register */
|
||||
#define SYSCIER 0x0c /* Interrupt Enable Register */
|
||||
#define SYSCIMR 0x10 /* Interrupt Mask Register */
|
||||
|
||||
/* SYSC Status Register */
|
||||
#define SYSCSR_PONENB 1 /* Ready for power resume requests */
|
||||
#define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
|
||||
|
||||
/*
|
||||
* Power Control Register Offsets inside the register block for each domain
|
||||
* Note: The "CR" registers for ARM cores exist on H1 only
|
||||
* Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
|
||||
* Use PSCI on R-Car Gen3
|
||||
*/
|
||||
#define PWRSR_OFFS 0x00 /* Power Status Register */
|
||||
#define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
|
||||
#define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
|
||||
#define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
|
||||
#define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
|
||||
#define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
|
||||
|
||||
|
||||
#define SYSCSR_RETRIES 100
|
||||
#define SYSCSR_DELAY_US 1
|
||||
|
||||
#define PWRER_RETRIES 100
|
||||
#define PWRER_DELAY_US 1
|
||||
|
||||
#define SYSCISR_RETRIES 1000
|
||||
#define SYSCISR_DELAY_US 1
|
||||
|
||||
#define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */
|
||||
|
||||
static void __iomem *rcar_sysc_base;
|
||||
static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
|
||||
|
||||
static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
|
||||
{
|
||||
unsigned int sr_bit, reg_offs;
|
||||
int k;
|
||||
|
||||
if (on) {
|
||||
sr_bit = SYSCSR_PONENB;
|
||||
reg_offs = PWRONCR_OFFS;
|
||||
} else {
|
||||
sr_bit = SYSCSR_POFFENB;
|
||||
reg_offs = PWROFFCR_OFFS;
|
||||
}
|
||||
|
||||
/* Wait until SYSC is ready to accept a power request */
|
||||
for (k = 0; k < SYSCSR_RETRIES; k++) {
|
||||
if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
|
||||
break;
|
||||
udelay(SYSCSR_DELAY_US);
|
||||
}
|
||||
|
||||
if (k == SYSCSR_RETRIES)
|
||||
return -EAGAIN;
|
||||
|
||||
/* Submit power shutoff or power resume request */
|
||||
iowrite32(BIT(sysc_ch->chan_bit),
|
||||
rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
|
||||
{
|
||||
unsigned int isr_mask = BIT(sysc_ch->isr_bit);
|
||||
unsigned int chan_mask = BIT(sysc_ch->chan_bit);
|
||||
unsigned int status;
|
||||
unsigned long flags;
|
||||
int ret = 0;
|
||||
int k;
|
||||
|
||||
spin_lock_irqsave(&rcar_sysc_lock, flags);
|
||||
|
||||
iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
|
||||
|
||||
/* Submit power shutoff or resume request until it was accepted */
|
||||
for (k = 0; k < PWRER_RETRIES; k++) {
|
||||
ret = rcar_sysc_pwr_on_off(sysc_ch, on);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
status = ioread32(rcar_sysc_base +
|
||||
sysc_ch->chan_offs + PWRER_OFFS);
|
||||
if (!(status & chan_mask))
|
||||
break;
|
||||
|
||||
udelay(PWRER_DELAY_US);
|
||||
}
|
||||
|
||||
if (k == PWRER_RETRIES) {
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Wait until the power shutoff or resume request has completed * */
|
||||
for (k = 0; k < SYSCISR_RETRIES; k++) {
|
||||
if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
|
||||
break;
|
||||
udelay(SYSCISR_DELAY_US);
|
||||
}
|
||||
|
||||
if (k == SYSCISR_RETRIES)
|
||||
ret = -EIO;
|
||||
|
||||
iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
|
||||
|
||||
out:
|
||||
spin_unlock_irqrestore(&rcar_sysc_lock, flags);
|
||||
|
||||
pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
|
||||
sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch)
|
||||
{
|
||||
return rcar_sysc_power(sysc_ch, false);
|
||||
}
|
||||
|
||||
int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch)
|
||||
{
|
||||
return rcar_sysc_power(sysc_ch, true);
|
||||
}
|
||||
|
||||
static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
|
||||
{
|
||||
unsigned int st;
|
||||
|
||||
st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
|
||||
if (st & BIT(sysc_ch->chan_bit))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void __iomem *rcar_sysc_init(phys_addr_t base)
|
||||
{
|
||||
rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
|
||||
if (!rcar_sysc_base)
|
||||
panic("unable to ioremap R-Car SYSC hardware block\n");
|
||||
|
||||
return rcar_sysc_base;
|
||||
}
|
||||
|
||||
struct rcar_sysc_pd {
|
||||
struct generic_pm_domain genpd;
|
||||
struct rcar_sysc_ch ch;
|
||||
unsigned int flags;
|
||||
char name[0];
|
||||
};
|
||||
|
||||
static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
|
||||
{
|
||||
return container_of(d, struct rcar_sysc_pd, genpd);
|
||||
}
|
||||
|
||||
static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
|
||||
{
|
||||
struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
|
||||
|
||||
pr_debug("%s: %s\n", __func__, genpd->name);
|
||||
|
||||
if (pd->flags & PD_NO_CR) {
|
||||
pr_debug("%s: Cannot control %s\n", __func__, genpd->name);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (pd->flags & PD_BUSY) {
|
||||
pr_debug("%s: %s busy\n", __func__, genpd->name);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return rcar_sysc_power_down(&pd->ch);
|
||||
}
|
||||
|
||||
static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
|
||||
{
|
||||
struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
|
||||
|
||||
pr_debug("%s: %s\n", __func__, genpd->name);
|
||||
|
||||
if (pd->flags & PD_NO_CR) {
|
||||
pr_debug("%s: Cannot control %s\n", __func__, genpd->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return rcar_sysc_power_up(&pd->ch);
|
||||
}
|
||||
|
||||
static bool has_cpg_mstp;
|
||||
|
||||
static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
|
||||
{
|
||||
struct generic_pm_domain *genpd = &pd->genpd;
|
||||
const char *name = pd->genpd.name;
|
||||
struct dev_power_governor *gov = &simple_qos_governor;
|
||||
|
||||
if (pd->flags & PD_CPU) {
|
||||
/*
|
||||
* This domain contains a CPU core and therefore it should
|
||||
* only be turned off if the CPU is not in use.
|
||||
*/
|
||||
pr_debug("PM domain %s contains %s\n", name, "CPU");
|
||||
pd->flags |= PD_BUSY;
|
||||
gov = &pm_domain_always_on_gov;
|
||||
} else if (pd->flags & PD_SCU) {
|
||||
/*
|
||||
* This domain contains an SCU and cache-controller, and
|
||||
* therefore it should only be turned off if the CPU cores are
|
||||
* not in use.
|
||||
*/
|
||||
pr_debug("PM domain %s contains %s\n", name, "SCU");
|
||||
pd->flags |= PD_BUSY;
|
||||
gov = &pm_domain_always_on_gov;
|
||||
} else if (pd->flags & PD_NO_CR) {
|
||||
/*
|
||||
* This domain cannot be turned off.
|
||||
*/
|
||||
pd->flags |= PD_BUSY;
|
||||
gov = &pm_domain_always_on_gov;
|
||||
}
|
||||
|
||||
if (!(pd->flags & (PD_CPU | PD_SCU))) {
|
||||
/* Enable Clock Domain for I/O devices */
|
||||
genpd->flags = GENPD_FLAG_PM_CLK;
|
||||
if (has_cpg_mstp) {
|
||||
genpd->attach_dev = cpg_mstp_attach_dev;
|
||||
genpd->detach_dev = cpg_mstp_detach_dev;
|
||||
} else {
|
||||
genpd->attach_dev = cpg_mssr_attach_dev;
|
||||
genpd->detach_dev = cpg_mssr_detach_dev;
|
||||
}
|
||||
}
|
||||
|
||||
genpd->power_off = rcar_sysc_pd_power_off;
|
||||
genpd->power_on = rcar_sysc_pd_power_on;
|
||||
|
||||
if (pd->flags & (PD_CPU | PD_NO_CR)) {
|
||||
/* Skip CPUs (handled by SMP code) and areas without control */
|
||||
pr_debug("%s: Not touching %s\n", __func__, genpd->name);
|
||||
goto finalize;
|
||||
}
|
||||
|
||||
if (!rcar_sysc_power_is_off(&pd->ch)) {
|
||||
pr_debug("%s: %s is already powered\n", __func__, genpd->name);
|
||||
goto finalize;
|
||||
}
|
||||
|
||||
rcar_sysc_power_up(&pd->ch);
|
||||
|
||||
finalize:
|
||||
pm_genpd_init(genpd, gov, false);
|
||||
}
|
||||
|
||||
static const struct of_device_id rcar_sysc_matches[] = {
|
||||
#ifdef CONFIG_ARCH_R8A7779
|
||||
{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A7790
|
||||
{ .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A7791
|
||||
{ .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A7793
|
||||
/* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */
|
||||
{ .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A7794
|
||||
{ .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A7795
|
||||
{ .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
struct rcar_pm_domains {
|
||||
struct genpd_onecell_data onecell_data;
|
||||
struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
|
||||
};
|
||||
|
||||
static int __init rcar_sysc_pd_init(void)
|
||||
{
|
||||
const struct rcar_sysc_info *info;
|
||||
const struct of_device_id *match;
|
||||
struct rcar_pm_domains *domains;
|
||||
struct device_node *np;
|
||||
u32 syscier, syscimr;
|
||||
void __iomem *base;
|
||||
unsigned int i;
|
||||
int error;
|
||||
|
||||
np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
|
||||
info = match->data;
|
||||
|
||||
has_cpg_mstp = of_find_compatible_node(NULL, NULL,
|
||||
"renesas,cpg-mstp-clocks");
|
||||
|
||||
base = of_iomap(np, 0);
|
||||
if (!base) {
|
||||
pr_warn("%s: Cannot map regs\n", np->full_name);
|
||||
error = -ENOMEM;
|
||||
goto out_put;
|
||||
}
|
||||
|
||||
rcar_sysc_base = base;
|
||||
|
||||
domains = kzalloc(sizeof(*domains), GFP_KERNEL);
|
||||
if (!domains) {
|
||||
error = -ENOMEM;
|
||||
goto out_put;
|
||||
}
|
||||
|
||||
domains->onecell_data.domains = domains->domains;
|
||||
domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
|
||||
|
||||
for (i = 0, syscier = 0; i < info->num_areas; i++)
|
||||
syscier |= BIT(info->areas[i].isr_bit);
|
||||
|
||||
/*
|
||||
* Mask all interrupt sources to prevent the CPU from receiving them.
|
||||
* Make sure not to clear reserved bits that were set before.
|
||||
*/
|
||||
syscimr = ioread32(base + SYSCIMR);
|
||||
syscimr |= syscier;
|
||||
pr_debug("%s: syscimr = 0x%08x\n", np->full_name, syscimr);
|
||||
iowrite32(syscimr, base + SYSCIMR);
|
||||
|
||||
/*
|
||||
* SYSC needs all interrupt sources enabled to control power.
|
||||
*/
|
||||
pr_debug("%s: syscier = 0x%08x\n", np->full_name, syscier);
|
||||
iowrite32(syscier, base + SYSCIER);
|
||||
|
||||
for (i = 0; i < info->num_areas; i++) {
|
||||
const struct rcar_sysc_area *area = &info->areas[i];
|
||||
struct rcar_sysc_pd *pd;
|
||||
|
||||
pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
|
||||
if (!pd) {
|
||||
error = -ENOMEM;
|
||||
goto out_put;
|
||||
}
|
||||
|
||||
strcpy(pd->name, area->name);
|
||||
pd->genpd.name = pd->name;
|
||||
pd->ch.chan_offs = area->chan_offs;
|
||||
pd->ch.chan_bit = area->chan_bit;
|
||||
pd->ch.isr_bit = area->isr_bit;
|
||||
pd->flags = area->flags;
|
||||
|
||||
rcar_sysc_pd_setup(pd);
|
||||
if (area->parent >= 0)
|
||||
pm_genpd_add_subdomain(domains->domains[area->parent],
|
||||
&pd->genpd);
|
||||
|
||||
domains->domains[area->isr_bit] = &pd->genpd;
|
||||
}
|
||||
|
||||
of_genpd_add_provider_onecell(np, &domains->onecell_data);
|
||||
|
||||
out_put:
|
||||
of_node_put(np);
|
||||
return error;
|
||||
}
|
||||
early_initcall(rcar_sysc_pd_init);
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Renesas R-Car System Controller
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
#ifndef __SOC_RENESAS_RCAR_SYSC_H__
|
||||
#define __SOC_RENESAS_RCAR_SYSC_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
|
||||
/*
|
||||
* Power Domain flags
|
||||
*/
|
||||
#define PD_CPU BIT(0) /* Area contains main CPU core */
|
||||
#define PD_SCU BIT(1) /* Area contains SCU and L2 cache */
|
||||
#define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */
|
||||
|
||||
#define PD_BUSY BIT(3) /* Busy, for internal use only */
|
||||
|
||||
#define PD_CPU_CR PD_CPU /* CPU area has CR (R-Car H1) */
|
||||
#define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
|
||||
#define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
|
||||
|
||||
|
||||
/*
|
||||
* Description of a Power Area
|
||||
*/
|
||||
|
||||
struct rcar_sysc_area {
|
||||
const char *name;
|
||||
u16 chan_offs; /* Offset of PWRSR register for this area */
|
||||
u8 chan_bit; /* Bit in PWR* (except for PWRUP in PWRSR) */
|
||||
u8 isr_bit; /* Bit in SYSCI*R */
|
||||
int parent; /* -1 if none */
|
||||
unsigned int flags; /* See PD_* */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* SoC-specific Power Area Description
|
||||
*/
|
||||
|
||||
struct rcar_sysc_info {
|
||||
const struct rcar_sysc_area *areas;
|
||||
unsigned int num_areas;
|
||||
};
|
||||
|
||||
extern const struct rcar_sysc_info r8a7779_sysc_info;
|
||||
extern const struct rcar_sysc_info r8a7790_sysc_info;
|
||||
extern const struct rcar_sysc_info r8a7791_sysc_info;
|
||||
extern const struct rcar_sysc_info r8a7794_sysc_info;
|
||||
extern const struct rcar_sysc_info r8a7795_sysc_info;
|
||||
#endif /* __SOC_RENESAS_RCAR_SYSC_H__ */
|
||||
|
|
@ -66,6 +66,7 @@
|
|||
#define R8A7790_CLK_IIC2 0
|
||||
#define R8A7790_CLK_TPU0 4
|
||||
#define R8A7790_CLK_MMCIF1 5
|
||||
#define R8A7790_CLK_SCIF2 10
|
||||
#define R8A7790_CLK_SDHI3 11
|
||||
#define R8A7790_CLK_SDHI2 12
|
||||
#define R8A7790_CLK_SDHI1 13
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#define R8A7794_CLK_SDH 6
|
||||
#define R8A7794_CLK_SD0 7
|
||||
#define R8A7794_CLK_Z 8
|
||||
#define R8A7794_CLK_RCAN 9
|
||||
|
||||
/* MSTP0 */
|
||||
#define R8A7794_CLK_MSIOF0 0
|
||||
|
|
@ -56,6 +57,8 @@
|
|||
#define R8A7794_CLK_SDHI1 12
|
||||
#define R8A7794_CLK_SDHI0 14
|
||||
#define R8A7794_CLK_MMCIF0 15
|
||||
#define R8A7794_CLK_IIC0 18
|
||||
#define R8A7794_CLK_IIC1 23
|
||||
#define R8A7794_CLK_CMT1 29
|
||||
#define R8A7794_CLK_USBDMAC0 30
|
||||
#define R8A7794_CLK_USBDMAC1 31
|
||||
|
|
@ -95,6 +98,8 @@
|
|||
#define R8A7794_CLK_GPIO2 10
|
||||
#define R8A7794_CLK_GPIO1 11
|
||||
#define R8A7794_CLK_GPIO0 12
|
||||
#define R8A7794_CLK_RCAN1 15
|
||||
#define R8A7794_CLK_RCAN0 16
|
||||
#define R8A7794_CLK_QSPI_MOD 17
|
||||
#define R8A7794_CLK_I2C5 25
|
||||
#define R8A7794_CLK_I2C4 27
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A7779_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A7779_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A7779_PD_ARM1 1
|
||||
#define R8A7779_PD_ARM2 2
|
||||
#define R8A7779_PD_ARM3 3
|
||||
#define R8A7779_PD_SGX 20
|
||||
#define R8A7779_PD_VDP 21
|
||||
#define R8A7779_PD_IMP 24
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A7779_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7779_SYSC_H__ */
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A7790_PD_CA15_CPU0 0
|
||||
#define R8A7790_PD_CA15_CPU1 1
|
||||
#define R8A7790_PD_CA15_CPU2 2
|
||||
#define R8A7790_PD_CA15_CPU3 3
|
||||
#define R8A7790_PD_CA7_CPU0 5
|
||||
#define R8A7790_PD_CA7_CPU1 6
|
||||
#define R8A7790_PD_CA7_CPU2 7
|
||||
#define R8A7790_PD_CA7_CPU3 8
|
||||
#define R8A7790_PD_CA15_SCU 12
|
||||
#define R8A7790_PD_SH_4A 16
|
||||
#define R8A7790_PD_RGX 20
|
||||
#define R8A7790_PD_CA7_SCU 21
|
||||
#define R8A7790_PD_IMP 24
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A7790_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A7791_PD_CA15_CPU0 0
|
||||
#define R8A7791_PD_CA15_CPU1 1
|
||||
#define R8A7791_PD_CA15_SCU 12
|
||||
#define R8A7791_PD_SH_4A 16
|
||||
#define R8A7791_PD_SGX 20
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A7791_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*
|
||||
* Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains.
|
||||
*/
|
||||
|
||||
#define R8A7793_PD_CA15_CPU0 0
|
||||
#define R8A7793_PD_CA15_CPU1 1
|
||||
#define R8A7793_PD_CA15_SCU 12
|
||||
#define R8A7793_PD_SH_4A 16
|
||||
#define R8A7793_PD_SGX 20
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A7793_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A7794_PD_CA7_CPU0 5
|
||||
#define R8A7794_PD_CA7_CPU1 6
|
||||
#define R8A7794_PD_SH_4A 16
|
||||
#define R8A7794_PD_SGX 20
|
||||
#define R8A7794_PD_CA7_SCU 21
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A7794_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A7795_PD_CA57_CPU0 0
|
||||
#define R8A7795_PD_CA57_CPU1 1
|
||||
#define R8A7795_PD_CA57_CPU2 2
|
||||
#define R8A7795_PD_CA57_CPU3 3
|
||||
#define R8A7795_PD_CA53_CPU0 5
|
||||
#define R8A7795_PD_CA53_CPU1 6
|
||||
#define R8A7795_PD_CA53_CPU2 7
|
||||
#define R8A7795_PD_CA53_CPU3 8
|
||||
#define R8A7795_PD_A3VP 9
|
||||
#define R8A7795_PD_CA57_SCU 12
|
||||
#define R8A7795_PD_CR7 13
|
||||
#define R8A7795_PD_A3VC 14
|
||||
#define R8A7795_PD_3DG_A 17
|
||||
#define R8A7795_PD_3DG_B 18
|
||||
#define R8A7795_PD_3DG_C 19
|
||||
#define R8A7795_PD_3DG_D 20
|
||||
#define R8A7795_PD_CA53_SCU 21
|
||||
#define R8A7795_PD_3DG_E 22
|
||||
#define R8A7795_PD_A3IR 24
|
||||
#define R8A7795_PD_A2VC0 25
|
||||
#define R8A7795_PD_A2VC1 26
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A7795_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */
|
||||
|
|
@ -24,12 +24,20 @@ void r8a7778_clocks_init(u32 mode);
|
|||
void r8a7779_clocks_init(u32 mode);
|
||||
void rcar_gen2_clocks_init(u32 mode);
|
||||
|
||||
#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
|
||||
void cpg_mstp_add_clk_domain(struct device_node *np);
|
||||
int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev);
|
||||
void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev);
|
||||
#ifdef CONFIG_CLK_RENESAS_CPG_MSTP
|
||||
int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev);
|
||||
void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev);
|
||||
#else
|
||||
static inline void cpg_mstp_add_clk_domain(struct device_node *np) {}
|
||||
#define cpg_mstp_attach_dev NULL
|
||||
#define cpg_mstp_detach_dev NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CLK_RENESAS_CPG_MSSR
|
||||
int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev);
|
||||
void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev);
|
||||
#else
|
||||
#define cpg_mssr_attach_dev NULL
|
||||
#define cpg_mssr_detach_dev NULL
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
#ifndef PM_RCAR_H
|
||||
#define PM_RCAR_H
|
||||
#ifndef __LINUX_SOC_RENESAS_RCAR_SYSC_H__
|
||||
#define __LINUX_SOC_RENESAS_RCAR_SYSC_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct rcar_sysc_ch {
|
||||
u16 chan_offs;
|
||||
|
|
@ -9,7 +11,6 @@ struct rcar_sysc_ch {
|
|||
|
||||
int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch);
|
||||
int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch);
|
||||
bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch);
|
||||
void __iomem *rcar_sysc_init(phys_addr_t base);
|
||||
|
||||
#endif /* PM_RCAR_H */
|
||||
#endif /* __LINUX_SOC_RENESAS_RCAR_SYSC_H__ */
|
||||
Loading…
Reference in New Issue