drm/i915/fbc: Use PLANE_HAS_FENCE to determine if the plane is fenced
Rather than trusting the cached value of plane_state->vma->fence to imply whether the plane_state itself holds a reference on the framebuffer's fence, use the information provided in the plane_state->flags (PLANE_HAS_FENCE). Note that we still assume that FBC is entirely bounded by the plane_state active life span; it's not clear if that is a safe assumption. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180220134208.24988-4-chris@chris-wilson.co.uk
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@ -667,6 +667,7 @@ struct intel_fbc {
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*/
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*/
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struct intel_fbc_state_cache {
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struct intel_fbc_state_cache {
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struct i915_vma *vma;
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struct i915_vma *vma;
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unsigned long flags;
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struct {
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struct {
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unsigned int mode_flags;
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unsigned int mode_flags;
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@ -705,6 +706,7 @@ struct intel_fbc {
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*/
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*/
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struct intel_fbc_reg_params {
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struct intel_fbc_reg_params {
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struct i915_vma *vma;
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struct i915_vma *vma;
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unsigned long flags;
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struct {
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struct {
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enum pipe pipe;
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enum pipe pipe;
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@ -183,7 +183,7 @@ static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
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else
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else
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dpfc_ctl |= DPFC_CTL_LIMIT_1X;
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dpfc_ctl |= DPFC_CTL_LIMIT_1X;
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if (params->vma->fence) {
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if (params->flags & PLANE_HAS_FENCE) {
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dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
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dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
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I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
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I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
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} else {
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} else {
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@ -241,7 +241,7 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
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break;
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break;
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}
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}
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if (params->vma->fence) {
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if (params->flags & PLANE_HAS_FENCE) {
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dpfc_ctl |= DPFC_CTL_FENCE_EN;
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dpfc_ctl |= DPFC_CTL_FENCE_EN;
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if (IS_GEN5(dev_priv))
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if (IS_GEN5(dev_priv))
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dpfc_ctl |= params->vma->fence->id;
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dpfc_ctl |= params->vma->fence->id;
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@ -324,7 +324,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
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break;
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break;
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}
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}
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if (params->vma->fence) {
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if (params->flags & PLANE_HAS_FENCE) {
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dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
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dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
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I915_WRITE(SNB_DPFC_CTL_SA,
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I915_WRITE(SNB_DPFC_CTL_SA,
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SNB_CPU_FENCE_ENABLE |
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SNB_CPU_FENCE_ENABLE |
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@ -753,6 +753,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
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struct drm_framebuffer *fb = plane_state->base.fb;
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struct drm_framebuffer *fb = plane_state->base.fb;
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cache->vma = NULL;
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cache->vma = NULL;
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cache->flags = 0;
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cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
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cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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@ -778,6 +779,9 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
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cache->fb.stride = fb->pitches[0];
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cache->fb.stride = fb->pitches[0];
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cache->vma = plane_state->vma;
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cache->vma = plane_state->vma;
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cache->flags = plane_state->flags;
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if (WARN_ON(cache->flags & PLANE_HAS_FENCE && !cache->vma->fence))
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cache->flags &= ~PLANE_HAS_FENCE;
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}
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}
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static bool intel_fbc_can_activate(struct intel_crtc *crtc)
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static bool intel_fbc_can_activate(struct intel_crtc *crtc)
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@ -817,7 +821,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
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* so have no fence associated with it) due to aperture constaints
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* so have no fence associated with it) due to aperture constaints
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* at the time of pinning.
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* at the time of pinning.
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*/
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*/
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if (!cache->vma->fence) {
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if (!(cache->flags & PLANE_HAS_FENCE)) {
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fbc->no_fbc_reason = "framebuffer not tiled or fenced";
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fbc->no_fbc_reason = "framebuffer not tiled or fenced";
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return false;
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return false;
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}
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}
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@ -898,6 +902,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
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memset(params, 0, sizeof(*params));
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memset(params, 0, sizeof(*params));
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params->vma = cache->vma;
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params->vma = cache->vma;
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params->flags = cache->flags;
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params->crtc.pipe = crtc->pipe;
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params->crtc.pipe = crtc->pipe;
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params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
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params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
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