qed: Prevent link getting down in case of autoneg-off.
Newly added link modes are required to be added during setting link modes. If the new link mode is not available during qed_set_link, it may cause link getting down due to empty supported capability, being passed to MFW, after setting autoneg off/on with current/supported speed. Signed-off-by: Rahul Verma <Rahul.Verma@cavium.com> Signed-off-by: Ariel Elior <ariel.elior@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1305,6 +1305,7 @@ static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
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struct qed_hwfn *hwfn;
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struct qed_mcp_link_params *link_params;
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struct qed_ptt *ptt;
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u32 sup_caps;
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int rc;
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if (!cdev)
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@ -1331,25 +1332,50 @@ static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
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link_params->speed.autoneg = params->autoneg;
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if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
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link_params->speed.advertised_speeds = 0;
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if (params->adv_speeds & QED_LM_1000baseT_Full_BIT)
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sup_caps = QED_LM_1000baseT_Full_BIT |
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QED_LM_1000baseKX_Full_BIT |
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QED_LM_1000baseX_Full_BIT;
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if (params->adv_speeds & sup_caps)
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link_params->speed.advertised_speeds |=
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
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if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT)
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sup_caps = QED_LM_10000baseT_Full_BIT |
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QED_LM_10000baseKR_Full_BIT |
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QED_LM_10000baseKX4_Full_BIT |
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QED_LM_10000baseR_FEC_BIT |
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QED_LM_10000baseCR_Full_BIT |
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QED_LM_10000baseSR_Full_BIT |
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QED_LM_10000baseLR_Full_BIT |
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QED_LM_10000baseLRM_Full_BIT;
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if (params->adv_speeds & sup_caps)
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link_params->speed.advertised_speeds |=
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
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if (params->adv_speeds & QED_LM_20000baseKR2_Full_BIT)
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link_params->speed.advertised_speeds |=
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G;
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if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT)
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sup_caps = QED_LM_25000baseKR_Full_BIT |
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QED_LM_25000baseCR_Full_BIT |
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QED_LM_25000baseSR_Full_BIT;
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if (params->adv_speeds & sup_caps)
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link_params->speed.advertised_speeds |=
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
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if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT)
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sup_caps = QED_LM_40000baseLR4_Full_BIT |
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QED_LM_40000baseKR4_Full_BIT |
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QED_LM_40000baseCR4_Full_BIT |
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QED_LM_40000baseSR4_Full_BIT;
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if (params->adv_speeds & sup_caps)
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link_params->speed.advertised_speeds |=
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
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if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT)
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
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sup_caps = QED_LM_50000baseKR2_Full_BIT |
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QED_LM_50000baseCR2_Full_BIT |
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QED_LM_50000baseSR2_Full_BIT;
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if (params->adv_speeds & sup_caps)
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link_params->speed.advertised_speeds |=
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
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if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT)
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sup_caps = QED_LM_100000baseKR4_Full_BIT |
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QED_LM_100000baseSR4_Full_BIT |
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QED_LM_100000baseCR4_Full_BIT |
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QED_LM_100000baseLR4_ER4_Full_BIT;
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if (params->adv_speeds & sup_caps)
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link_params->speed.advertised_speeds |=
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NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G;
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}
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