drm/i915: enable ring freq scaling, RC6 and graphics turbo on Ivy Bridge v3
They use the same register interfaces, so we can simply enable the existing code on IVB. v2: - resolve conflict with ring freq scaling, we can enable it too v3: - resolve conflict again, this time on drm-intel-next Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
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@ -865,7 +865,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
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MEMSTAT_VID_SHIFT);
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MEMSTAT_VID_SHIFT);
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seq_printf(m, "Current P-state: %d\n",
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seq_printf(m, "Current P-state: %d\n",
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(rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
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(rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
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} else if (IS_GEN6(dev)) {
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} else if (IS_GEN6(dev) || IS_GEN7(dev)) {
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u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
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u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
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u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
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u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
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u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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@ -1131,7 +1131,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
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int ret;
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int ret;
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int gpu_freq, ia_freq;
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int gpu_freq, ia_freq;
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if (!IS_GEN6(dev)) {
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if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
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seq_printf(m, "unsupported on this chipset\n");
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seq_printf(m, "unsupported on this chipset\n");
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return 0;
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return 0;
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}
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}
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@ -7970,7 +7970,7 @@ void intel_modeset_init(struct drm_device *dev)
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intel_init_emon(dev);
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intel_init_emon(dev);
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}
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}
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if (IS_GEN6(dev)) {
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if (IS_GEN6(dev) || IS_GEN7(dev)) {
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gen6_enable_rps(dev_priv);
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gen6_enable_rps(dev_priv);
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gen6_update_ring_freq(dev_priv);
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gen6_update_ring_freq(dev_priv);
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}
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}
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@ -8014,7 +8014,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
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if (IS_IRONLAKE_M(dev))
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if (IS_IRONLAKE_M(dev))
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ironlake_disable_drps(dev);
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ironlake_disable_drps(dev);
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if (IS_GEN6(dev))
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if (IS_GEN6(dev) || IS_GEN7(dev))
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gen6_disable_rps(dev);
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gen6_disable_rps(dev);
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if (IS_IRONLAKE_M(dev))
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if (IS_IRONLAKE_M(dev))
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