Merge remote-tracking branches 'asoc/fix/arizona', 'asoc/fix/dpcm', 'asoc/fix/dwc', 'asoc/fix/fsl-ssi' and 'asoc/fix/hdmi-codec' into asoc-linus
This commit is contained in:
commit
1c681a1921
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@ -36,10 +36,10 @@ struct hdmi_codec_daifmt {
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HDMI_AC97,
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HDMI_SPDIF,
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} fmt;
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int bit_clk_inv:1;
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int frame_clk_inv:1;
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int bit_clk_master:1;
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int frame_clk_master:1;
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unsigned int bit_clk_inv:1;
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unsigned int frame_clk_inv:1;
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unsigned int bit_clk_master:1;
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unsigned int frame_clk_master:1;
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};
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/*
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@ -1551,7 +1551,7 @@ static int wm_adsp_load(struct wm_adsp *dsp)
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const struct wmfw_region *region;
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const struct wm_adsp_region *mem;
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const char *region_name;
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char *file, *text;
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char *file, *text = NULL;
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struct wm_adsp_buf *buf;
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unsigned int reg;
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int regions = 0;
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@ -1700,10 +1700,21 @@ static int wm_adsp_load(struct wm_adsp *dsp)
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regions, le32_to_cpu(region->len), offset,
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region_name);
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if ((pos + le32_to_cpu(region->len) + sizeof(*region)) >
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firmware->size) {
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adsp_err(dsp,
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"%s.%d: %s region len %d bytes exceeds file length %zu\n",
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file, regions, region_name,
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le32_to_cpu(region->len), firmware->size);
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ret = -EINVAL;
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goto out_fw;
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}
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if (text) {
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memcpy(text, region->data, le32_to_cpu(region->len));
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adsp_info(dsp, "%s: %s\n", file, text);
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kfree(text);
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text = NULL;
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}
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if (reg) {
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@ -1748,6 +1759,7 @@ out_fw:
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regmap_async_complete(regmap);
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wm_adsp_buf_free(&buf_list);
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release_firmware(firmware);
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kfree(text);
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out:
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kfree(file);
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@ -2233,6 +2245,17 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp)
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}
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if (reg) {
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if ((pos + le32_to_cpu(blk->len) + sizeof(*blk)) >
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firmware->size) {
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adsp_err(dsp,
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"%s.%d: %s region len %d bytes exceeds file length %zu\n",
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file, blocks, region_name,
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le32_to_cpu(blk->len),
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firmware->size);
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ret = -EINVAL;
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goto out_fw;
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}
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buf = wm_adsp_buf_alloc(blk->data,
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le32_to_cpu(blk->len),
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&buf_list);
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@ -681,22 +681,19 @@ static int dw_i2s_probe(struct platform_device *pdev)
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}
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if (!pdata) {
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ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
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if (ret == -EPROBE_DEFER) {
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dev_err(&pdev->dev,
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"failed to register PCM, deferring probe\n");
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return ret;
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} else if (ret) {
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dev_err(&pdev->dev,
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"Could not register DMA PCM: %d\n"
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"falling back to PIO mode\n", ret);
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if (irq >= 0) {
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ret = dw_pcm_register(pdev);
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if (ret) {
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dev_err(&pdev->dev,
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"Could not register PIO PCM: %d\n",
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dev->use_pio = true;
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} else {
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ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
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0);
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dev->use_pio = false;
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}
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if (ret) {
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dev_err(&pdev->dev, "could not register pcm: %d\n",
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ret);
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goto err_clk_disable;
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}
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goto err_clk_disable;
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}
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}
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@ -224,6 +224,12 @@ struct fsl_ssi_soc_data {
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* @dbg_stats: Debugging statistics
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*
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* @soc: SoC specific data
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*
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* @fifo_watermark: the FIFO watermark setting. Notifies DMA when
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* there are @fifo_watermark or fewer words in TX fifo or
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* @fifo_watermark or more empty words in RX fifo.
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* @dma_maxburst: max number of words to transfer in one go. So far,
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* this is always the same as fifo_watermark.
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*/
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struct fsl_ssi_private {
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struct regmap *regs;
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@ -263,6 +269,9 @@ struct fsl_ssi_private {
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const struct fsl_ssi_soc_data *soc;
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struct device *dev;
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u32 fifo_watermark;
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u32 dma_maxburst;
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};
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/*
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@ -1051,21 +1060,7 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev,
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regmap_write(regs, CCSR_SSI_SRCR, srcr);
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regmap_write(regs, CCSR_SSI_SCR, scr);
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/*
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* Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
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* use FIFO 1. We program the transmit water to signal a DMA transfer
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* if there are only two (or fewer) elements left in the FIFO. Two
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* elements equals one frame (left channel, right channel). This value,
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* however, depends on the depth of the transmit buffer.
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*
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* We set the watermark on the same level as the DMA burstsize. For
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* fiq it is probably better to use the biggest possible watermark
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* size.
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*/
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if (ssi_private->use_dma)
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wm = ssi_private->fifo_depth - 2;
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else
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wm = ssi_private->fifo_depth;
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wm = ssi_private->fifo_watermark;
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regmap_write(regs, CCSR_SSI_SFCSR,
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CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
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@ -1373,12 +1368,8 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev,
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dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
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PTR_ERR(ssi_private->baudclk));
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/*
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* We have burstsize be "fifo_depth - 2" to match the SSI
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* watermark setting in fsl_ssi_startup().
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*/
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ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
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ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
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ssi_private->dma_params_tx.maxburst = ssi_private->dma_maxburst;
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ssi_private->dma_params_rx.maxburst = ssi_private->dma_maxburst;
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ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
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ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
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@ -1543,6 +1534,47 @@ static int fsl_ssi_probe(struct platform_device *pdev)
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/* Older 8610 DTs didn't have the fifo-depth property */
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ssi_private->fifo_depth = 8;
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/*
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* Set the watermark for transmit FIFO 0 and receive FIFO 0. We don't
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* use FIFO 1 but set the watermark appropriately nontheless.
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* We program the transmit water to signal a DMA transfer
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* if there are N elements left in the FIFO. For chips with 15-deep
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* FIFOs, set watermark to 8. This allows the SSI to operate at a
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* high data rate without channel slipping. Behavior is unchanged
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* for the older chips with a fifo depth of only 8. A value of 4
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* might be appropriate for the older chips, but is left at
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* fifo_depth-2 until sombody has a chance to test.
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*
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* We set the watermark on the same level as the DMA burstsize. For
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* fiq it is probably better to use the biggest possible watermark
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* size.
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*/
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switch (ssi_private->fifo_depth) {
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case 15:
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/*
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* 2 samples is not enough when running at high data
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* rates (like 48kHz @ 16 bits/channel, 16 channels)
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* 8 seems to split things evenly and leave enough time
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* for the DMA to fill the FIFO before it's over/under
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* run.
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*/
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ssi_private->fifo_watermark = 8;
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ssi_private->dma_maxburst = 8;
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break;
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case 8:
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default:
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/*
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* maintain old behavior for older chips.
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* Keeping it the same because I don't have an older
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* board to test with.
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* I suspect this could be changed to be something to
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* leave some more space in the fifo.
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*/
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ssi_private->fifo_watermark = ssi_private->fifo_depth - 2;
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ssi_private->dma_maxburst = ssi_private->fifo_depth - 2;
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break;
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}
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dev_set_drvdata(&pdev->dev, ssi_private);
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if (ssi_private->soc->imx) {
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@ -2184,9 +2184,11 @@ static int dpcm_fe_dai_do_trigger(struct snd_pcm_substream *substream, int cmd)
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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fe->dpcm[stream].state = SND_SOC_DPCM_STATE_STOP;
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break;
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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fe->dpcm[stream].state = SND_SOC_DPCM_STATE_PAUSED;
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break;
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}
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out:
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