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Immutable branch between MFD and ASoC due for the v5.14 merge window 

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mergetag object 5258f7eed4
 type commit
 tag tb-mfd-gpio-regulator-v5.14
 tagger Lee Jones <lee.jones@linaro.org> 1621427664 +0100
 
 Immutable branch between MFD, GPIO and Regulator due for the v5.14 merge window
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mergetag object 4cfc965475
 type commit
 tag tb-mfd-regulator-rtc-v5.14
 tagger Lee Jones <lee.jones@linaro.org> 1622562292 +0100
 
 Immutable branch between MFD, Regulator and RTC due for the v5.14 merge window
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Merge tags 'tb-mfd-asoc-v5.14-1', 'tb-mfd-gpio-regulator-v5.14' and 'tb-mfd-regulator-rtc-v5.14' into ibs-for-mfd-merged

Immutable branch between MFD and ASoC due for the v5.14 merge window

Immutable branch between MFD, GPIO and Regulator due for the v5.14 merge window

Immutable branch between MFD, Regulator and RTC due for the v5.14 merge window
This commit is contained in:
Lee Jones 2021-06-02 10:48:48 +01:00
parent ef7570b675 5258f7eed4 4cfc965475
commit 1c4565f55b
18 changed files with 2520 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/mfd/mt6397.txt
View File

@ -21,6 +21,7 @@ Required properties:
compatible:
"mediatek,mt6323" for PMIC MT6323
"mediatek,mt6358" for PMIC MT6358
"mediatek,mt6359" for PMIC MT6359
"mediatek,mt6397" for PMIC MT6397
Optional subnodes:

385
Documentation/devicetree/bindings/regulator/mt6359-regulator.yaml Normal file
View File

@ -0,0 +1,385 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/mt6359-regulator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MT6359 Regulator from MediaTek Integrated
maintainers:
- Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
description: |
List of regulators provided by this controller. It is named
according to its regulator type, buck_<name> and ldo_<name>.
MT6359 regulators node should be sub node of the MT6397 MFD node.
patternProperties:
"^buck_v(s1|gpu11|modem|pu|core|s2|pa|proc2|proc1|core_sshub)$":
type: object
$ref: "regulator.yaml#"
properties:
regulator-name:
pattern: "^v(s1|gpu11|modem|pu|core|s2|pa|proc2|proc1|core_sshub)$"
unevaluatedProperties: false
"^ldo_v(ibr|rf12|usb|camio|efuse|xo22)$":
type: object
$ref: "regulator.yaml#"
properties:
regulator-name:
pattern: "^v(ibr|rf12|usb|camio|efuse|xo22)$"
unevaluatedProperties: false
"^ldo_v(rfck|emc|a12|a09|ufs|bbck)$":
type: object
$ref: "regulator.yaml#"
properties:
regulator-name:
pattern: "^v(rfck|emc|a12|a09|ufs|bbck)$"
unevaluatedProperties: false
"^ldo_vcn(18|13|33_1_bt|13_1_wifi|33_2_bt|33_2_wifi)$":
type: object
$ref: "regulator.yaml#"
properties:
regulator-name:
pattern: "^vcn(18|13|33_1_bt|13_1_wifi|33_2_bt|33_2_wifi)$"
unevaluatedProperties: false
"^ldo_vsram_(proc2|others|md|proc1|others_sshub)$":
type: object
$ref: "regulator.yaml#"
properties:
regulator-name:
pattern: "^vsram_(proc2|others|md|proc1|others_sshub)$"
unevaluatedProperties: false
"^ldo_v(fe|bif|io)28$":
type: object
$ref: "regulator.yaml#"
properties:
regulator-name:
pattern: "^v(fe|bif|io)28$"
unevaluatedProperties: false
"^ldo_v(aud|io|aux|rf|m)18$":
type: object
$ref: "regulator.yaml#"
properties:
regulator-name:
pattern: "^v(aud|io|aux|rf|m)18$"
unevaluatedProperties: false
"^ldo_vsim[12]$":
type: object
$ref: "regulator.yaml#"
properties:
regulator-name:
pattern: "^vsim[12]$"
required:
- regulator-name
unevaluatedProperties: false
additionalProperties: false
examples:
- |
pmic {
regulators {
mt6359_vs1_buck_reg: buck_vs1 {
regulator-name = "vs1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <2200000>;
regulator-enable-ramp-delay = <0>;
regulator-always-on;
};
mt6359_vgpu11_buck_reg: buck_vgpu11 {
regulator-name = "vgpu11";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-ramp-delay = <5000>;
regulator-enable-ramp-delay = <200>;
regulator-allowed-modes = <0 1 2>;
};
mt6359_vmodem_buck_reg: buck_vmodem {
regulator-name = "vmodem";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1100000>;
regulator-ramp-delay = <10760>;
regulator-enable-ramp-delay = <200>;
};
mt6359_vpu_buck_reg: buck_vpu {
regulator-name = "vpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-ramp-delay = <5000>;
regulator-enable-ramp-delay = <200>;
regulator-allowed-modes = <0 1 2>;
};
mt6359_vcore_buck_reg: buck_vcore {
regulator-name = "vcore";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <5000>;
regulator-enable-ramp-delay = <200>;
regulator-allowed-modes = <0 1 2>;
};
mt6359_vs2_buck_reg: buck_vs2 {
regulator-name = "vs2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1600000>;
regulator-enable-ramp-delay = <0>;
regulator-always-on;
};
mt6359_vpa_buck_reg: buck_vpa {
regulator-name = "vpa";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3650000>;
regulator-enable-ramp-delay = <300>;
};
mt6359_vproc2_buck_reg: buck_vproc2 {
regulator-name = "vproc2";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-ramp-delay = <7500>;
regulator-enable-ramp-delay = <200>;
regulator-allowed-modes = <0 1 2>;
};
mt6359_vproc1_buck_reg: buck_vproc1 {
regulator-name = "vproc1";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-ramp-delay = <7500>;
regulator-enable-ramp-delay = <200>;
regulator-allowed-modes = <0 1 2>;
};
mt6359_vcore_sshub_buck_reg: buck_vcore_sshub {
regulator-name = "vcore_sshub";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
};
mt6359_vgpu11_sshub_buck_reg: buck_vgpu11_sshub {
regulator-name = "vgpu11_sshub";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
};
mt6359_vaud18_ldo_reg: ldo_vaud18 {
regulator-name = "vaud18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <240>;
};
mt6359_vsim1_ldo_reg: ldo_vsim1 {
regulator-name = "vsim1";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3100000>;
};
mt6359_vibr_ldo_reg: ldo_vibr {
regulator-name = "vibr";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
};
mt6359_vrf12_ldo_reg: ldo_vrf12 {
regulator-name = "vrf12";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
};
mt6359_vusb_ldo_reg: ldo_vusb {
regulator-name = "vusb";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <960>;
regulator-always-on;
};
mt6359_vsram_proc2_ldo_reg: ldo_vsram_proc2 {
regulator-name = "vsram_proc2";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <7500>;
regulator-enable-ramp-delay = <240>;
regulator-always-on;
};
mt6359_vio18_ldo_reg: ldo_vio18 {
regulator-name = "vio18";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
regulator-enable-ramp-delay = <960>;
regulator-always-on;
};
mt6359_vcamio_ldo_reg: ldo_vcamio {
regulator-name = "vcamio";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
};
mt6359_vcn18_ldo_reg: ldo_vcn18 {
regulator-name = "vcn18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <240>;
};
mt6359_vfe28_ldo_reg: ldo_vfe28 {
regulator-name = "vfe28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <120>;
};
mt6359_vcn13_ldo_reg: ldo_vcn13 {
regulator-name = "vcn13";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1300000>;
};
mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt {
regulator-name = "vcn33_1_bt";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3500000>;
};
mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi {
regulator-name = "vcn33_1_wifi";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3500000>;
};
mt6359_vaux18_ldo_reg: ldo_vaux18 {
regulator-name = "vaux18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <240>;
regulator-always-on;
};
mt6359_vsram_others_ldo_reg: ldo_vsram_others {
regulator-name = "vsram_others";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <5000>;
regulator-enable-ramp-delay = <240>;
};
mt6359_vefuse_ldo_reg: ldo_vefuse {
regulator-name = "vefuse";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <2000000>;
};
mt6359_vxo22_ldo_reg: ldo_vxo22 {
regulator-name = "vxo22";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2200000>;
regulator-always-on;
};
mt6359_vrfck_ldo_reg: ldo_vrfck {
regulator-name = "vrfck";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1700000>;
};
mt6359_vrfck_1_ldo_reg: ldo_vrfck_1 {
regulator-name = "vrfck";
regulator-min-microvolt = <1240000>;
regulator-max-microvolt = <1600000>;
};
mt6359_vbif28_ldo_reg: ldo_vbif28 {
regulator-name = "vbif28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <240>;
};
mt6359_vio28_ldo_reg: ldo_vio28 {
regulator-name = "vio28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
mt6359_vemc_ldo_reg: ldo_vemc {
regulator-name = "vemc";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <3300000>;
};
mt6359_vemc_1_ldo_reg: ldo_vemc_1 {
regulator-name = "vemc";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
};
mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt {
regulator-name = "vcn33_2_bt";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3500000>;
};
mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi {
regulator-name = "vcn33_2_wifi";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3500000>;
};
mt6359_va12_ldo_reg: ldo_va12 {
regulator-name = "va12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
};
mt6359_va09_ldo_reg: ldo_va09 {
regulator-name = "va09";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1200000>;
};
mt6359_vrf18_ldo_reg: ldo_vrf18 {
regulator-name = "vrf18";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1810000>;
};
mt6359_vsram_md_ldo_reg: ldo_vsram_md {
regulator-name = "vsram_md";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <10760>;
regulator-enable-ramp-delay = <240>;
};
mt6359_vufs_ldo_reg: ldo_vufs {
regulator-name = "vufs";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
};
mt6359_vm18_ldo_reg: ldo_vm18 {
regulator-name = "vm18";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
regulator-always-on;
};
mt6359_vbbck_ldo_reg: ldo_vbbck {
regulator-name = "vbbck";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1200000>;
};
mt6359_vsram_proc1_ldo_reg: ldo_vsram_proc1 {
regulator-name = "vsram_proc1";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <7500>;
regulator-enable-ramp-delay = <240>;
regulator-always-on;
};
mt6359_vsim2_ldo_reg: ldo_vsim2 {
regulator-name = "vsim2";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3100000>;
};
mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub {
regulator-name = "vsram_others_sshub";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
};
};
};
...

6
drivers/gpio/gpio-lp87565.c
View File

@ -123,14 +123,14 @@ static int lp87565_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
return regmap_update_bits(gpio->map,
LP87565_REG_GPIO_CONFIG,
BIT(offset +
__ffs(LP87565_GOIO1_OD)),
__ffs(LP87565_GPIO1_OD)),
BIT(offset +
__ffs(LP87565_GOIO1_OD)));
__ffs(LP87565_GPIO1_OD)));
case PIN_CONFIG_DRIVE_PUSH_PULL:
return regmap_update_bits(gpio->map,
LP87565_REG_GPIO_CONFIG,
BIT(offset +
__ffs(LP87565_GOIO1_OD)), 0);
__ffs(LP87565_GPIO1_OD)), 0);
default:
return -ENOTSUPP;
}

89
drivers/mfd/mt6358-irq.c
View File

@ -5,6 +5,8 @@
#include <linux/interrupt.h>
#include <linux/mfd/mt6358/core.h>
#include <linux/mfd/mt6358/registers.h>
#include <linux/mfd/mt6359/core.h>
#include <linux/mfd/mt6359/registers.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/module.h>
#include <linux/of.h>
@ -13,7 +15,9 @@
#include <linux/platform_device.h>
#include <linux/regmap.h>
static struct irq_top_t mt6358_ints[] = {
#define MTK_PMIC_REG_WIDTH 16
static const struct irq_top_t mt6358_ints[] = {
MT6358_TOP_GEN(BUCK),
MT6358_TOP_GEN(LDO),
MT6358_TOP_GEN(PSC),
@ -24,6 +28,31 @@ static struct irq_top_t mt6358_ints[] = {
MT6358_TOP_GEN(MISC),
};
static const struct irq_top_t mt6359_ints[] = {
MT6359_TOP_GEN(BUCK),
MT6359_TOP_GEN(LDO),
MT6359_TOP_GEN(PSC),
MT6359_TOP_GEN(SCK),
MT6359_TOP_GEN(BM),
MT6359_TOP_GEN(HK),
MT6359_TOP_GEN(AUD),
MT6359_TOP_GEN(MISC),
};
static struct pmic_irq_data mt6358_irqd = {
.num_top = ARRAY_SIZE(mt6358_ints),
.num_pmic_irqs = MT6358_IRQ_NR,
.top_int_status_reg = MT6358_TOP_INT_STATUS0,
.pmic_ints = mt6358_ints,
};
static struct pmic_irq_data mt6359_irqd = {
.num_top = ARRAY_SIZE(mt6359_ints),
.num_pmic_irqs = MT6359_IRQ_NR,
.top_int_status_reg = MT6359_TOP_INT_STATUS0,
.pmic_ints = mt6359_ints,
};
static void pmic_irq_enable(struct irq_data *data)
{
unsigned int hwirq = irqd_to_hwirq(data);
@ -62,15 +91,15 @@ static void pmic_irq_sync_unlock(struct irq_data *data)
/* Find out the IRQ group */
top_gp = 0;
while ((top_gp + 1) < irqd->num_top &&
i >= mt6358_ints[top_gp + 1].hwirq_base)
i >= irqd->pmic_ints[top_gp + 1].hwirq_base)
top_gp++;
/* Find the IRQ registers */
gp_offset = i - mt6358_ints[top_gp].hwirq_base;
int_regs = gp_offset / MT6358_REG_WIDTH;
shift = gp_offset % MT6358_REG_WIDTH;
en_reg = mt6358_ints[top_gp].en_reg +
(mt6358_ints[top_gp].en_reg_shift * int_regs);
gp_offset = i - irqd->pmic_ints[top_gp].hwirq_base;
int_regs = gp_offset / MTK_PMIC_REG_WIDTH;
shift = gp_offset % MTK_PMIC_REG_WIDTH;
en_reg = irqd->pmic_ints[top_gp].en_reg +
(irqd->pmic_ints[top_gp].en_reg_shift * int_regs);
regmap_update_bits(chip->regmap, en_reg, BIT(shift),
irqd->enable_hwirq[i] << shift);
@ -95,10 +124,11 @@ static void mt6358_irq_sp_handler(struct mt6397_chip *chip,
unsigned int irq_status, sta_reg, status;
unsigned int hwirq, virq;
int i, j, ret;
struct pmic_irq_data *irqd = chip->irq_data;
for (i = 0; i < mt6358_ints[top_gp].num_int_regs; i++) {
sta_reg = mt6358_ints[top_gp].sta_reg +
mt6358_ints[top_gp].sta_reg_shift * i;
for (i = 0; i < irqd->pmic_ints[top_gp].num_int_regs; i++) {
sta_reg = irqd->pmic_ints[top_gp].sta_reg +
irqd->pmic_ints[top_gp].sta_reg_shift * i;
ret = regmap_read(chip->regmap, sta_reg, &irq_status);
if (ret) {
@ -114,8 +144,8 @@ static void mt6358_irq_sp_handler(struct mt6397_chip *chip,
do {
j = __ffs(status);
hwirq = mt6358_ints[top_gp].hwirq_base +
MT6358_REG_WIDTH * i + j;
hwirq = irqd->pmic_ints[top_gp].hwirq_base +
MTK_PMIC_REG_WIDTH * i + j;
virq = irq_find_mapping(chip->irq_domain, hwirq);
if (virq)
@ -131,12 +161,12 @@ static void mt6358_irq_sp_handler(struct mt6397_chip *chip,
static irqreturn_t mt6358_irq_handler(int irq, void *data)
{
struct mt6397_chip *chip = data;
struct pmic_irq_data *mt6358_irq_data = chip->irq_data;
struct pmic_irq_data *irqd = chip->irq_data;
unsigned int bit, i, top_irq_status = 0;
int ret;
ret = regmap_read(chip->regmap,
mt6358_irq_data->top_int_status_reg,
irqd->top_int_status_reg,
&top_irq_status);
if (ret) {
dev_err(chip->dev,
@ -144,8 +174,8 @@ static irqreturn_t mt6358_irq_handler(int irq, void *data)
return IRQ_NONE;
}
for (i = 0; i < mt6358_irq_data->num_top; i++) {
bit = BIT(mt6358_ints[i].top_offset);
for (i = 0; i < irqd->num_top; i++) {
bit = BIT(irqd->pmic_ints[i].top_offset);
if (top_irq_status & bit) {
mt6358_irq_sp_handler(chip, i);
top_irq_status &= ~bit;
@ -180,17 +210,22 @@ int mt6358_irq_init(struct mt6397_chip *chip)
int i, j, ret;
struct pmic_irq_data *irqd;
irqd = devm_kzalloc(chip->dev, sizeof(*irqd), GFP_KERNEL);
if (!irqd)
return -ENOMEM;
switch (chip->chip_id) {
case MT6358_CHIP_ID:
chip->irq_data = &mt6358_irqd;
break;
chip->irq_data = irqd;
case MT6359_CHIP_ID:
chip->irq_data = &mt6359_irqd;
break;
default:
dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
return -ENODEV;
}
mutex_init(&chip->irqlock);
irqd->top_int_status_reg = MT6358_TOP_INT_STATUS0;
irqd->num_pmic_irqs = MT6358_IRQ_NR;
irqd->num_top = ARRAY_SIZE(mt6358_ints);
irqd = chip->irq_data;
irqd->enable_hwirq = devm_kcalloc(chip->dev,
irqd->num_pmic_irqs,
sizeof(*irqd->enable_hwirq),
@ -207,10 +242,10 @@ int mt6358_irq_init(struct mt6397_chip *chip)
/* Disable all interrupts for initializing */
for (i = 0; i < irqd->num_top; i++) {
for (j = 0; j < mt6358_ints[i].num_int_regs; j++)
for (j = 0; j < irqd->pmic_ints[i].num_int_regs; j++)
regmap_write(chip->regmap,
mt6358_ints[i].en_reg +
mt6358_ints[i].en_reg_shift * j, 0);
irqd->pmic_ints[i].en_reg +
irqd->pmic_ints[i].en_reg_shift * j, 0);
}
chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,

24
drivers/mfd/mt6397-core.c
View File

@ -13,9 +13,11 @@
#include <linux/mfd/core.h>
#include <linux/mfd/mt6323/core.h>
#include <linux/mfd/mt6358/core.h>
#include <linux/mfd/mt6359/core.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6323/registers.h>
#include <linux/mfd/mt6358/registers.h>
#include <linux/mfd/mt6359/registers.h>
#include <linux/mfd/mt6397/registers.h>
#define MT6323_RTC_BASE 0x8000
@ -99,6 +101,17 @@ static const struct mfd_cell mt6358_devs[] = {
},
};
static const struct mfd_cell mt6359_devs[] = {
{ .name = "mt6359-regulator", },
{
.name = "mt6359-rtc",
.num_resources = ARRAY_SIZE(mt6358_rtc_resources),
.resources = mt6358_rtc_resources,
.of_compatible = "mediatek,mt6358-rtc",
},
{ .name = "mt6359-sound", },
};
static const struct mfd_cell mt6397_devs[] = {
{
.name = "mt6397-rtc",
@ -149,6 +162,14 @@ static const struct chip_data mt6358_core = {
.irq_init = mt6358_irq_init,
};
static const struct chip_data mt6359_core = {
.cid_addr = MT6359_SWCID,
.cid_shift = 8,
.cells = mt6359_devs,
.cell_size = ARRAY_SIZE(mt6359_devs),
.irq_init = mt6358_irq_init,
};
static const struct chip_data mt6397_core = {
.cid_addr = MT6397_CID,
.cid_shift = 0,
@ -218,6 +239,9 @@ static const struct of_device_id mt6397_of_match[] = {
}, {
.compatible = "mediatek,mt6358",
.data = &mt6358_core,
}, {
.compatible = "mediatek,mt6359",
.data = &mt6359_core,
}, {
.compatible = "mediatek,mt6397",
.data = &mt6397_core,

9
drivers/regulator/Kconfig
View File

@ -779,6 +779,15 @@ config REGULATOR_MT6358
This driver supports the control of different power rails of device
through regulator interface.
config REGULATOR_MT6359
tristate "MediaTek MT6359 PMIC"
depends on MFD_MT6397
help
Say y here to select this option to enable the power regulator of
MediaTek MT6359 PMIC.
This driver supports the control of different power rails of device
through regulator interface.
config REGULATOR_MT6360
tristate "MT6360 SubPMIC Regulator"
depends on MFD_MT6360

1
drivers/regulator/Makefile
View File

@ -94,6 +94,7 @@ obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o
obj-$(CONFIG_REGULATOR_MT6315) += mt6315-regulator.o
obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o
obj-$(CONFIG_REGULATOR_MT6358) += mt6358-regulator.o
obj-$(CONFIG_REGULATOR_MT6359) += mt6359-regulator.o
obj-$(CONFIG_REGULATOR_MT6360) += mt6360-regulator.o
obj-$(CONFIG_REGULATOR_MT6380) += mt6380-regulator.o
obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o

11
drivers/regulator/lp87565-regulator.c
View File

@ -11,6 +11,17 @@
#include <linux/mfd/lp87565.h>
enum LP87565_regulator_id {
/* BUCK's */
LP87565_BUCK_0,
LP87565_BUCK_1,
LP87565_BUCK_2,
LP87565_BUCK_3,
LP87565_BUCK_10,
LP87565_BUCK_23,
LP87565_BUCK_3210,
};
#define LP87565_REGULATOR(_name, _id, _of, _ops, _n, _vr, _vm, \
_er, _em, _ev, _delay, _lr, _cr) \
[_id] = { \

1036
drivers/regulator/mt6359-regulator.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/rtc/rtc-mt6397.c
View File

@ -75,7 +75,7 @@ static int __mtk_rtc_read_time(struct mt6397_rtc *rtc,
tm->tm_min = data[RTC_OFFSET_MIN];
tm->tm_hour = data[RTC_OFFSET_HOUR];
tm->tm_mday = data[RTC_OFFSET_DOM];
tm->tm_mon = data[RTC_OFFSET_MTH];
tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_TC_MTH_MASK;
tm->tm_year = data[RTC_OFFSET_YEAR];
ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec);

35
include/linux/mfd/lp87565.h
View File

@ -222,31 +222,20 @@ enum lp87565_device_type {
#define LP87565_GPIO2_SEL BIT(1)
#define LP87565_GPIO1_SEL BIT(0)
#define LP87565_GOIO3_OD BIT(6)
#define LP87565_GOIO2_OD BIT(5)
#define LP87565_GOIO1_OD BIT(4)
#define LP87565_GOIO3_DIR BIT(2)
#define LP87565_GOIO2_DIR BIT(1)
#define LP87565_GOIO1_DIR BIT(0)
#define LP87565_GPIO3_OD BIT(6)
#define LP87565_GPIO2_OD BIT(5)
#define LP87565_GPIO1_OD BIT(4)
#define LP87565_GPIO3_DIR BIT(2)
#define LP87565_GPIO2_DIR BIT(1)
#define LP87565_GPIO1_DIR BIT(0)
#define LP87565_GOIO3_IN BIT(2)
#define LP87565_GOIO2_IN BIT(1)
#define LP87565_GOIO1_IN BIT(0)
#define LP87565_GPIO3_IN BIT(2)
#define LP87565_GPIO2_IN BIT(1)
#define LP87565_GPIO1_IN BIT(0)
#define LP87565_GOIO3_OUT BIT(2)
#define LP87565_GOIO2_OUT BIT(1)
#define LP87565_GOIO1_OUT BIT(0)
enum LP87565_regulator_id {
/* BUCK's */
LP87565_BUCK_0,
LP87565_BUCK_1,
LP87565_BUCK_2,
LP87565_BUCK_3,
LP87565_BUCK_10,
LP87565_BUCK_23,
LP87565_BUCK_3210,
};
#define LP87565_GPIO3_OUT BIT(2)
#define LP87565_GPIO2_OUT BIT(1)
#define LP87565_GPIO1_OUT BIT(0)
/**
* struct LP87565 - state holder for the LP87565 driver

8
include/linux/mfd/mt6358/core.h
View File

@ -6,12 +6,9 @@
#ifndef __MFD_MT6358_CORE_H__
#define __MFD_MT6358_CORE_H__
#define MT6358_REG_WIDTH 16
struct irq_top_t {
int hwirq_base;
unsigned int num_int_regs;
unsigned int num_int_bits;
unsigned int en_reg;
unsigned int en_reg_shift;
unsigned int sta_reg;
@ -25,6 +22,7 @@ struct pmic_irq_data {
unsigned short top_int_status_reg;
bool *enable_hwirq;
bool *cache_hwirq;
const struct irq_top_t *pmic_ints;
};
enum mt6358_irq_top_status_shift {
@ -146,8 +144,8 @@ enum mt6358_irq_numbers {
{ \
.hwirq_base = MT6358_IRQ_##sp##_BASE, \
.num_int_regs = \
((MT6358_IRQ_##sp##_BITS - 1) / MT6358_REG_WIDTH) + 1, \
.num_int_bits = MT6358_IRQ_##sp##_BITS, \
((MT6358_IRQ_##sp##_BITS - 1) / \
MTK_PMIC_REG_WIDTH) + 1, \
.en_reg = MT6358_##sp##_TOP_INT_CON0, \
.en_reg_shift = 0x6, \
.sta_reg = MT6358_##sp##_TOP_INT_STATUS0, \

133
include/linux/mfd/mt6359/core.h Normal file
View File

@ -0,0 +1,133 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#ifndef __MFD_MT6359_CORE_H__
#define __MFD_MT6359_CORE_H__
enum mt6359_irq_top_status_shift {
MT6359_BUCK_TOP = 0,
MT6359_LDO_TOP,
MT6359_PSC_TOP,
MT6359_SCK_TOP,
MT6359_BM_TOP,
MT6359_HK_TOP,
MT6359_AUD_TOP = 7,
MT6359_MISC_TOP,
};
enum mt6359_irq_numbers {
MT6359_IRQ_VCORE_OC = 1,
MT6359_IRQ_VGPU11_OC,
MT6359_IRQ_VGPU12_OC,
MT6359_IRQ_VMODEM_OC,
MT6359_IRQ_VPROC1_OC,
MT6359_IRQ_VPROC2_OC,
MT6359_IRQ_VS1_OC,
MT6359_IRQ_VS2_OC,
MT6359_IRQ_VPA_OC = 9,
MT6359_IRQ_VFE28_OC = 16,
MT6359_IRQ_VXO22_OC,
MT6359_IRQ_VRF18_OC,
MT6359_IRQ_VRF12_OC,
MT6359_IRQ_VEFUSE_OC,
MT6359_IRQ_VCN33_1_OC,
MT6359_IRQ_VCN33_2_OC,
MT6359_IRQ_VCN13_OC,
MT6359_IRQ_VCN18_OC,
MT6359_IRQ_VA09_OC,
MT6359_IRQ_VCAMIO_OC,
MT6359_IRQ_VA12_OC,
MT6359_IRQ_VAUX18_OC,
MT6359_IRQ_VAUD18_OC,
MT6359_IRQ_VIO18_OC,
MT6359_IRQ_VSRAM_PROC1_OC,
MT6359_IRQ_VSRAM_PROC2_OC,
MT6359_IRQ_VSRAM_OTHERS_OC,
MT6359_IRQ_VSRAM_MD_OC,
MT6359_IRQ_VEMC_OC,
MT6359_IRQ_VSIM1_OC,
MT6359_IRQ_VSIM2_OC,
MT6359_IRQ_VUSB_OC,
MT6359_IRQ_VRFCK_OC,
MT6359_IRQ_VBBCK_OC,
MT6359_IRQ_VBIF28_OC,
MT6359_IRQ_VIBR_OC,
MT6359_IRQ_VIO28_OC,
MT6359_IRQ_VM18_OC,
MT6359_IRQ_VUFS_OC = 45,
MT6359_IRQ_PWRKEY = 48,
MT6359_IRQ_HOMEKEY,
MT6359_IRQ_PWRKEY_R,
MT6359_IRQ_HOMEKEY_R,
MT6359_IRQ_NI_LBAT_INT,
MT6359_IRQ_CHRDET_EDGE = 53,
MT6359_IRQ_RTC = 64,
MT6359_IRQ_FG_BAT_H = 80,
MT6359_IRQ_FG_BAT_L,
MT6359_IRQ_FG_CUR_H,
MT6359_IRQ_FG_CUR_L,
MT6359_IRQ_FG_ZCV = 84,
MT6359_IRQ_FG_N_CHARGE_L = 87,
MT6359_IRQ_FG_IAVG_H,
MT6359_IRQ_FG_IAVG_L = 89,
MT6359_IRQ_FG_DISCHARGE = 91,
MT6359_IRQ_FG_CHARGE,
MT6359_IRQ_BATON_LV = 96,
MT6359_IRQ_BATON_BAT_IN = 98,
MT6359_IRQ_BATON_BAT_OU,
MT6359_IRQ_BIF = 100,
MT6359_IRQ_BAT_H = 112,
MT6359_IRQ_BAT_L,
MT6359_IRQ_BAT2_H,
MT6359_IRQ_BAT2_L,
MT6359_IRQ_BAT_TEMP_H,
MT6359_IRQ_BAT_TEMP_L,
MT6359_IRQ_THR_H,
MT6359_IRQ_THR_L,
MT6359_IRQ_AUXADC_IMP,
MT6359_IRQ_NAG_C_DLTV = 121,
MT6359_IRQ_AUDIO = 128,
MT6359_IRQ_ACCDET = 133,
MT6359_IRQ_ACCDET_EINT0,
MT6359_IRQ_ACCDET_EINT1,
MT6359_IRQ_SPI_CMD_ALERT = 144,
MT6359_IRQ_NR,
};
#define MT6359_IRQ_BUCK_BASE MT6359_IRQ_VCORE_OC
#define MT6359_IRQ_LDO_BASE MT6359_IRQ_VFE28_OC
#define MT6359_IRQ_PSC_BASE MT6359_IRQ_PWRKEY
#define MT6359_IRQ_SCK_BASE MT6359_IRQ_RTC
#define MT6359_IRQ_BM_BASE MT6359_IRQ_FG_BAT_H
#define MT6359_IRQ_HK_BASE MT6359_IRQ_BAT_H
#define MT6359_IRQ_AUD_BASE MT6359_IRQ_AUDIO
#define MT6359_IRQ_MISC_BASE MT6359_IRQ_SPI_CMD_ALERT
#define MT6359_IRQ_BUCK_BITS (MT6359_IRQ_VPA_OC - MT6359_IRQ_BUCK_BASE + 1)
#define MT6359_IRQ_LDO_BITS (MT6359_IRQ_VUFS_OC - MT6359_IRQ_LDO_BASE + 1)
#define MT6359_IRQ_PSC_BITS \
(MT6359_IRQ_CHRDET_EDGE - MT6359_IRQ_PSC_BASE + 1)
#define MT6359_IRQ_SCK_BITS (MT6359_IRQ_RTC - MT6359_IRQ_SCK_BASE + 1)
#define MT6359_IRQ_BM_BITS (MT6359_IRQ_BIF - MT6359_IRQ_BM_BASE + 1)
#define MT6359_IRQ_HK_BITS (MT6359_IRQ_NAG_C_DLTV - MT6359_IRQ_HK_BASE + 1)
#define MT6359_IRQ_AUD_BITS \
(MT6359_IRQ_ACCDET_EINT1 - MT6359_IRQ_AUD_BASE + 1)
#define MT6359_IRQ_MISC_BITS \
(MT6359_IRQ_SPI_CMD_ALERT - MT6359_IRQ_MISC_BASE + 1)
#define MT6359_TOP_GEN(sp) \
{ \
.hwirq_base = MT6359_IRQ_##sp##_BASE, \
.num_int_regs = \
((MT6359_IRQ_##sp##_BITS - 1) / \
MTK_PMIC_REG_WIDTH) + 1, \
.en_reg = MT6359_##sp##_TOP_INT_CON0, \
.en_reg_shift = 0x6, \
.sta_reg = MT6359_##sp##_TOP_INT_STATUS0, \
.sta_reg_shift = 0x2, \
.top_offset = MT6359_##sp##_TOP, \
}
#endif /* __MFD_MT6359_CORE_H__ */

529
include/linux/mfd/mt6359/registers.h Normal file
View File

@ -0,0 +1,529 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#ifndef __MFD_MT6359_REGISTERS_H__
#define __MFD_MT6359_REGISTERS_H__
/* PMIC Registers */
#define MT6359_SWCID 0xa
#define MT6359_MISC_TOP_INT_CON0 0x188
#define MT6359_MISC_TOP_INT_STATUS0 0x194
#define MT6359_TOP_INT_STATUS0 0x19e
#define MT6359_SCK_TOP_INT_CON0 0x528
#define MT6359_SCK_TOP_INT_STATUS0 0x534
#define MT6359_EOSC_CALI_CON0 0x53a
#define MT6359_EOSC_CALI_CON1 0x53c
#define MT6359_RTC_MIX_CON0 0x53e
#define MT6359_RTC_MIX_CON1 0x540
#define MT6359_RTC_MIX_CON2 0x542
#define MT6359_RTC_DSN_ID 0x580
#define MT6359_RTC_DSN_REV0 0x582
#define MT6359_RTC_DBI 0x584
#define MT6359_RTC_DXI 0x586
#define MT6359_RTC_BBPU 0x588
#define MT6359_RTC_IRQ_STA 0x58a
#define MT6359_RTC_IRQ_EN 0x58c
#define MT6359_RTC_CII_EN 0x58e
#define MT6359_RTC_AL_MASK 0x590
#define MT6359_RTC_TC_SEC 0x592
#define MT6359_RTC_TC_MIN 0x594
#define MT6359_RTC_TC_HOU 0x596
#define MT6359_RTC_TC_DOM 0x598
#define MT6359_RTC_TC_DOW 0x59a
#define MT6359_RTC_TC_MTH 0x59c
#define MT6359_RTC_TC_YEA 0x59e
#define MT6359_RTC_AL_SEC 0x5a0
#define MT6359_RTC_AL_MIN 0x5a2
#define MT6359_RTC_AL_HOU 0x5a4
#define MT6359_RTC_AL_DOM 0x5a6
#define MT6359_RTC_AL_DOW 0x5a8
#define MT6359_RTC_AL_MTH 0x5aa
#define MT6359_RTC_AL_YEA 0x5ac
#define MT6359_RTC_OSC32CON 0x5ae
#define MT6359_RTC_POWERKEY1 0x5b0
#define MT6359_RTC_POWERKEY2 0x5b2
#define MT6359_RTC_PDN1 0x5b4
#define MT6359_RTC_PDN2 0x5b6
#define MT6359_RTC_SPAR0 0x5b8
#define MT6359_RTC_SPAR1 0x5ba
#define MT6359_RTC_PROT 0x5bc
#define MT6359_RTC_DIFF 0x5be
#define MT6359_RTC_CALI 0x5c0
#define MT6359_RTC_WRTGR 0x5c2
#define MT6359_RTC_CON 0x5c4
#define MT6359_RTC_SEC_CTRL 0x5c6
#define MT6359_RTC_INT_CNT 0x5c8
#define MT6359_RTC_SEC_DAT0 0x5ca
#define MT6359_RTC_SEC_DAT1 0x5cc
#define MT6359_RTC_SEC_DAT2 0x5ce
#define MT6359_RTC_SEC_DSN_ID 0x600
#define MT6359_RTC_SEC_DSN_REV0 0x602
#define MT6359_RTC_SEC_DBI 0x604
#define MT6359_RTC_SEC_DXI 0x606
#define MT6359_RTC_TC_SEC_SEC 0x608
#define MT6359_RTC_TC_MIN_SEC 0x60a
#define MT6359_RTC_TC_HOU_SEC 0x60c
#define MT6359_RTC_TC_DOM_SEC 0x60e
#define MT6359_RTC_TC_DOW_SEC 0x610
#define MT6359_RTC_TC_MTH_SEC 0x612
#define MT6359_RTC_TC_YEA_SEC 0x614
#define MT6359_RTC_SEC_CK_PDN 0x616
#define MT6359_RTC_SEC_WRTGR 0x618
#define MT6359_PSC_TOP_INT_CON0 0x910
#define MT6359_PSC_TOP_INT_STATUS0 0x91c
#define MT6359_BM_TOP_INT_CON0 0xc32
#define MT6359_BM_TOP_INT_CON1 0xc38
#define MT6359_BM_TOP_INT_STATUS0 0xc4a
#define MT6359_BM_TOP_INT_STATUS1 0xc4c
#define MT6359_HK_TOP_INT_CON0 0xf92
#define MT6359_HK_TOP_INT_STATUS0 0xf9e
#define MT6359_BUCK_TOP_INT_CON0 0x1418
#define MT6359_BUCK_TOP_INT_STATUS0 0x1424
#define MT6359_BUCK_VPU_CON0 0x1488
#define MT6359_BUCK_VPU_DBG0 0x14a6
#define MT6359_BUCK_VPU_DBG1 0x14a8
#define MT6359_BUCK_VPU_ELR0 0x14ac
#define MT6359_BUCK_VCORE_CON0 0x1508
#define MT6359_BUCK_VCORE_DBG0 0x1526
#define MT6359_BUCK_VCORE_DBG1 0x1528
#define MT6359_BUCK_VCORE_SSHUB_CON0 0x152a
#define MT6359_BUCK_VCORE_ELR0 0x1534
#define MT6359_BUCK_VGPU11_CON0 0x1588
#define MT6359_BUCK_VGPU11_DBG0 0x15a6
#define MT6359_BUCK_VGPU11_DBG1 0x15a8
#define MT6359_BUCK_VGPU11_ELR0 0x15ac
#define MT6359_BUCK_VMODEM_CON0 0x1688
#define MT6359_BUCK_VMODEM_DBG0 0x16a6
#define MT6359_BUCK_VMODEM_DBG1 0x16a8
#define MT6359_BUCK_VMODEM_ELR0 0x16ae
#define MT6359_BUCK_VPROC1_CON0 0x1708
#define MT6359_BUCK_VPROC1_DBG0 0x1726
#define MT6359_BUCK_VPROC1_DBG1 0x1728
#define MT6359_BUCK_VPROC1_ELR0 0x172e
#define MT6359_BUCK_VPROC2_CON0 0x1788
#define MT6359_BUCK_VPROC2_DBG0 0x17a6
#define MT6359_BUCK_VPROC2_DBG1 0x17a8
#define MT6359_BUCK_VPROC2_ELR0 0x17b2
#define MT6359_BUCK_VS1_CON0 0x1808
#define MT6359_BUCK_VS1_DBG0 0x1826
#define MT6359_BUCK_VS1_DBG1 0x1828
#define MT6359_BUCK_VS1_ELR0 0x1834
#define MT6359_BUCK_VS2_CON0 0x1888
#define MT6359_BUCK_VS2_DBG0 0x18a6
#define MT6359_BUCK_VS2_DBG1 0x18a8
#define MT6359_BUCK_VS2_ELR0 0x18b4
#define MT6359_BUCK_VPA_CON0 0x1908
#define MT6359_BUCK_VPA_CON1 0x190e
#define MT6359_BUCK_VPA_CFG0 0x1910
#define MT6359_BUCK_VPA_CFG1 0x1912
#define MT6359_BUCK_VPA_DBG0 0x1914
#define MT6359_BUCK_VPA_DBG1 0x1916
#define MT6359_VGPUVCORE_ANA_CON2 0x198e
#define MT6359_VGPUVCORE_ANA_CON13 0x19a4
#define MT6359_VPROC1_ANA_CON3 0x19b2
#define MT6359_VPROC2_ANA_CON3 0x1a0e
#define MT6359_VMODEM_ANA_CON3 0x1a1a
#define MT6359_VPU_ANA_CON3 0x1a26
#define MT6359_VS1_ANA_CON0 0x1a2c
#define MT6359_VS2_ANA_CON0 0x1a34
#define MT6359_VPA_ANA_CON0 0x1a3c
#define MT6359_LDO_TOP_INT_CON0 0x1b14
#define MT6359_LDO_TOP_INT_CON1 0x1b1a
#define MT6359_LDO_TOP_INT_STATUS0 0x1b28
#define MT6359_LDO_TOP_INT_STATUS1 0x1b2a
#define MT6359_LDO_VSRAM_PROC1_ELR 0x1b40
#define MT6359_LDO_VSRAM_PROC2_ELR 0x1b42
#define MT6359_LDO_VSRAM_OTHERS_ELR 0x1b44
#define MT6359_LDO_VSRAM_MD_ELR 0x1b46
#define MT6359_LDO_VFE28_CON0 0x1b88
#define MT6359_LDO_VFE28_MON 0x1b8a
#define MT6359_LDO_VXO22_CON0 0x1b98
#define MT6359_LDO_VXO22_MON 0x1b9a
#define MT6359_LDO_VRF18_CON0 0x1ba8
#define MT6359_LDO_VRF18_MON 0x1baa
#define MT6359_LDO_VRF12_CON0 0x1bb8
#define MT6359_LDO_VRF12_MON 0x1bba
#define MT6359_LDO_VEFUSE_CON0 0x1bc8
#define MT6359_LDO_VEFUSE_MON 0x1bca
#define MT6359_LDO_VCN33_1_CON0 0x1bd8
#define MT6359_LDO_VCN33_1_MON 0x1bda
#define MT6359_LDO_VCN33_1_MULTI_SW 0x1be8
#define MT6359_LDO_VCN33_2_CON0 0x1c08
#define MT6359_LDO_VCN33_2_MON 0x1c0a
#define MT6359_LDO_VCN33_2_MULTI_SW 0x1c18
#define MT6359_LDO_VCN13_CON0 0x1c1a
#define MT6359_LDO_VCN13_MON 0x1c1c
#define MT6359_LDO_VCN18_CON0 0x1c2a
#define MT6359_LDO_VCN18_MON 0x1c2c
#define MT6359_LDO_VA09_CON0 0x1c3a
#define MT6359_LDO_VA09_MON 0x1c3c
#define MT6359_LDO_VCAMIO_CON0 0x1c4a
#define MT6359_LDO_VCAMIO_MON 0x1c4c
#define MT6359_LDO_VA12_CON0 0x1c5a
#define MT6359_LDO_VA12_MON 0x1c5c
#define MT6359_LDO_VAUX18_CON0 0x1c88
#define MT6359_LDO_VAUX18_MON 0x1c8a
#define MT6359_LDO_VAUD18_CON0 0x1c98
#define MT6359_LDO_VAUD18_MON 0x1c9a
#define MT6359_LDO_VIO18_CON0 0x1ca8
#define MT6359_LDO_VIO18_MON 0x1caa
#define MT6359_LDO_VEMC_CON0 0x1cb8
#define MT6359_LDO_VEMC_MON 0x1cba
#define MT6359_LDO_VSIM1_CON0 0x1cc8
#define MT6359_LDO_VSIM1_MON 0x1cca
#define MT6359_LDO_VSIM2_CON0 0x1cd8
#define MT6359_LDO_VSIM2_MON 0x1cda
#define MT6359_LDO_VUSB_CON0 0x1d08
#define MT6359_LDO_VUSB_MON 0x1d0a
#define MT6359_LDO_VUSB_MULTI_SW 0x1d18
#define MT6359_LDO_VRFCK_CON0 0x1d1a
#define MT6359_LDO_VRFCK_MON 0x1d1c
#define MT6359_LDO_VBBCK_CON0 0x1d2a
#define MT6359_LDO_VBBCK_MON 0x1d2c
#define MT6359_LDO_VBIF28_CON0 0x1d3a
#define MT6359_LDO_VBIF28_MON 0x1d3c
#define MT6359_LDO_VIBR_CON0 0x1d4a
#define MT6359_LDO_VIBR_MON 0x1d4c
#define MT6359_LDO_VIO28_CON0 0x1d5a
#define MT6359_LDO_VIO28_MON 0x1d5c
#define MT6359_LDO_VM18_CON0 0x1d88
#define MT6359_LDO_VM18_MON 0x1d8a
#define MT6359_LDO_VUFS_CON0 0x1d98
#define MT6359_LDO_VUFS_MON 0x1d9a
#define MT6359_LDO_VSRAM_PROC1_CON0 0x1e88
#define MT6359_LDO_VSRAM_PROC1_MON 0x1e8a
#define MT6359_LDO_VSRAM_PROC1_VOSEL1 0x1e8e
#define MT6359_LDO_VSRAM_PROC2_CON0 0x1ea6
#define MT6359_LDO_VSRAM_PROC2_MON 0x1ea8
#define MT6359_LDO_VSRAM_PROC2_VOSEL1 0x1eac
#define MT6359_LDO_VSRAM_OTHERS_CON0 0x1f08
#define MT6359_LDO_VSRAM_OTHERS_MON 0x1f0a
#define MT6359_LDO_VSRAM_OTHERS_VOSEL1 0x1f0e
#define MT6359_LDO_VSRAM_OTHERS_SSHUB 0x1f26
#define MT6359_LDO_VSRAM_MD_CON0 0x1f2c
#define MT6359_LDO_VSRAM_MD_MON 0x1f2e
#define MT6359_LDO_VSRAM_MD_VOSEL1 0x1f32
#define MT6359_VFE28_ANA_CON0 0x1f88
#define MT6359_VAUX18_ANA_CON0 0x1f8c
#define MT6359_VUSB_ANA_CON0 0x1f90
#define MT6359_VBIF28_ANA_CON0 0x1f94
#define MT6359_VCN33_1_ANA_CON0 0x1f98
#define MT6359_VCN33_2_ANA_CON0 0x1f9c
#define MT6359_VEMC_ANA_CON0 0x1fa0
#define MT6359_VSIM1_ANA_CON0 0x1fa4
#define MT6359_VSIM2_ANA_CON0 0x1fa8
#define MT6359_VIO28_ANA_CON0 0x1fac
#define MT6359_VIBR_ANA_CON0 0x1fb0
#define MT6359_VRF18_ANA_CON0 0x2008
#define MT6359_VEFUSE_ANA_CON0 0x200c
#define MT6359_VCN18_ANA_CON0 0x2010
#define MT6359_VCAMIO_ANA_CON0 0x2014
#define MT6359_VAUD18_ANA_CON0 0x2018
#define MT6359_VIO18_ANA_CON0 0x201c
#define MT6359_VM18_ANA_CON0 0x2020
#define MT6359_VUFS_ANA_CON0 0x2024
#define MT6359_VRF12_ANA_CON0 0x202a
#define MT6359_VCN13_ANA_CON0 0x202e
#define MT6359_VA09_ANA_CON0 0x2032
#define MT6359_VA12_ANA_CON0 0x2036
#define MT6359_VXO22_ANA_CON0 0x2088
#define MT6359_VRFCK_ANA_CON0 0x208c
#define MT6359_VBBCK_ANA_CON0 0x2094
#define MT6359_AUD_TOP_INT_CON0 0x2328
#define MT6359_AUD_TOP_INT_STATUS0 0x2334
#define MT6359_RG_BUCK_VPU_EN_ADDR MT6359_BUCK_VPU_CON0
#define MT6359_RG_BUCK_VPU_LP_ADDR MT6359_BUCK_VPU_CON0
#define MT6359_RG_BUCK_VPU_LP_SHIFT 1
#define MT6359_DA_VPU_VOSEL_ADDR MT6359_BUCK_VPU_DBG0
#define MT6359_DA_VPU_VOSEL_MASK 0x7F
#define MT6359_DA_VPU_VOSEL_SHIFT 0
#define MT6359_DA_VPU_EN_ADDR MT6359_BUCK_VPU_DBG1
#define MT6359_RG_BUCK_VPU_VOSEL_ADDR MT6359_BUCK_VPU_ELR0
#define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VCORE_EN_ADDR MT6359_BUCK_VCORE_CON0
#define MT6359_RG_BUCK_VCORE_LP_ADDR MT6359_BUCK_VCORE_CON0
#define MT6359_RG_BUCK_VCORE_LP_SHIFT 1
#define MT6359_DA_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_DBG0
#define MT6359_DA_VCORE_VOSEL_MASK 0x7F
#define MT6359_DA_VCORE_VOSEL_SHIFT 0
#define MT6359_DA_VCORE_EN_ADDR MT6359_BUCK_VCORE_DBG1
#define MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR MT6359_BUCK_VCORE_SSHUB_CON0
#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR MT6359_BUCK_VCORE_SSHUB_CON0
#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT 4
#define MT6359_RG_BUCK_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_ELR0
#define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_CON0
#define MT6359_RG_BUCK_VGPU11_LP_ADDR MT6359_BUCK_VGPU11_CON0
#define MT6359_RG_BUCK_VGPU11_LP_SHIFT 1
#define MT6359_DA_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_DBG0
#define MT6359_DA_VGPU11_VOSEL_MASK 0x7F
#define MT6359_DA_VGPU11_VOSEL_SHIFT 0
#define MT6359_DA_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_DBG1
#define MT6359_RG_BUCK_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_ELR0
#define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_CON0
#define MT6359_RG_BUCK_VMODEM_LP_ADDR MT6359_BUCK_VMODEM_CON0
#define MT6359_RG_BUCK_VMODEM_LP_SHIFT 1
#define MT6359_DA_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_DBG0
#define MT6359_DA_VMODEM_VOSEL_MASK 0x7F
#define MT6359_DA_VMODEM_VOSEL_SHIFT 0
#define MT6359_DA_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_DBG1
#define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_ELR0
#define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_CON0
#define MT6359_RG_BUCK_VPROC1_LP_ADDR MT6359_BUCK_VPROC1_CON0
#define MT6359_RG_BUCK_VPROC1_LP_SHIFT 1
#define MT6359_DA_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_DBG0
#define MT6359_DA_VPROC1_VOSEL_MASK 0x7F
#define MT6359_DA_VPROC1_VOSEL_SHIFT 0
#define MT6359_DA_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_DBG1
#define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_ELR0
#define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_CON0
#define MT6359_RG_BUCK_VPROC2_LP_ADDR MT6359_BUCK_VPROC2_CON0
#define MT6359_RG_BUCK_VPROC2_LP_SHIFT 1
#define MT6359_DA_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_DBG0
#define MT6359_DA_VPROC2_VOSEL_MASK 0x7F
#define MT6359_DA_VPROC2_VOSEL_SHIFT 0
#define MT6359_DA_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_DBG1
#define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_ELR0
#define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VS1_EN_ADDR MT6359_BUCK_VS1_CON0
#define MT6359_RG_BUCK_VS1_LP_ADDR MT6359_BUCK_VS1_CON0
#define MT6359_RG_BUCK_VS1_LP_SHIFT 1
#define MT6359_DA_VS1_VOSEL_ADDR MT6359_BUCK_VS1_DBG0
#define MT6359_DA_VS1_VOSEL_MASK 0x7F
#define MT6359_DA_VS1_VOSEL_SHIFT 0
#define MT6359_DA_VS1_EN_ADDR MT6359_BUCK_VS1_DBG1
#define MT6359_RG_BUCK_VS1_VOSEL_ADDR MT6359_BUCK_VS1_ELR0
#define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VS2_EN_ADDR MT6359_BUCK_VS2_CON0
#define MT6359_RG_BUCK_VS2_LP_ADDR MT6359_BUCK_VS2_CON0
#define MT6359_RG_BUCK_VS2_LP_SHIFT 1
#define MT6359_DA_VS2_VOSEL_ADDR MT6359_BUCK_VS2_DBG0
#define MT6359_DA_VS2_VOSEL_MASK 0x7F
#define MT6359_DA_VS2_VOSEL_SHIFT 0
#define MT6359_DA_VS2_EN_ADDR MT6359_BUCK_VS2_DBG1
#define MT6359_RG_BUCK_VS2_VOSEL_ADDR MT6359_BUCK_VS2_ELR0
#define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VPA_EN_ADDR MT6359_BUCK_VPA_CON0
#define MT6359_RG_BUCK_VPA_LP_ADDR MT6359_BUCK_VPA_CON0
#define MT6359_RG_BUCK_VPA_LP_SHIFT 1
#define MT6359_RG_BUCK_VPA_VOSEL_ADDR MT6359_BUCK_VPA_CON1
#define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F
#define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0
#define MT6359_DA_VPA_VOSEL_ADDR MT6359_BUCK_VPA_DBG0
#define MT6359_DA_VPA_VOSEL_MASK 0x3F
#define MT6359_DA_VPA_VOSEL_SHIFT 0
#define MT6359_DA_VPA_EN_ADDR MT6359_BUCK_VPA_DBG1
#define MT6359_RG_VGPU11_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON2
#define MT6359_RG_VGPU11_FCCM_SHIFT 9
#define MT6359_RG_VCORE_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON13
#define MT6359_RG_VCORE_FCCM_SHIFT 5
#define MT6359_RG_VPROC1_FCCM_ADDR MT6359_VPROC1_ANA_CON3
#define MT6359_RG_VPROC1_FCCM_SHIFT 1
#define MT6359_RG_VPROC2_FCCM_ADDR MT6359_VPROC2_ANA_CON3
#define MT6359_RG_VPROC2_FCCM_SHIFT 1
#define MT6359_RG_VMODEM_FCCM_ADDR MT6359_VMODEM_ANA_CON3
#define MT6359_RG_VMODEM_FCCM_SHIFT 1
#define MT6359_RG_VPU_FCCM_ADDR MT6359_VPU_ANA_CON3
#define MT6359_RG_VPU_FCCM_SHIFT 1
#define MT6359_RG_VS1_FPWM_ADDR MT6359_VS1_ANA_CON0
#define MT6359_RG_VS1_FPWM_SHIFT 3
#define MT6359_RG_VS2_FPWM_ADDR MT6359_VS2_ANA_CON0
#define MT6359_RG_VS2_FPWM_SHIFT 3
#define MT6359_RG_VPA_MODESET_ADDR MT6359_VPA_ANA_CON0
#define MT6359_RG_VPA_MODESET_SHIFT 1
#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_ELR
#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F
#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0
#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_ELR
#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F
#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0
#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_ELR
#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F
#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0
#define MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_ELR
#define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F
#define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0
#define MT6359_RG_LDO_VFE28_EN_ADDR MT6359_LDO_VFE28_CON0
#define MT6359_DA_VFE28_B_EN_ADDR MT6359_LDO_VFE28_MON
#define MT6359_RG_LDO_VXO22_EN_ADDR MT6359_LDO_VXO22_CON0
#define MT6359_RG_LDO_VXO22_EN_SHIFT 0
#define MT6359_DA_VXO22_B_EN_ADDR MT6359_LDO_VXO22_MON
#define MT6359_RG_LDO_VRF18_EN_ADDR MT6359_LDO_VRF18_CON0
#define MT6359_RG_LDO_VRF18_EN_SHIFT 0
#define MT6359_DA_VRF18_B_EN_ADDR MT6359_LDO_VRF18_MON
#define MT6359_RG_LDO_VRF12_EN_ADDR MT6359_LDO_VRF12_CON0
#define MT6359_RG_LDO_VRF12_EN_SHIFT 0
#define MT6359_DA_VRF12_B_EN_ADDR MT6359_LDO_VRF12_MON
#define MT6359_RG_LDO_VEFUSE_EN_ADDR MT6359_LDO_VEFUSE_CON0
#define MT6359_RG_LDO_VEFUSE_EN_SHIFT 0
#define MT6359_DA_VEFUSE_B_EN_ADDR MT6359_LDO_VEFUSE_MON
#define MT6359_RG_LDO_VCN33_1_EN_0_ADDR MT6359_LDO_VCN33_1_CON0
#define MT6359_RG_LDO_VCN33_1_EN_0_MASK 0x1
#define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0
#define MT6359_DA_VCN33_1_B_EN_ADDR MT6359_LDO_VCN33_1_MON
#define MT6359_RG_LDO_VCN33_1_EN_1_ADDR MT6359_LDO_VCN33_1_MULTI_SW
#define MT6359_RG_LDO_VCN33_1_EN_1_SHIFT 15
#define MT6359_RG_LDO_VCN33_2_EN_0_ADDR MT6359_LDO_VCN33_2_CON0
#define MT6359_RG_LDO_VCN33_2_EN_0_SHIFT 0
#define MT6359_DA_VCN33_2_B_EN_ADDR MT6359_LDO_VCN33_2_MON
#define MT6359_RG_LDO_VCN33_2_EN_1_ADDR MT6359_LDO_VCN33_2_MULTI_SW
#define MT6359_RG_LDO_VCN33_2_EN_1_MASK 0x1
#define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT 15
#define MT6359_RG_LDO_VCN13_EN_ADDR MT6359_LDO_VCN13_CON0
#define MT6359_RG_LDO_VCN13_EN_SHIFT 0
#define MT6359_DA_VCN13_B_EN_ADDR MT6359_LDO_VCN13_MON
#define MT6359_RG_LDO_VCN18_EN_ADDR MT6359_LDO_VCN18_CON0
#define MT6359_DA_VCN18_B_EN_ADDR MT6359_LDO_VCN18_MON
#define MT6359_RG_LDO_VA09_EN_ADDR MT6359_LDO_VA09_CON0
#define MT6359_RG_LDO_VA09_EN_SHIFT 0
#define MT6359_DA_VA09_B_EN_ADDR MT6359_LDO_VA09_MON
#define MT6359_RG_LDO_VCAMIO_EN_ADDR MT6359_LDO_VCAMIO_CON0
#define MT6359_RG_LDO_VCAMIO_EN_SHIFT 0
#define MT6359_DA_VCAMIO_B_EN_ADDR MT6359_LDO_VCAMIO_MON
#define MT6359_RG_LDO_VA12_EN_ADDR MT6359_LDO_VA12_CON0
#define MT6359_RG_LDO_VA12_EN_SHIFT 0
#define MT6359_DA_VA12_B_EN_ADDR MT6359_LDO_VA12_MON
#define MT6359_RG_LDO_VAUX18_EN_ADDR MT6359_LDO_VAUX18_CON0
#define MT6359_DA_VAUX18_B_EN_ADDR MT6359_LDO_VAUX18_MON
#define MT6359_RG_LDO_VAUD18_EN_ADDR MT6359_LDO_VAUD18_CON0
#define MT6359_DA_VAUD18_B_EN_ADDR MT6359_LDO_VAUD18_MON
#define MT6359_RG_LDO_VIO18_EN_ADDR MT6359_LDO_VIO18_CON0
#define MT6359_RG_LDO_VIO18_EN_SHIFT 0
#define MT6359_DA_VIO18_B_EN_ADDR MT6359_LDO_VIO18_MON
#define MT6359_RG_LDO_VEMC_EN_ADDR MT6359_LDO_VEMC_CON0
#define MT6359_RG_LDO_VEMC_EN_SHIFT 0
#define MT6359_DA_VEMC_B_EN_ADDR MT6359_LDO_VEMC_MON
#define MT6359_RG_LDO_VSIM1_EN_ADDR MT6359_LDO_VSIM1_CON0
#define MT6359_RG_LDO_VSIM1_EN_SHIFT 0
#define MT6359_DA_VSIM1_B_EN_ADDR MT6359_LDO_VSIM1_MON
#define MT6359_RG_LDO_VSIM2_EN_ADDR MT6359_LDO_VSIM2_CON0
#define MT6359_RG_LDO_VSIM2_EN_SHIFT 0
#define MT6359_DA_VSIM2_B_EN_ADDR MT6359_LDO_VSIM2_MON
#define MT6359_RG_LDO_VUSB_EN_0_ADDR MT6359_LDO_VUSB_CON0
#define MT6359_RG_LDO_VUSB_EN_0_MASK 0x1
#define MT6359_RG_LDO_VUSB_EN_0_SHIFT 0
#define MT6359_DA_VUSB_B_EN_ADDR MT6359_LDO_VUSB_MON
#define MT6359_RG_LDO_VUSB_EN_1_ADDR MT6359_LDO_VUSB_MULTI_SW
#define MT6359_RG_LDO_VUSB_EN_1_MASK 0x1
#define MT6359_RG_LDO_VUSB_EN_1_SHIFT 15
#define MT6359_RG_LDO_VRFCK_EN_ADDR MT6359_LDO_VRFCK_CON0
#define MT6359_RG_LDO_VRFCK_EN_SHIFT 0
#define MT6359_DA_VRFCK_B_EN_ADDR MT6359_LDO_VRFCK_MON
#define MT6359_RG_LDO_VBBCK_EN_ADDR MT6359_LDO_VBBCK_CON0
#define MT6359_RG_LDO_VBBCK_EN_SHIFT 0
#define MT6359_DA_VBBCK_B_EN_ADDR MT6359_LDO_VBBCK_MON
#define MT6359_RG_LDO_VBIF28_EN_ADDR MT6359_LDO_VBIF28_CON0
#define MT6359_DA_VBIF28_B_EN_ADDR MT6359_LDO_VBIF28_MON
#define MT6359_RG_LDO_VIBR_EN_ADDR MT6359_LDO_VIBR_CON0
#define MT6359_RG_LDO_VIBR_EN_SHIFT 0
#define MT6359_DA_VIBR_B_EN_ADDR MT6359_LDO_VIBR_MON
#define MT6359_RG_LDO_VIO28_EN_ADDR MT6359_LDO_VIO28_CON0
#define MT6359_RG_LDO_VIO28_EN_SHIFT 0
#define MT6359_DA_VIO28_B_EN_ADDR MT6359_LDO_VIO28_MON
#define MT6359_RG_LDO_VM18_EN_ADDR MT6359_LDO_VM18_CON0
#define MT6359_RG_LDO_VM18_EN_SHIFT 0
#define MT6359_DA_VM18_B_EN_ADDR MT6359_LDO_VM18_MON
#define MT6359_RG_LDO_VUFS_EN_ADDR MT6359_LDO_VUFS_CON0
#define MT6359_RG_LDO_VUFS_EN_SHIFT 0
#define MT6359_DA_VUFS_B_EN_ADDR MT6359_LDO_VUFS_MON
#define MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359_LDO_VSRAM_PROC1_CON0
#define MT6359_DA_VSRAM_PROC1_B_EN_ADDR MT6359_LDO_VSRAM_PROC1_MON
#define MT6359_DA_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_VOSEL1
#define MT6359_DA_VSRAM_PROC1_VOSEL_MASK 0x7F
#define MT6359_DA_VSRAM_PROC1_VOSEL_SHIFT 8
#define MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359_LDO_VSRAM_PROC2_CON0
#define MT6359_DA_VSRAM_PROC2_B_EN_ADDR MT6359_LDO_VSRAM_PROC2_MON
#define MT6359_DA_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_VOSEL1
#define MT6359_DA_VSRAM_PROC2_VOSEL_MASK 0x7F
#define MT6359_DA_VSRAM_PROC2_VOSEL_SHIFT 8
#define MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359_LDO_VSRAM_OTHERS_CON0
#define MT6359_DA_VSRAM_OTHERS_B_EN_ADDR MT6359_LDO_VSRAM_OTHERS_MON
#define MT6359_DA_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_VOSEL1
#define MT6359_DA_VSRAM_OTHERS_VOSEL_MASK 0x7F
#define MT6359_DA_VSRAM_OTHERS_VOSEL_SHIFT 8
#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR MT6359_LDO_VSRAM_OTHERS_SSHUB
#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_SSHUB
#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F
#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1
#define MT6359_RG_LDO_VSRAM_MD_EN_ADDR MT6359_LDO_VSRAM_MD_CON0
#define MT6359_DA_VSRAM_MD_B_EN_ADDR MT6359_LDO_VSRAM_MD_MON
#define MT6359_DA_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_VOSEL1
#define MT6359_DA_VSRAM_MD_VOSEL_MASK 0x7F
#define MT6359_DA_VSRAM_MD_VOSEL_SHIFT 8
#define MT6359_RG_VCN33_1_VOSEL_ADDR MT6359_VCN33_1_ANA_CON0
#define MT6359_RG_VCN33_1_VOSEL_MASK 0xF
#define MT6359_RG_VCN33_1_VOSEL_SHIFT 8
#define MT6359_RG_VCN33_2_VOSEL_ADDR MT6359_VCN33_2_ANA_CON0
#define MT6359_RG_VCN33_2_VOSEL_MASK 0xF
#define MT6359_RG_VCN33_2_VOSEL_SHIFT 8
#define MT6359_RG_VEMC_VOSEL_ADDR MT6359_VEMC_ANA_CON0
#define MT6359_RG_VEMC_VOSEL_MASK 0xF
#define MT6359_RG_VEMC_VOSEL_SHIFT 8
#define MT6359_RG_VSIM1_VOSEL_ADDR MT6359_VSIM1_ANA_CON0
#define MT6359_RG_VSIM1_VOSEL_MASK 0xF
#define MT6359_RG_VSIM1_VOSEL_SHIFT 8
#define MT6359_RG_VSIM2_VOSEL_ADDR MT6359_VSIM2_ANA_CON0
#define MT6359_RG_VSIM2_VOSEL_MASK 0xF
#define MT6359_RG_VSIM2_VOSEL_SHIFT 8
#define MT6359_RG_VIO28_VOSEL_ADDR MT6359_VIO28_ANA_CON0
#define MT6359_RG_VIO28_VOSEL_MASK 0xF
#define MT6359_RG_VIO28_VOSEL_SHIFT 8
#define MT6359_RG_VIBR_VOSEL_ADDR MT6359_VIBR_ANA_CON0
#define MT6359_RG_VIBR_VOSEL_MASK 0xF
#define MT6359_RG_VIBR_VOSEL_SHIFT 8
#define MT6359_RG_VRF18_VOSEL_ADDR MT6359_VRF18_ANA_CON0
#define MT6359_RG_VRF18_VOSEL_MASK 0xF
#define MT6359_RG_VRF18_VOSEL_SHIFT 8
#define MT6359_RG_VEFUSE_VOSEL_ADDR MT6359_VEFUSE_ANA_CON0
#define MT6359_RG_VEFUSE_VOSEL_MASK 0xF
#define MT6359_RG_VEFUSE_VOSEL_SHIFT 8
#define MT6359_RG_VCAMIO_VOSEL_ADDR MT6359_VCAMIO_ANA_CON0
#define MT6359_RG_VCAMIO_VOSEL_MASK 0xF
#define MT6359_RG_VCAMIO_VOSEL_SHIFT 8
#define MT6359_RG_VIO18_VOSEL_ADDR MT6359_VIO18_ANA_CON0
#define MT6359_RG_VIO18_VOSEL_MASK 0xF
#define MT6359_RG_VIO18_VOSEL_SHIFT 8
#define MT6359_RG_VM18_VOSEL_ADDR MT6359_VM18_ANA_CON0
#define MT6359_RG_VM18_VOSEL_MASK 0xF
#define MT6359_RG_VM18_VOSEL_SHIFT 8
#define MT6359_RG_VUFS_VOSEL_ADDR MT6359_VUFS_ANA_CON0
#define MT6359_RG_VUFS_VOSEL_MASK 0xF
#define MT6359_RG_VUFS_VOSEL_SHIFT 8
#define MT6359_RG_VRF12_VOSEL_ADDR MT6359_VRF12_ANA_CON0
#define MT6359_RG_VRF12_VOSEL_MASK 0xF
#define MT6359_RG_VRF12_VOSEL_SHIFT 8
#define MT6359_RG_VCN13_VOSEL_ADDR MT6359_VCN13_ANA_CON0
#define MT6359_RG_VCN13_VOSEL_MASK 0xF
#define MT6359_RG_VCN13_VOSEL_SHIFT 8
#define MT6359_RG_VA09_VOSEL_ADDR MT6359_VA09_ANA_CON0
#define MT6359_RG_VA09_VOSEL_MASK 0xF
#define MT6359_RG_VA09_VOSEL_SHIFT 8
#define MT6359_RG_VA12_VOSEL_ADDR MT6359_VA12_ANA_CON0
#define MT6359_RG_VA12_VOSEL_MASK 0xF
#define MT6359_RG_VA12_VOSEL_SHIFT 8
#define MT6359_RG_VXO22_VOSEL_ADDR MT6359_VXO22_ANA_CON0
#define MT6359_RG_VXO22_VOSEL_MASK 0xF
#define MT6359_RG_VXO22_VOSEL_SHIFT 8
#define MT6359_RG_VRFCK_VOSEL_ADDR MT6359_VRFCK_ANA_CON0
#define MT6359_RG_VRFCK_VOSEL_MASK 0xF
#define MT6359_RG_VRFCK_VOSEL_SHIFT 8
#define MT6359_RG_VBBCK_VOSEL_ADDR MT6359_VBBCK_ANA_CON0
#define MT6359_RG_VBBCK_VOSEL_MASK 0xF
#define MT6359_RG_VBBCK_VOSEL_SHIFT 8
#endif /* __MFD_MT6359_REGISTERS_H__ */

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#ifndef __MFD_MT6359P_REGISTERS_H__
#define __MFD_MT6359P_REGISTERS_H__
#define MT6359P_CHIP_VER 0x5930
/* PMIC Registers */
#define MT6359P_HWCID 0x8
#define MT6359P_TOP_TRAP 0x50
#define MT6359P_TOP_TMA_KEY 0x3a8
#define MT6359P_BUCK_VCORE_ELR_NUM 0x152a
#define MT6359P_BUCK_VCORE_ELR0 0x152c
#define MT6359P_BUCK_VGPU11_SSHUB_CON0 0x15aa
#define MT6359P_BUCK_VGPU11_ELR0 0x15b4
#define MT6359P_LDO_VSRAM_PROC1_ELR 0x1b44
#define MT6359P_LDO_VSRAM_PROC2_ELR 0x1b46
#define MT6359P_LDO_VSRAM_OTHERS_ELR 0x1b48
#define MT6359P_LDO_VSRAM_MD_ELR 0x1b4a
#define MT6359P_LDO_VEMC_ELR_0 0x1b4c
#define MT6359P_LDO_VFE28_CON0 0x1b88
#define MT6359P_LDO_VFE28_MON 0x1b8c
#define MT6359P_LDO_VXO22_CON0 0x1b9a
#define MT6359P_LDO_VXO22_MON 0x1b9e
#define MT6359P_LDO_VRF18_CON0 0x1bac
#define MT6359P_LDO_VRF18_MON 0x1bb0
#define MT6359P_LDO_VRF12_CON0 0x1bbe
#define MT6359P_LDO_VRF12_MON 0x1bc2
#define MT6359P_LDO_VEFUSE_CON0 0x1bd0
#define MT6359P_LDO_VEFUSE_MON 0x1bd4
#define MT6359P_LDO_VCN33_1_CON0 0x1be2
#define MT6359P_LDO_VCN33_1_MON 0x1be6
#define MT6359P_LDO_VCN33_1_MULTI_SW 0x1bf4
#define MT6359P_LDO_VCN33_2_CON0 0x1c08
#define MT6359P_LDO_VCN33_2_MON 0x1c0c
#define MT6359P_LDO_VCN33_2_MULTI_SW 0x1c1a
#define MT6359P_LDO_VCN13_CON0 0x1c1c
#define MT6359P_LDO_VCN13_MON 0x1c20
#define MT6359P_LDO_VCN18_CON0 0x1c2e
#define MT6359P_LDO_VCN18_MON 0x1c32
#define MT6359P_LDO_VA09_CON0 0x1c40
#define MT6359P_LDO_VA09_MON 0x1c44
#define MT6359P_LDO_VCAMIO_CON0 0x1c52
#define MT6359P_LDO_VCAMIO_MON 0x1c56
#define MT6359P_LDO_VA12_CON0 0x1c64
#define MT6359P_LDO_VA12_MON 0x1c68
#define MT6359P_LDO_VAUX18_CON0 0x1c88
#define MT6359P_LDO_VAUX18_MON 0x1c8c
#define MT6359P_LDO_VAUD18_CON0 0x1c9a
#define MT6359P_LDO_VAUD18_MON 0x1c9e
#define MT6359P_LDO_VIO18_CON0 0x1cac
#define MT6359P_LDO_VIO18_MON 0x1cb0
#define MT6359P_LDO_VEMC_CON0 0x1cbe
#define MT6359P_LDO_VEMC_MON 0x1cc2
#define MT6359P_LDO_VSIM1_CON0 0x1cd0
#define MT6359P_LDO_VSIM1_MON 0x1cd4
#define MT6359P_LDO_VSIM2_CON0 0x1ce2
#define MT6359P_LDO_VSIM2_MON 0x1ce6
#define MT6359P_LDO_VUSB_CON0 0x1d08
#define MT6359P_LDO_VUSB_MON 0x1d0c
#define MT6359P_LDO_VUSB_MULTI_SW 0x1d1a
#define MT6359P_LDO_VRFCK_CON0 0x1d1c
#define MT6359P_LDO_VRFCK_MON 0x1d20
#define MT6359P_LDO_VBBCK_CON0 0x1d2e
#define MT6359P_LDO_VBBCK_MON 0x1d32
#define MT6359P_LDO_VBIF28_CON0 0x1d40
#define MT6359P_LDO_VBIF28_MON 0x1d44
#define MT6359P_LDO_VIBR_CON0 0x1d52
#define MT6359P_LDO_VIBR_MON 0x1d56
#define MT6359P_LDO_VIO28_CON0 0x1d64
#define MT6359P_LDO_VIO28_MON 0x1d68
#define MT6359P_LDO_VM18_CON0 0x1d88
#define MT6359P_LDO_VM18_MON 0x1d8c
#define MT6359P_LDO_VUFS_CON0 0x1d9a
#define MT6359P_LDO_VUFS_MON 0x1d9e
#define MT6359P_LDO_VSRAM_PROC1_CON0 0x1e88
#define MT6359P_LDO_VSRAM_PROC1_MON 0x1e8c
#define MT6359P_LDO_VSRAM_PROC1_VOSEL1 0x1e90
#define MT6359P_LDO_VSRAM_PROC2_CON0 0x1ea8
#define MT6359P_LDO_VSRAM_PROC2_MON 0x1eac
#define MT6359P_LDO_VSRAM_PROC2_VOSEL1 0x1eb0
#define MT6359P_LDO_VSRAM_OTHERS_CON0 0x1f08
#define MT6359P_LDO_VSRAM_OTHERS_MON 0x1f0c
#define MT6359P_LDO_VSRAM_OTHERS_VOSEL1 0x1f10
#define MT6359P_LDO_VSRAM_OTHERS_SSHUB 0x1f28
#define MT6359P_LDO_VSRAM_MD_CON0 0x1f2e
#define MT6359P_LDO_VSRAM_MD_MON 0x1f32
#define MT6359P_LDO_VSRAM_MD_VOSEL1 0x1f36
#define MT6359P_VFE28_ANA_CON0 0x1f88
#define MT6359P_VAUX18_ANA_CON0 0x1f8c
#define MT6359P_VUSB_ANA_CON0 0x1f90
#define MT6359P_VBIF28_ANA_CON0 0x1f94
#define MT6359P_VCN33_1_ANA_CON0 0x1f98
#define MT6359P_VCN33_2_ANA_CON0 0x1f9c
#define MT6359P_VEMC_ANA_CON0 0x1fa0
#define MT6359P_VSIM1_ANA_CON0 0x1fa2
#define MT6359P_VSIM2_ANA_CON0 0x1fa6
#define MT6359P_VIO28_ANA_CON0 0x1faa
#define MT6359P_VIBR_ANA_CON0 0x1fae
#define MT6359P_VFE28_ELR_4 0x1fc0
#define MT6359P_VRF18_ANA_CON0 0x2008
#define MT6359P_VEFUSE_ANA_CON0 0x200c
#define MT6359P_VCN18_ANA_CON0 0x2010
#define MT6359P_VCAMIO_ANA_CON0 0x2014
#define MT6359P_VAUD18_ANA_CON0 0x2018
#define MT6359P_VIO18_ANA_CON0 0x201c
#define MT6359P_VM18_ANA_CON0 0x2020
#define MT6359P_VUFS_ANA_CON0 0x2024
#define MT6359P_VRF12_ANA_CON0 0x202a
#define MT6359P_VCN13_ANA_CON0 0x202e
#define MT6359P_VA09_ANA_CON0 0x2032
#define MT6359P_VRF18_ELR_3 0x204e
#define MT6359P_VXO22_ANA_CON0 0x2088
#define MT6359P_VRFCK_ANA_CON0 0x208c
#define MT6359P_VBBCK_ANA_CON0 0x2096
#define MT6359P_RG_BUCK_VCORE_VOSEL_ADDR MT6359P_BUCK_VCORE_ELR0
#define MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0
#define MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR MT6359P_BUCK_VGPU11_ELR0
#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0
#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK 0x7F
#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT 4
#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC1_ELR
#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC2_ELR
#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_ELR
#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359P_LDO_VSRAM_MD_ELR
#define MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR MT6359P_LDO_VEMC_ELR_0
#define MT6359P_RG_LDO_VEMC_VOSEL_0_MASK 0xF
#define MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT 0
#define MT6359P_RG_LDO_VFE28_EN_ADDR MT6359P_LDO_VFE28_CON0
#define MT6359P_DA_VFE28_B_EN_ADDR MT6359P_LDO_VFE28_MON
#define MT6359P_RG_LDO_VXO22_EN_ADDR MT6359P_LDO_VXO22_CON0
#define MT6359P_RG_LDO_VXO22_EN_SHIFT 0
#define MT6359P_DA_VXO22_B_EN_ADDR MT6359P_LDO_VXO22_MON
#define MT6359P_RG_LDO_VRF18_EN_ADDR MT6359P_LDO_VRF18_CON0
#define MT6359P_RG_LDO_VRF18_EN_SHIFT 0
#define MT6359P_DA_VRF18_B_EN_ADDR MT6359P_LDO_VRF18_MON
#define MT6359P_RG_LDO_VRF12_EN_ADDR MT6359P_LDO_VRF12_CON0
#define MT6359P_RG_LDO_VRF12_EN_SHIFT 0
#define MT6359P_DA_VRF12_B_EN_ADDR MT6359P_LDO_VRF12_MON
#define MT6359P_RG_LDO_VEFUSE_EN_ADDR MT6359P_LDO_VEFUSE_CON0
#define MT6359P_RG_LDO_VEFUSE_EN_SHIFT 0
#define MT6359P_DA_VEFUSE_B_EN_ADDR MT6359P_LDO_VEFUSE_MON
#define MT6359P_RG_LDO_VCN33_1_EN_0_ADDR MT6359P_LDO_VCN33_1_CON0
#define MT6359P_DA_VCN33_1_B_EN_ADDR MT6359P_LDO_VCN33_1_MON
#define MT6359P_RG_LDO_VCN33_1_EN_1_ADDR MT6359P_LDO_VCN33_1_MULTI_SW
#define MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT 15
#define MT6359P_RG_LDO_VCN33_2_EN_0_ADDR MT6359P_LDO_VCN33_2_CON0
#define MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT 0
#define MT6359P_DA_VCN33_2_B_EN_ADDR MT6359P_LDO_VCN33_2_MON
#define MT6359P_RG_LDO_VCN33_2_EN_1_ADDR MT6359P_LDO_VCN33_2_MULTI_SW
#define MT6359P_RG_LDO_VCN13_EN_ADDR MT6359P_LDO_VCN13_CON0
#define MT6359P_RG_LDO_VCN13_EN_SHIFT 0
#define MT6359P_DA_VCN13_B_EN_ADDR MT6359P_LDO_VCN13_MON
#define MT6359P_RG_LDO_VCN18_EN_ADDR MT6359P_LDO_VCN18_CON0
#define MT6359P_DA_VCN18_B_EN_ADDR MT6359P_LDO_VCN18_MON
#define MT6359P_RG_LDO_VA09_EN_ADDR MT6359P_LDO_VA09_CON0
#define MT6359P_RG_LDO_VA09_EN_SHIFT 0
#define MT6359P_DA_VA09_B_EN_ADDR MT6359P_LDO_VA09_MON
#define MT6359P_RG_LDO_VCAMIO_EN_ADDR MT6359P_LDO_VCAMIO_CON0
#define MT6359P_RG_LDO_VCAMIO_EN_SHIFT 0
#define MT6359P_DA_VCAMIO_B_EN_ADDR MT6359P_LDO_VCAMIO_MON
#define MT6359P_RG_LDO_VA12_EN_ADDR MT6359P_LDO_VA12_CON0
#define MT6359P_RG_LDO_VA12_EN_SHIFT 0
#define MT6359P_DA_VA12_B_EN_ADDR MT6359P_LDO_VA12_MON
#define MT6359P_RG_LDO_VAUX18_EN_ADDR MT6359P_LDO_VAUX18_CON0
#define MT6359P_DA_VAUX18_B_EN_ADDR MT6359P_LDO_VAUX18_MON
#define MT6359P_RG_LDO_VAUD18_EN_ADDR MT6359P_LDO_VAUD18_CON0
#define MT6359P_DA_VAUD18_B_EN_ADDR MT6359P_LDO_VAUD18_MON
#define MT6359P_RG_LDO_VIO18_EN_ADDR MT6359P_LDO_VIO18_CON0
#define MT6359P_RG_LDO_VIO18_EN_SHIFT 0
#define MT6359P_DA_VIO18_B_EN_ADDR MT6359P_LDO_VIO18_MON
#define MT6359P_RG_LDO_VEMC_EN_ADDR MT6359P_LDO_VEMC_CON0
#define MT6359P_RG_LDO_VEMC_EN_SHIFT 0
#define MT6359P_DA_VEMC_B_EN_ADDR MT6359P_LDO_VEMC_MON
#define MT6359P_RG_LDO_VSIM1_EN_ADDR MT6359P_LDO_VSIM1_CON0
#define MT6359P_RG_LDO_VSIM1_EN_SHIFT 0
#define MT6359P_DA_VSIM1_B_EN_ADDR MT6359P_LDO_VSIM1_MON
#define MT6359P_RG_LDO_VSIM2_EN_ADDR MT6359P_LDO_VSIM2_CON0
#define MT6359P_RG_LDO_VSIM2_EN_SHIFT 0
#define MT6359P_DA_VSIM2_B_EN_ADDR MT6359P_LDO_VSIM2_MON
#define MT6359P_RG_LDO_VUSB_EN_0_ADDR MT6359P_LDO_VUSB_CON0
#define MT6359P_DA_VUSB_B_EN_ADDR MT6359P_LDO_VUSB_MON
#define MT6359P_RG_LDO_VUSB_EN_1_ADDR MT6359P_LDO_VUSB_MULTI_SW
#define MT6359P_RG_LDO_VRFCK_EN_ADDR MT6359P_LDO_VRFCK_CON0
#define MT6359P_RG_LDO_VRFCK_EN_SHIFT 0
#define MT6359P_DA_VRFCK_B_EN_ADDR MT6359P_LDO_VRFCK_MON
#define MT6359P_RG_LDO_VBBCK_EN_ADDR MT6359P_LDO_VBBCK_CON0
#define MT6359P_RG_LDO_VBBCK_EN_SHIFT 0
#define MT6359P_DA_VBBCK_B_EN_ADDR MT6359P_LDO_VBBCK_MON
#define MT6359P_RG_LDO_VBIF28_EN_ADDR MT6359P_LDO_VBIF28_CON0
#define MT6359P_DA_VBIF28_B_EN_ADDR MT6359P_LDO_VBIF28_MON
#define MT6359P_RG_LDO_VIBR_EN_ADDR MT6359P_LDO_VIBR_CON0
#define MT6359P_RG_LDO_VIBR_EN_SHIFT 0
#define MT6359P_DA_VIBR_B_EN_ADDR MT6359P_LDO_VIBR_MON
#define MT6359P_RG_LDO_VIO28_EN_ADDR MT6359P_LDO_VIO28_CON0
#define MT6359P_RG_LDO_VIO28_EN_SHIFT 0
#define MT6359P_DA_VIO28_B_EN_ADDR MT6359P_LDO_VIO28_MON
#define MT6359P_RG_LDO_VM18_EN_ADDR MT6359P_LDO_VM18_CON0
#define MT6359P_RG_LDO_VM18_EN_SHIFT 0
#define MT6359P_DA_VM18_B_EN_ADDR MT6359P_LDO_VM18_MON
#define MT6359P_RG_LDO_VUFS_EN_ADDR MT6359P_LDO_VUFS_CON0
#define MT6359P_RG_LDO_VUFS_EN_SHIFT 0
#define MT6359P_DA_VUFS_B_EN_ADDR MT6359P_LDO_VUFS_MON
#define MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359P_LDO_VSRAM_PROC1_CON0
#define MT6359P_DA_VSRAM_PROC1_B_EN_ADDR MT6359P_LDO_VSRAM_PROC1_MON
#define MT6359P_DA_VSRAM_PROC1_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC1_VOSEL1
#define MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359P_LDO_VSRAM_PROC2_CON0
#define MT6359P_DA_VSRAM_PROC2_B_EN_ADDR MT6359P_LDO_VSRAM_PROC2_MON
#define MT6359P_DA_VSRAM_PROC2_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC2_VOSEL1
#define MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_CON0
#define MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_MON
#define MT6359P_DA_VSRAM_OTHERS_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_VOSEL1
#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB
#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB
#define MT6359P_RG_LDO_VSRAM_MD_EN_ADDR MT6359P_LDO_VSRAM_MD_CON0
#define MT6359P_DA_VSRAM_MD_B_EN_ADDR MT6359P_LDO_VSRAM_MD_MON
#define MT6359P_DA_VSRAM_MD_VOSEL_ADDR MT6359P_LDO_VSRAM_MD_VOSEL1
#define MT6359P_RG_VCN33_1_VOSEL_ADDR MT6359P_VCN33_1_ANA_CON0
#define MT6359P_RG_VCN33_2_VOSEL_ADDR MT6359P_VCN33_2_ANA_CON0
#define MT6359P_RG_VEMC_VOSEL_ADDR MT6359P_VEMC_ANA_CON0
#define MT6359P_RG_VSIM1_VOSEL_ADDR MT6359P_VSIM1_ANA_CON0
#define MT6359P_RG_VSIM2_VOSEL_ADDR MT6359P_VSIM2_ANA_CON0
#define MT6359P_RG_VIO28_VOSEL_ADDR MT6359P_VIO28_ANA_CON0
#define MT6359P_RG_VIBR_VOSEL_ADDR MT6359P_VIBR_ANA_CON0
#define MT6359P_RG_VRF18_VOSEL_ADDR MT6359P_VRF18_ANA_CON0
#define MT6359P_RG_VEFUSE_VOSEL_ADDR MT6359P_VEFUSE_ANA_CON0
#define MT6359P_RG_VCAMIO_VOSEL_ADDR MT6359P_VCAMIO_ANA_CON0
#define MT6359P_RG_VIO18_VOSEL_ADDR MT6359P_VIO18_ANA_CON0
#define MT6359P_RG_VM18_VOSEL_ADDR MT6359P_VM18_ANA_CON0
#define MT6359P_RG_VUFS_VOSEL_ADDR MT6359P_VUFS_ANA_CON0
#define MT6359P_RG_VRF12_VOSEL_ADDR MT6359P_VRF12_ANA_CON0
#define MT6359P_RG_VCN13_VOSEL_ADDR MT6359P_VCN13_ANA_CON0
#define MT6359P_RG_VA09_VOSEL_ADDR MT6359P_VRF18_ELR_3
#define MT6359P_RG_VA12_VOSEL_ADDR MT6359P_VFE28_ELR_4
#define MT6359P_RG_VXO22_VOSEL_ADDR MT6359P_VXO22_ANA_CON0
#define MT6359P_RG_VRFCK_VOSEL_ADDR MT6359P_VRFCK_ANA_CON0
#define MT6359P_RG_VBBCK_VOSEL_ADDR MT6359P_VBBCK_ANA_CON0
#define MT6359P_RG_VBBCK_VOSEL_MASK 0xF
#define MT6359P_RG_VBBCK_VOSEL_SHIFT 4
#define MT6359P_VM_MODE_ADDR MT6359P_TOP_TRAP
#define MT6359P_TMA_KEY_ADDR MT6359P_TOP_TMA_KEY
#define TMA_KEY 0x9CA6
#endif /* __MFD_MT6359P_REGISTERS_H__ */

1
include/linux/mfd/mt6397/core.h
View File

@ -13,6 +13,7 @@
enum chip_id {
MT6323_CHIP_ID = 0x23,
MT6358_CHIP_ID = 0x58,
MT6359_CHIP_ID = 0x59,
MT6391_CHIP_ID = 0x91,
MT6397_CHIP_ID = 0x97,
};

1
include/linux/mfd/mt6397/rtc.h
View File

@ -36,6 +36,7 @@
#define RTC_AL_MASK_DOW BIT(4)
#define RTC_TC_SEC 0x000a
#define RTC_TC_MTH_MASK 0x000f
/* Min, Hour, Dom... register offset to RTC_TC_SEC */
#define RTC_OFFSET_SEC 0
#define RTC_OFFSET_MIN 1

59
include/linux/regulator/mt6359-regulator.h Normal file
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@ -0,0 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#ifndef __LINUX_REGULATOR_MT6359_H
#define __LINUX_REGULATOR_MT6359_H
enum {
MT6359_ID_VS1 = 0,
MT6359_ID_VGPU11,
MT6359_ID_VMODEM,
MT6359_ID_VPU,
MT6359_ID_VCORE,
MT6359_ID_VS2,
MT6359_ID_VPA,
MT6359_ID_VPROC2,
MT6359_ID_VPROC1,
MT6359_ID_VCORE_SSHUB,
MT6359_ID_VGPU11_SSHUB = MT6359_ID_VCORE_SSHUB,
MT6359_ID_VAUD18 = 10,
MT6359_ID_VSIM1,
MT6359_ID_VIBR,
MT6359_ID_VRF12,
MT6359_ID_VUSB,
MT6359_ID_VSRAM_PROC2,
MT6359_ID_VIO18,
MT6359_ID_VCAMIO,
MT6359_ID_VCN18,
MT6359_ID_VFE28,
MT6359_ID_VCN13,
MT6359_ID_VCN33_1_BT,
MT6359_ID_VCN33_1_WIFI,
MT6359_ID_VAUX18,
MT6359_ID_VSRAM_OTHERS,
MT6359_ID_VEFUSE,
MT6359_ID_VXO22,
MT6359_ID_VRFCK,
MT6359_ID_VBIF28,
MT6359_ID_VIO28,
MT6359_ID_VEMC,
MT6359_ID_VCN33_2_BT,
MT6359_ID_VCN33_2_WIFI,
MT6359_ID_VA12,
MT6359_ID_VA09,
MT6359_ID_VRF18,
MT6359_ID_VSRAM_MD,
MT6359_ID_VUFS,
MT6359_ID_VM18,
MT6359_ID_VBBCK,
MT6359_ID_VSRAM_PROC1,
MT6359_ID_VSIM2,
MT6359_ID_VSRAM_OTHERS_SSHUB,
MT6359_ID_RG_MAX,
};
#define MT6359_MAX_REGULATOR MT6359_ID_RG_MAX
#endif /* __LINUX_REGULATOR_MT6359_H */