m68k/mm: move {cache,nocahe}_page() definitions close to their user
The cache_page() and nocache_page() functions are only used by the motorola MMU variant for setting caching attributes for the page table pages. Move the definitions of these functions from arch/m68k/include/asm/motorola_pgtable.h closer to their usage in arch/m68k/mm/motorola.c and drop unused definition in arch/m68k/include/asm/mcf_pgtable.h. Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Acked-by: Greg Ungerer <gerg@linux-m68k.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Cain <bcain@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Zankel <chris@zankel.net> Cc: "David S. Miller" <davem@davemloft.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greentime Hu <green.hu@gmail.com> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Guo Ren <guoren@kernel.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Helge Deller <deller@gmx.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Mark Salter <msalter@redhat.com> Cc: Matthew Wilcox <willy@infradead.org> Cc: Matt Turner <mattst88@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Nick Hu <nickhu@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Richard Weinberger <richard@nod.at> Cc: Rich Felker <dalias@libc.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Stafford Horne <shorne@gmail.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Vincent Chen <deanbo422@gmail.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Will Deacon <will@kernel.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Link: http://lkml.kernel.org/r/20200514170327.31389-7-rppt@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -328,46 +328,6 @@ extern pgd_t kernel_pg_dir[PTRS_PER_PGD];
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#define pte_offset_kernel(dir, address) \
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((pte_t *) __pmd_page(*(dir)) + __pte_offset(address))
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/*
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* Disable caching for page at given kernel virtual address.
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*/
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static inline void nocache_page(void *vaddr)
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{
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pgd_t *dir;
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p4d_t *p4dp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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unsigned long addr = (unsigned long) vaddr;
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dir = pgd_offset_k(addr);
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p4dp = p4d_offset(dir, addr);
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pudp = pud_offset(p4dp, addr);
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pmdp = pmd_offset(pudp, addr);
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ptep = pte_offset_kernel(pmdp, addr);
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*ptep = pte_mknocache(*ptep);
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}
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/*
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* Enable caching for page at given kernel virtual address.
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*/
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static inline void cache_page(void *vaddr)
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{
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pgd_t *dir;
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p4d_t *p4dp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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unsigned long addr = (unsigned long) vaddr;
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dir = pgd_offset_k(addr);
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p4dp = p4d_offset(dir, addr);
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pudp = pud_offset(p4dp, addr);
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pmdp = pmd_offset(pudp, addr);
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ptep = pte_offset_kernel(pmdp, addr);
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*ptep = pte_mkcache(*ptep);
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}
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/*
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* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e))
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*/
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@ -227,50 +227,6 @@ static inline pte_t *pte_offset_kernel(pmd_t *pmdp, unsigned long address)
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#define pte_offset_map(pmdp,address) ((pte_t *)__pmd_page(*pmdp) + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
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#define pte_unmap(pte) ((void)0)
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/* Prior to calling these routines, the page should have been flushed
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* from both the cache and ATC, or the CPU might not notice that the
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* cache setting for the page has been changed. -jskov
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*/
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static inline void nocache_page(void *vaddr)
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{
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unsigned long addr = (unsigned long)vaddr;
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if (CPU_IS_040_OR_060) {
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pgd_t *dir;
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p4d_t *p4dp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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dir = pgd_offset_k(addr);
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p4dp = p4d_offset(dir, addr);
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pudp = pud_offset(p4dp, addr);
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pmdp = pmd_offset(pudp, addr);
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ptep = pte_offset_kernel(pmdp, addr);
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*ptep = pte_mknocache(*ptep);
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}
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}
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static inline void cache_page(void *vaddr)
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{
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unsigned long addr = (unsigned long)vaddr;
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if (CPU_IS_040_OR_060) {
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pgd_t *dir;
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p4d_t *p4dp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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dir = pgd_offset_k(addr);
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p4dp = p4d_offset(dir, addr);
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pudp = pud_offset(p4dp, addr);
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pmdp = pmd_offset(pudp, addr);
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ptep = pte_offset_kernel(pmdp, addr);
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*ptep = pte_mkcache(*ptep);
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}
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}
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/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
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#define __swp_type(x) (((x).val >> 4) & 0xff)
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#define __swp_offset(x) ((x).val >> 12)
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@ -45,6 +45,49 @@ unsigned long mm_cachebits;
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EXPORT_SYMBOL(mm_cachebits);
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#endif
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/* Prior to calling these routines, the page should have been flushed
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* from both the cache and ATC, or the CPU might not notice that the
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* cache setting for the page has been changed. -jskov
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*/
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static inline void nocache_page(void *vaddr)
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{
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unsigned long addr = (unsigned long)vaddr;
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if (CPU_IS_040_OR_060) {
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pgd_t *dir;
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p4d_t *p4dp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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dir = pgd_offset_k(addr);
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p4dp = p4d_offset(dir, addr);
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pudp = pud_offset(p4dp, addr);
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pmdp = pmd_offset(pudp, addr);
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ptep = pte_offset_kernel(pmdp, addr);
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*ptep = pte_mknocache(*ptep);
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}
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}
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static inline void cache_page(void *vaddr)
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{
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unsigned long addr = (unsigned long)vaddr;
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if (CPU_IS_040_OR_060) {
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pgd_t *dir;
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p4d_t *p4dp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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dir = pgd_offset_k(addr);
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p4dp = p4d_offset(dir, addr);
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pudp = pud_offset(p4dp, addr);
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pmdp = pmd_offset(pudp, addr);
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ptep = pte_offset_kernel(pmdp, addr);
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*ptep = pte_mkcache(*ptep);
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}
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}
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/*
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* Motorola 680x0 user's manual recommends using uncached memory for address
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