GPIO bug fixes on top of v3.4-rc6
An OMAP bug fix, a set of PCH bug fixes, and one patch to fix up compile warnings -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPra+FAAoJEEFnBt12D9kBW3oQALDLW0bneFl+sysynzu9qOAu Qy4BmQjNalPHoZ3PZ6Q5CevrTXJsDwFxkKAS+29melBrPaKpubTPMoqD9yaTjizU yH2MClTLIfOXOQTDwYyILeCq5jcw7uRAyx73cHzAD/JBCTkUgv8HoLKCbhZN4wo5 s/KqZRCEpee8rLHhQa7DFUuJVH7L9zskO2ZwpxgMGOAkDH4aB7OHzlcndB6jST4f dFkMva50pQ8iggCu9tX/zmGbPXWKroSswnrdZVBOEKIj3QJq6h2B9s0u64B4ergZ W57xnCF6AmPWp8YvenMruQRLUUy3KQIMZV5d8fIjvYXpH9TQJE4PR9IWjt+PADqy TVoVR4tjcdYWFJuYhskpvT5dq/x2AX9eyNsTgu9ob8HyUQgzbcTu9zczUF52SiyN ohqjrbKmPINnUrLD1gUkUmUayWt5SOt+hu19rMijqKY/HWQn2rzK5mUIreZeG/Cb aPY1acunbdaNTsIgmIBqLkfSl/ErCYcXwmkulBIZOyUitaMYnZyhbZmgTIeEebTY 2ffX658MTT9cWlHsZ4wfWDynJIpsvTHCVau/oQfurLSO2p6Jb/xA7k34v9mxfAaK gESiK+8T8n0u9RetLSSk7uKNyTqRvDaWsbaB7As0mAd1r8ETAL98N2ZzBv5o+bmF JH4g4IgKNdowY4EqA0Ms =P8v+ -----END PGP SIGNATURE----- Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6 Pull a few more GPIO bug fixes from Grant Likely: "Oops, missed a couple. Here's an updated pull req for GPIO" A set of PCH bug fixes, and one patch to fix up compile warnings * tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6: gpio/exynos: Fix compiler warnings when non-exynos machines are selected gpio: pch9: Use proper flow type handlers
This commit is contained in:
Linus Torvalds
commit
1bc4a5be0a
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@ -230,16 +230,12 @@ static void pch_gpio_setup(struct pch_gpio *chip)
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static int pch_irq_type(struct irq_data *d, unsigned int type)
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{
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u32 im;
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u32 __iomem *im_reg;
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u32 ien;
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u32 im_pos;
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int ch;
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unsigned long flags;
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u32 val;
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int irq = d->irq;
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pch_gpio *chip = gc->private;
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u32 im, im_pos, val;
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u32 __iomem *im_reg;
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unsigned long flags;
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int ch, irq = d->irq;
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ch = irq - chip->irq_base;
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if (irq <= chip->irq_base + 7) {
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@ -270,30 +266,22 @@ static int pch_irq_type(struct irq_data *d, unsigned int type)
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case IRQ_TYPE_LEVEL_LOW:
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val = PCH_LEVEL_L;
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break;
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case IRQ_TYPE_PROBE:
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goto end;
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default:
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dev_warn(chip->dev, "%s: unknown type(%dd)",
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__func__, type);
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goto end;
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goto unlock;
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}
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/* Set interrupt mode */
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im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
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iowrite32(im | (val << (im_pos * 4)), im_reg);
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/* iclr */
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iowrite32(BIT(ch), &chip->reg->iclr);
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/* And the handler */
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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__irq_set_handler_locked(d->irq, handle_level_irq);
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else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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/* IMASKCLR */
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iowrite32(BIT(ch), &chip->reg->imaskclr);
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/* Enable interrupt */
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ien = ioread32(&chip->reg->ien);
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iowrite32(ien | BIT(ch), &chip->reg->ien);
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end:
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unlock:
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spin_unlock_irqrestore(&chip->spinlock, flags);
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return 0;
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}
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@ -313,18 +301,24 @@ static void pch_irq_mask(struct irq_data *d)
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iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
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}
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static void pch_irq_ack(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pch_gpio *chip = gc->private;
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iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
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}
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static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
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{
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struct pch_gpio *chip = dev_id;
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u32 reg_val = ioread32(&chip->reg->istatus);
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int i;
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int ret = IRQ_NONE;
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int i, ret = IRQ_NONE;
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for (i = 0; i < gpio_pins[chip->ioh]; i++) {
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if (reg_val & BIT(i)) {
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dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n",
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__func__, i, irq, reg_val);
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iowrite32(BIT(i), &chip->reg->iclr);
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generic_handle_irq(chip->irq_base + i);
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ret = IRQ_HANDLED;
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}
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@ -343,6 +337,7 @@ static __devinit void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
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gc->private = chip;
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ct = gc->chip_types;
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ct->chip.irq_ack = pch_irq_ack;
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ct->chip.irq_mask = pch_irq_mask;
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ct->chip.irq_unmask = pch_irq_unmask;
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ct->chip.irq_set_type = pch_irq_type;
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@ -357,6 +352,7 @@ static int __devinit pch_gpio_probe(struct pci_dev *pdev,
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s32 ret;
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struct pch_gpio *chip;
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int irq_base;
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u32 msk;
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chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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if (chip == NULL)
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@ -408,8 +404,13 @@ static int __devinit pch_gpio_probe(struct pci_dev *pdev,
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}
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chip->irq_base = irq_base;
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/* Mask all interrupts, but enable them */
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msk = (1 << gpio_pins[chip->ioh]) - 1;
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iowrite32(msk, &chip->reg->imask);
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iowrite32(msk, &chip->reg->ien);
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ret = request_irq(pdev->irq, pch_gpio_handler,
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IRQF_SHARED, KBUILD_MODNAME, chip);
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IRQF_SHARED, KBUILD_MODNAME, chip);
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if (ret != 0) {
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dev_err(&pdev->dev,
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"%s request_irq failed\n", __func__);
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@ -418,8 +419,6 @@ static int __devinit pch_gpio_probe(struct pci_dev *pdev,
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pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
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/* Initialize interrupt ien register */
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iowrite32(0, &chip->reg->ien);
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end:
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return 0;
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@ -452,12 +452,14 @@ static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
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};
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#endif
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#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
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static struct samsung_gpio_cfg exynos_gpio_cfg = {
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.set_pull = exynos_gpio_setpull,
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.get_pull = exynos_gpio_getpull,
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.set_config = samsung_gpio_setcfg_4bit,
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.get_config = samsung_gpio_getcfg_4bit,
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};
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#endif
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#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
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static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
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@ -2123,8 +2125,8 @@ static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
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* uses the above macro and depends on the banks being listed in order here.
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*/
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static struct samsung_gpio_chip exynos4_gpios_1[] = {
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#ifdef CONFIG_ARCH_EXYNOS4
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static struct samsung_gpio_chip exynos4_gpios_1[] = {
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{
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.chip = {
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.base = EXYNOS4_GPA0(0),
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@ -2222,11 +2224,11 @@ static struct samsung_gpio_chip exynos4_gpios_1[] = {
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.label = "GPF3",
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},
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},
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#endif
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};
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#endif
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static struct samsung_gpio_chip exynos4_gpios_2[] = {
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#ifdef CONFIG_ARCH_EXYNOS4
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static struct samsung_gpio_chip exynos4_gpios_2[] = {
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{
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.chip = {
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.base = EXYNOS4_GPJ0(0),
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@ -2367,11 +2369,11 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
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.to_irq = samsung_gpiolib_to_irq,
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},
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},
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#endif
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};
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#endif
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static struct samsung_gpio_chip exynos4_gpios_3[] = {
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#ifdef CONFIG_ARCH_EXYNOS4
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static struct samsung_gpio_chip exynos4_gpios_3[] = {
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{
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.chip = {
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.base = EXYNOS4_GPZ(0),
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@ -2379,8 +2381,8 @@ static struct samsung_gpio_chip exynos4_gpios_3[] = {
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.label = "GPZ",
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},
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},
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#endif
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};
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#endif
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#ifdef CONFIG_ARCH_EXYNOS5
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static struct samsung_gpio_chip exynos5_gpios_1[] = {
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@ -2719,7 +2721,9 @@ static __init int samsung_gpiolib_init(void)
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{
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struct samsung_gpio_chip *chip;
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int i, nr_chips;
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#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS5250)
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void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
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#endif
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int group = 0;
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samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
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@ -2971,6 +2975,7 @@ static __init int samsung_gpiolib_init(void)
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return 0;
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#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS5250)
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err_ioremap4:
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iounmap(gpio_base3);
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err_ioremap3:
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@ -2979,6 +2984,7 @@ err_ioremap2:
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iounmap(gpio_base1);
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err_ioremap1:
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return -ENOMEM;
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#endif
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}
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core_initcall(samsung_gpiolib_init);
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