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amdgpu/pm: Disallow managing power profiles on SRIOV for Sienna Cichlid 

Managing power profiles mode is not allowed in SRIOV mode for Sienna
Cichlid. This patch is adjusting the "pp_power_profile_mode" and
"power_dpm_force_performance_level" accordingly.

Signed-off-by: Danijel Slivka <danijel.slivka@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Danijel Slivka 2022-05-05 16:45:32 +02:00 committed by Alex Deucher
parent cae5c1ab05
commit 1b85257290
1 changed files with 9 additions and 0 deletions
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9
drivers/gpu/drm/amd/pm/amdgpu_pm.c
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@ -2025,6 +2025,8 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
} else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
*states = ATTR_STATE_UNSUPPORTED;
else if (gc_ver == IP_VERSION(10, 3, 0) && amdgpu_sriov_vf(adev))
*states = ATTR_STATE_UNSUPPORTED;
}
switch (gc_ver) {
@ -2038,6 +2040,13 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
dev_attr->store = NULL;
}
break;
case IP_VERSION(10, 3, 0):
if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
amdgpu_sriov_vf(adev)) {
dev_attr->attr.mode &= ~0222;
dev_attr->store = NULL;
}
break;
default:
break;
}